ra8_cgc.c File Reference

Clock Generation Circuit driver – RA8D2 PLL bring-up. More...

#include "ra8_cgc.h"
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_cgc_internal.h"
#include "ra8_cgc_regs.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mrms_regs.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
#include "ra8_register_protection.h"
#include "ra8_sram.h"
#include "ra8_system_regs.h"
#include "ra8_time_constants.h"

Include dependency graph for ra8_cgc.c:

Go to the source code of this file.

Enumerations
enum	ra8_cgc_clock_count_t : uint8_t { k_ra8_cgc_clock_count = 10U }
	Sentinel for the size of the published frequency table. More...
enum	ra8_cgc_spin_t : uint32_t {   k_ra8_cgc_osc_spin_limit = 0x40000UL ,   k_ra8_cgc_pll_spin_limit = 0x40000UL ,   k_ra8_cgc_mrm_spin_limit = 0x40000UL ,   k_ra8_cgc_vscr_spin_limit = 0x40000UL ,   k_ra8_cgc_scik_spin_limit = 0x40000UL }
	Bounded polling limits for oscillator / PLL / wait-state spins. More...
enum	ra8_cgc_dummy_count_t : uint8_t { k_ra8_pfb_flush_dummy_reads = 3U }
	How many dummy reads to issue when flushing the MRAM PFB. More...
enum	ra8_pllcr_bit_t : uint8_t { k_ra8_pllcr_bit_pllstp = 0U }
	Bit positions in PLLCR (PLL stop control). More...
enum	ra8_pllcr_val_t : uint8_t {   k_ra8_pllcr_run = 0x00U ,   k_ra8_pllcr_stop = 0x01U }
	Discrete values written to the 8-bit PLLCR register. More...
enum	ra8_cgc_pll_mul_t : uint16_t {   k_ra8_cgc_pllmul_int_default = 250U ,   k_ra8_cgc_pllmul_quarters = 0U }
	PLL multiplier vocabulary for the EK-RA8D2 quickstart target. More...
enum	ra8_cgc_scickcr_bit_t : uint8_t {   k_ra8_scickcr_sel_pll1r = 0x08U ,   k_ra8_scickcr_cksreq = (1U << 6U) ,   k_ra8_scickcr_cksrdy = (1U << 7U) }
	Bit positions inside SCICKCR (SCICLK clock-source control). More...
enum	ra8_cgc_scickdivcr_t : uint8_t { k_ra8_scickdivcr_div4 = 0x03U }
	Discrete values written to the 8-bit SCICKDIVCR register. More...

Functions
static void	internal_publish_clocks (void)
	Internal helper.
ra8_err_t	ra8_cgc_get_clock_hz (ra8_clock_id_t id, uint32_t *out_hz)
	Query the current frequency of a clock-tree domain.
ra8_err_t	priv_ra8_cgc_wait_oscsf_set (uint8_t bit)
	Bounded poll on a single OSCSF flag becoming set.
ra8_err_t	priv_ra8_cgc_wait_oscsf_clear (uint8_t bit)
	Bounded poll on a single OSCSF flag becoming clear.
static void	internal_clear_pfb (void)
	Step 1: clear the MRAM prefetch buffer before any clock change.
static ra8_err_t	internal_set_vscr_not_high_v (void)
	Step 2: drop core to not-high-voltage range before lifting PLL.
static ra8_err_t	internal_stop_pll1 (void)
	Step 3: stop PLL1 and wait for the PLLSF flag to clear.
static ra8_err_t	internal_program_and_start_pll1 (void)
	Steps 4 + 5: programme PLLCCR / PLLCCR2 then start PLL1.
static ra8_err_t	internal_wait_mrm_freq (volatile uint32_t *reg, uint32_t key, uint32_t freq_mhz)
	Bounded write-and-readback poll on MRCFREQ or MREFREQ.
static ra8_err_t	internal_set_mrm_wait_states (uint32_t mriclk_hz, uint32_t mrpclk_hz)
	Step 6: programme MRMS wait-state frequency latches.
static void	internal_program_dividers (void)
	Step 8: programme SCKDIVCR + SCKDIVCR2 for the FSP-quickstart tree.
static void	internal_set_pfb (void)
	Step 10: re-enable the MRAM prefetch buffer if MRICLK >= 100 MHz.
static ra8_err_t	internal_route_sciclk (void)
	Step 11: route SCICLK = PLL1R / 4 per HUM 9.2.54.
static ra8_err_t	internal_start_main_osc (void)
	Start the main crystal oscillator and wait for stabilisation.
static ra8_err_t	internal_cgc_init_protected (void)
	PRCR-protected core of ra8_cgc_init – runs steps 2..8.
ra8_err_t	ra8_cgc_init (void)
	Configure the clock tree to a safe default.
ra8_err_t	ra8_cgc_use_hoco (void)
	Switch the system clock source to HOCO (20 MHz).
ra8_err_t	ra8_cgc_switch_pll1_target (uint32_t new_cpuclk_hz)
	Retune PLL1 to a new CPUCLK0 target without a full deinit.
ra8_err_t	ra8_cgc_enable_stop_detection (ra8_cgc_ostd_fn_t handler, void *ctx)
	Enable oscillation-stop detection on the main crystal.
ra8_err_t	ra8_cgc_disable_stop_detection (void)
	Disable oscillation-stop detection.
void	ra8_cgc_fake_trigger_stop_detection (void)
	Test helper: invoke the registered OSTD callback.

Variables
static const char *	s_tag = "CGC"
static uint32_t	s_clock_hz [k_ra8_cgc_clock_count]
	Most-recently programmed frequency for each clock-tree domain.
static ra8_cgc_ostd_fn_t	s_ostd_handler = nullptr
	Registered oscillation-stop-detection callback.
static void *	s_ostd_ctx = nullptr
	Stored context passed to s_ostd_handler.
static bool	s_ostd_enabled = false
	true while the stop-detection path is armed.

Detailed Description

Clock Generation Circuit driver – RA8D2 PLL bring-up.

Brings the RA8D2 clock tree from reset defaults (MOCO @ ~8 MHz) up to the EK-RA8D2 quickstart target (CPUCLK0 = 1 GHz, ICLK = 250 MHz). Mirrors the FSP bsp_clocks.c bring-up sequence for RA8 Gen2; on RA8 Gen2 silicon, several non-obvious steps are mandatory and their omission was previously HardFaulting the chip:

1. Flush the MRAM prefetch buffer (MRMS.MRCPFB = 0 + 3 dummy reads). FSP bsp_clocks.c.
2. Drop the core voltage to "not high voltage" range (R_SYSTEM->VSCR.VSCM = 1) and wait for VSCMTSF to clear. FSP bsp_clocks.c. Required before lifting PLL above its boot rate.
3. Stop PLL1 (PLLCR = 1), then poll OSCSF.PLLSF = 0. Without this barrier, PLLCCR / PLLCCR2 writes are silently dropped and read back as zero. FSP bsp_clocks.c.
4. Programme PLLCCR + PLLCCR2 with the new multiplier and output dividers. FSP bsp_clocks.c.
5. Start PLL1 (PLLCR = 0), then poll OSCSF.PLLSF = 1. FSP bsp_clocks.c.
6. Programme MRMS wait-state frequency latches (MRCFREQ for MRICLK, MREFREQ for MRPCLK). The hardware refuses any write whose key byte is wrong, so we spin-poll until readback matches. FSP bsp_clocks.c. This is the MRAM wait-state step – RA8D2 does NOT have legacy MEMWAIT / FLDWAITR / FLWT.
7. Programme the SRAM wait state (SRAMWTSC.WTEN) for the ICLK about to be selected. The SRAM's counterpart to step 6, and just as mandatory: HUM Ch 58.3.7 p 3540 requires a wait cycle above half the rated maximum ICLK, and without it "the operation is not guaranteed" – which on this part means a bit silently dropped from an SRAM read, not a hang (tracker #524 / #499).
8. Programme SCKDIVCR + SCKDIVCR2 for the full divider tree. FSP bsp_clocks.c.
9. Switch SCKSCR to PLL1.

Re-enable the prefetch buffer (MRCPFB = 1) iff MRICLK >= 100 MHz. FSP bsp_clocks.c.

1. Programme SCICKCR + SCICKDIVCR per HUM 9.2.54 so SCI_B's TCLK has a real edge source.

Every protected-register write is wrapped in RA8_PROTECTED_WRITE so the PRCR re-lock always happens, even on early-return paths.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file ra8_cgc.c.

Enumeration Type Documentation

ra8_cgc_clock_count_t

enum ra8_cgc_clock_count_t : uint8_t

Sentinel for the size of the published frequency table.

Enumerator
k_ra8_cgc_clock_count	Number of tracked clock-tree domains.

Definition at line 77 of file ra8_cgc.c.

ra8_cgc_dummy_count_t

enum ra8_cgc_dummy_count_t : uint8_t

How many dummy reads to issue when flushing the MRAM PFB.

FSP bsp_clocks.c issues exactly three dummy reads after writing MRCPFB = 0 to ensure the prefetch buffer is fully flushed before any clock-tree change.

Enumerator
k_ra8_pfb_flush_dummy_reads	Dummy-read count after MRCPFB clear.

Definition at line 171 of file ra8_cgc.c.

ra8_cgc_pll_mul_t

enum ra8_cgc_pll_mul_t : uint16_t

PLL multiplier vocabulary for the EK-RA8D2 quickstart target.

quickstart_ek_ra8d2_ep (ra8_cfg.txt:269) requests x250.00. FSP encodes this as the integer multiplier 250 placed in PLLCCR[16:8] with PLLMULNF[7:6] = 0 (zero quarter-steps).

Enumerator
k_ra8_cgc_pllmul_int_default	Integer multiplier x250.
k_ra8_cgc_pllmul_quarters	Fractional quarter-steps.

Definition at line 201 of file ra8_cgc.c.

ra8_cgc_scickcr_bit_t

enum ra8_cgc_scickcr_bit_t : uint8_t

Bit positions inside SCICKCR (SCICLK clock-source control).

Cited from FSP CMSIS device header R7KA8D2KF_core0.h and HUM 9.2.54 "SCICKCR : SCI Clock Control Register".

Enumerator
k_ra8_scickcr_sel_pll1r	CKSEL = 0x08 selects PLL1R.
k_ra8_scickcr_cksreq	CKSREQ – request switch.
k_ra8_scickcr_cksrdy	CKSRDY – switch acknowledged.

Definition at line 214 of file ra8_cgc.c.

ra8_cgc_scickdivcr_t

enum ra8_cgc_scickdivcr_t : uint8_t

Discrete values written to the 8-bit SCICKDIVCR register.

SCICKDIV[3:0] uses the same code-to-ratio map as PLODIV: code N selects /N+1 for codes 0..5, /8 = 7, /9 = 8, /16 = 15. We pick /4 (code 3) so SCICLK = PLL1R / 4 = 100 MHz, matching FSP quickstart.

Enumerator
k_ra8_scickdivcr_div4	SCICLK divider code for /4.

Definition at line 229 of file ra8_cgc.c.

ra8_cgc_spin_t

enum ra8_cgc_spin_t : uint32_t

Bounded polling limits for oscillator / PLL / wait-state spins.

Enumerator
k_ra8_cgc_osc_spin_limit	Generic OSCSF wait budget.
k_ra8_cgc_pll_spin_limit	PLL stop / start wait budget.
k_ra8_cgc_mrm_spin_limit	MRCFREQ / MREFREQ wait.
k_ra8_cgc_vscr_spin_limit	VSCMTSF wait budget.
k_ra8_cgc_scik_spin_limit	SCICKCR.CKSRDY wait budget.

Definition at line 154 of file ra8_cgc.c.

ra8_pllcr_bit_t

enum ra8_pllcr_bit_t : uint8_t

Bit positions in PLLCR (PLL stop control).

Enumerator
k_ra8_pllcr_bit_pllstp	PLLCR.PLLSTP: 1 stops PLL, 0 runs PLL.

Definition at line 179 of file ra8_cgc.c.

ra8_pllcr_val_t

enum ra8_pllcr_val_t : uint8_t

Discrete values written to the 8-bit PLLCR register.

Enumerator
k_ra8_pllcr_run	Clear PLLSTP -> run PLL.
k_ra8_pllcr_stop	Set PLLSTP -> stop PLL.

Definition at line 187 of file ra8_cgc.c.

Function Documentation

internal_cgc_init_protected()

ra8_err_t internal_cgc_init_protected ( void )

static

PRCR-protected core of ra8_cgc_init – runs steps 2..8.

Splits out the protected register window so ra8_cgc_init stays within the NASA Rule 4 statement budget. Returns the first error encountered (or k_ra8_ok on a clean run).

Returns

ra8_err_t error code from the first failing step, or k_ra8_ok.

Precondition

Caller has flushed the MRAM PFB (internal_clear_pfb).

Caller is single-threaded init context.

Postcondition

On k_ra8_ok the PLL is locked, MRMS wait-state latches are set, SCKDIVCR / SCKDIVCR2 are committed, and SCKSCR points to PLL1.

Note

Not thread-safe.

Since

0.1.0

Return values

k_ra8_ok

Operation succeeded.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 688 of file ra8_cgc.c.

References internal_program_and_start_pll1(), internal_program_dividers(), internal_set_mrm_wait_states(), internal_set_vscr_not_high_v(), internal_start_main_osc(), internal_stop_pll1(), k_ra8_cksel_pll1, k_ra8_fclk_hz, k_ra8_iclk_hz, k_ra8_iclk_max_hz, k_ra8_mriclk_hz, k_ra8_ok, RA8_INTERNAL, ra8_sram_set_wait_state_for_clock(), and ra8_sys_sckscr().

Referenced by ra8_cgc_init().

internal_clear_pfb()

void internal_clear_pfb ( void )

static

Step 1: clear the MRAM prefetch buffer before any clock change.

Mirrors FSP bsp_prv_clear_pfb() (bsp_clocks.c): write MRCPFB = 0 then issue 3 dummy reads to flush the prefetch pipeline. Required before any frequency change per HUM Ch 54.4.3.

Precondition

No code is fetched from MRAM with the PFB enabled afterwards until step 9 re-enables it.

Postcondition

MRCPFB reads back as 0 and the prefetch pipeline is empty.

Note

Not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 269 of file ra8_cgc.c.

References k_ra8_mrcpfb_disable, k_ra8_pfb_flush_dummy_reads, RA8_INTERNAL, and ra8_mrms_mrcpfb().

Referenced by ra8_cgc_init().

internal_program_and_start_pll1()

ra8_err_t internal_program_and_start_pll1 ( void )

static

Steps 4 + 5: programme PLLCCR / PLLCCR2 then start PLL1.

Writes the EK-RA8D2 quickstart values (XTAL=24, /3 in, x250.00, P=/2, Q=/6, R=/5) and starts PLL1. After this returns successfully the PLL is locked at PLL1P = 1 GHz, PLL1Q ~= 333 MHz, PLL1R = 400 MHz.

Predicted register values: PLLCCR = 0xFA02 (PLLMUL=250, PLLMULNF=0, PLSRCSEL=0, PLIDIV=2) PLLCCR2 = 0x0451 (PLODIVR=4, PLODIVQ=5, PLODIVP=1)

Returns

ra8_err_t error code.

Return values

k_ra8_ok	PLL locked, OSCSF.PLLSF == 1.
k_ra8_err_hw_timeout	PLLSF never set within the spin budget.

Precondition

Main XTAL is running and stable (OSCSF.MOSCSF == 1).

PLL1 has been stopped via internal_stop_pll1.

Caller has unlocked PRCR group 0 (CGC).

Postcondition

PLLCR == 0 and OSCSF.PLLSF == 1.

PLLCCR / PLLCCR2 read back as the values written above.

Note

Not thread-safe.

Since

0.1.0

Definition at line 374 of file ra8_cgc.c.

References k_ra8_cgc_pllmul_int_default, k_ra8_cgc_pllmul_quarters, k_ra8_cgc_quarters_per_unit, k_ra8_oscsf_bit_pll1sf, k_ra8_plidiv_div3, k_ra8_pllccr2_shift_plodivp, k_ra8_pllccr2_shift_plodivq, k_ra8_pllccr2_shift_plodivr, k_ra8_pllccr_mask_plidiv, k_ra8_pllccr_mask_quarters, k_ra8_pllccr_shift_plsrcsel, k_ra8_pllccr_shift_quarters, k_ra8_pllcr_run, k_ra8_plodiv_div2, k_ra8_plodiv_div5, k_ra8_plodiv_div6, k_ra8_plsrcsel_main, priv_ra8_cgc_wait_oscsf_set(), RA8_INTERNAL, ra8_sys_pllccr(), ra8_sys_pllccr2(), and ra8_sys_pllcr().

Referenced by internal_cgc_init_protected(), and ra8_cgc_switch_pll1_target().

internal_program_dividers()

void internal_program_dividers ( void )

static

Step 8: programme SCKDIVCR + SCKDIVCR2 for the FSP-quickstart tree.

Predicted register values: SCKDIVCR = 0x32233432 FCK = 0x3 (/8), ICK = 0x2 (/4), PCKE = 0x2 (/4), BCK = 0x3 (/8), PCKA = 0x3 (/8), PCKB = 0x4 (/16), PCKC = 0x3 (/8), PCKD = 0x2 (/4) SCKDIVCR2 = 0x2020 MRICK = 0x2 (/4), NPUCK = 0, CPUCK1 = 0x2 (/4), CPUCK = 0 (/1)

Precondition

PLL1 is locked.

Caller has unlocked PRCR group 0 (CGC).

Postcondition

SCKDIVCR / SCKDIVCR2 read back as the constants written above.

Note

Not thread-safe.

Since

0.1.0

Postcondition

Caller-visible state matches the documented contract.

Definition at line 527 of file ra8_cgc.c.

References k_ra8_clock_div_1, k_ra8_clock_div_16, k_ra8_clock_div_4, k_ra8_clock_div_8, k_ra8_sckdivcr2_cpuclk0_shift, k_ra8_sckdivcr2_cpuclk1_shift, k_ra8_sckdivcr2_mriclk_shift, k_ra8_sckdivcr2_npuclk_shift, k_ra8_sckdivcr_bck_shift, k_ra8_sckdivcr_fck_shift, k_ra8_sckdivcr_ick_shift, k_ra8_sckdivcr_pcka_shift, k_ra8_sckdivcr_pckb_shift, k_ra8_sckdivcr_pckc_shift, k_ra8_sckdivcr_pckd_shift, k_ra8_sckdivcr_pcke_shift, RA8_INTERNAL, ra8_sys_sckdivcr(), and ra8_sys_sckdivcr2().

Referenced by internal_cgc_init_protected().

internal_publish_clocks()

void internal_publish_clocks ( void )

static

Internal helper.

See implementation.

Precondition

Module state is consistent.

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Caller-visible state matches the documented contract.

Note

Not thread-safe unless documented otherwise.

Since

0.1.0

Definition at line 118 of file ra8_cgc.c.

References k_ra8_clock_id_cpuclk0, k_ra8_clock_id_cpuclk1, k_ra8_clock_id_fclk, k_ra8_clock_id_iclk, k_ra8_clock_id_mriclk, k_ra8_clock_id_pclka, k_ra8_clock_id_pclkb, k_ra8_clock_id_pclkc, k_ra8_clock_id_pclkd, k_ra8_clock_id_pclke, k_ra8_cpuclk0_hz, k_ra8_cpuclk1_hz, k_ra8_fclk_hz, k_ra8_iclk_hz, k_ra8_mriclk_hz, k_ra8_pclka_hz, k_ra8_pclkb_hz, k_ra8_pclkc_hz, k_ra8_pclkd_hz, k_ra8_pclke_hz, RA8_INTERNAL, and s_clock_hz.

Referenced by ra8_cgc_init(), and ra8_cgc_switch_pll1_target().

internal_route_sciclk()

ra8_err_t internal_route_sciclk ( void )

static

Step 11: route SCICLK = PLL1R / 4 per HUM 9.2.54.

Without this, SCI_B's TCLK is left at the reset default (MOCO @ ~8 MHz) and the bit-shift state machine never advances even though register-level writes look correct. The procedure is:

1. Set CKSREQ = 1, poll until CKSRDY = 1 (SCICLK gated, switchable).
2. Programme SCICKDIVCR + SCICKCR.CKSEL while CKSREQ stays asserted.
3. Clear CKSREQ, poll until CKSRDY = 0 (new clock active).

Precondition

PLL1 is locked and PRCR is unlocked (caller responsibility).

Postcondition

SCICKCR.CKSEL = PLL1R, SCICKDIVCR = /4. SCICLK ~= 100 MHz.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	SCICLK switched.
k_ra8_err_hw_timeout	CKSRDY transition stuck.

Note

Not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 606 of file ra8_cgc.c.

References k_ra8_cgc_scik_spin_limit, k_ra8_ok, k_ra8_scickcr_cksrdy, k_ra8_scickcr_cksreq, k_ra8_scickcr_sel_pll1r, k_ra8_scickdivcr_div4, ra8_hw_wait_flag_clear8(), ra8_hw_wait_flag_set8(), RA8_INTERNAL, ra8_sys_scickcr(), and ra8_sys_scickdivcr().

Referenced by ra8_cgc_init().

internal_set_mrm_wait_states()

ra8_err_t internal_set_mrm_wait_states ( uint32_t mriclk_hz, uint32_t mrpclk_hz )

static

Step 6: programme MRMS wait-state frequency latches.

Mirrors FSP bsp_prv_set_wait_state_frequency() for RA8 Gen2 (bsp_clocks.c). Writes the MRICLK rate (rounded up to MHz) to MRCFREQ and the MRPCLK rate to MREFREQ, in poll-until-readback loops to handle the key-byte filter.

Parameters

[in]	mriclk_hz	MRICLK rate in Hz.
[in]	mrpclk_hz	MRPCLK rate in Hz.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Both registers latched.
k_ra8_err_hw_timeout	MRCFREQ or MREFREQ never readback-matched.

Precondition

PLL1 is locked and providing the new clock source.

Caller has flushed the PFB via internal_clear_pfb.

Postcondition

MRCFREQ reads mriclk_hz / 1MHz (or 0 if below 1 MHz).

MREFREQ reads mrpclk_hz / 1MHz (or 0 if below 1 MHz).

Note

Not thread-safe.

Since

0.1.0

Definition at line 484 of file ra8_cgc.c.

References internal_wait_mrm_freq(), k_ra8_cgc_hz_per_mhz, k_ra8_cgc_mr_min_hz, k_ra8_mrcfreq_key, k_ra8_mrefreq_key, k_ra8_ok, RA8_INTERNAL, ra8_mrms_mrcfreq(), and ra8_mrms_mrefreq().

Referenced by internal_cgc_init_protected().

internal_set_pfb()

void internal_set_pfb ( void )

static

Step 10: re-enable the MRAM prefetch buffer if MRICLK >= 100 MHz.

Mirrors FSP bsp_prv_set_pfb() (bsp_clocks.c). Reading MRCFREQ confirms what the wait-state stage actually latched, then the buffer is enabled only above the 100 MHz threshold required by HUM Ch 54.4.3.

Precondition

internal_set_mrm_wait_states has succeeded.

Postcondition

MRCPFB == 1 iff MRCFREQ >= 100 (MHz).

Note

Not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 570 of file ra8_cgc.c.

References k_ra8_mrcpfb_enable, k_ra8_mrcpfb_threshold_mhz, RA8_INTERNAL, ra8_mrms_mrcfreq(), and ra8_mrms_mrcpfb().

Referenced by ra8_cgc_init().

internal_set_vscr_not_high_v()

ra8_err_t internal_set_vscr_not_high_v ( void )

static

Step 2: drop core to not-high-voltage range before lifting PLL.

FSP bsp_clocks.c writes VSCR.VSCM = 1 then waits VSCMTSF to clear. Required on RA8 Gen2 silicon before raising PLL above its boot rate; without it, the PLL writes succeed but the chip browns out as soon as CPUCLK0 lifts past the high-voltage threshold.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Voltage range switched.
k_ra8_err_hw_timeout	VSCMTSF stayed set past the spin budget.

Precondition

Caller has unlocked PRCR group 0 (CGC).

Postcondition

VSCR.VSCM = 1 and VSCMTSF = 0.

Note

Not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 303 of file ra8_cgc.c.

References k_ra8_cgc_vscr_spin_limit, k_ra8_vscr_bit_vscm, k_ra8_vscr_bit_vscmtsf, ra8_hw_wait_flag_clear32(), RA8_INTERNAL, and ra8_sys_vscr().

Referenced by internal_cgc_init_protected().

internal_start_main_osc()

ra8_err_t internal_start_main_osc ( void )

static

Start the main crystal oscillator and wait for stabilisation.

Clears MOSCCR.MOSTP to start the crystal, then polls OSCSF.MOSCSF until set. The MOSCWTCR wait-count was committed earlier in the boot path; we leave it unchanged here.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Main XTAL stable.
k_ra8_err_hw_timeout	MOSCSF never set within the spin budget.

Precondition

EK-RA8D2 24 MHz crystal is populated.

Postcondition

OSCSF.MOSCSF == 1 and MOSCCR.MOSTP == 0.

Note

Not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Postcondition

Caller-visible state matches the documented contract.

Definition at line 652 of file ra8_cgc.c.

References k_ra8_moscr_mostp_mask, k_ra8_moscwtcr_2_to_16_cycles, k_ra8_oscsf_bit_moscsf, k_ra8_sys_off_moscr, k_ra8_system_base_addr, priv_ra8_cgc_wait_oscsf_set(), RA8_INTERNAL, and ra8_sys_moscwtcr().

Referenced by internal_cgc_init_protected().

internal_stop_pll1()

ra8_err_t internal_stop_pll1 ( void )

static

Step 3: stop PLL1 and wait for the PLLSF flag to clear.

FSP bsp_clocks.c. Without polling PLLSF=0 here, the subsequent PLLCCR / PLLCCR2 writes are silently dropped (they read back as 0). This was the missing barrier in the previous driver.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	PLL stopped, OSCSF.PLLSF == 0.
k_ra8_err_hw_timeout	PLLSF stayed set past the spin budget.

Precondition

Caller has unlocked PRCR group 0 (CGC).

CPU is currently clocked from MOCO / HOCO / Main (not PLL1).

Postcondition

PLLCR == 1 and OSCSF.PLLSF == 0.

Note

Not thread-safe.

Since

0.1.0

Postcondition

Caller-visible state matches the documented contract.

Definition at line 337 of file ra8_cgc.c.

References k_ra8_oscsf_bit_pll1sf, k_ra8_pllcr_stop, priv_ra8_cgc_wait_oscsf_clear(), RA8_INTERNAL, and ra8_sys_pllcr().

Referenced by internal_cgc_init_protected(), and ra8_cgc_switch_pll1_target().

internal_wait_mrm_freq()

ra8_err_t internal_wait_mrm_freq ( volatile uint32_t * reg, uint32_t key, uint32_t freq_mhz )

static

Bounded write-and-readback poll on MRCFREQ or MREFREQ.

The MRMS frequency latches accept a write only when the upper byte matches the per-register key (0x1E for MRCFREQ, 0xE1 for MREFREQ). FSP loops the write until the readback matches the freq_mhz payload (see bsp_clocks.c). We wrap the same pattern with a bounded spin so a wedged register reports k_ra8_err_hw_timeout instead of hanging forever.

Parameters

[in,out]	reg	Pointer to MRCFREQ or MREFREQ.
[in]	key	Per-register key (k_ra8_mrcfreq_key etc.).
[in]	freq_mhz	Desired clock rate in MHz.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Readback matches freq_mhz.
k_ra8_err_hw_timeout	Readback never matched.

Precondition

reg is non-null and points at MRCFREQ or MREFREQ.

Caller is single-threaded init context.

Postcondition

On k_ra8_ok return, *reg reads back as freq_mhz.

Note

Not thread-safe.

Since

0.1.0

Postcondition

Caller-visible state matches the documented contract.

Definition at line 437 of file ra8_cgc.c.

References k_ra8_cgc_mrm_spin_limit, k_ra8_err_hw_timeout, and k_ra8_ok.

Referenced by internal_set_mrm_wait_states().

priv_ra8_cgc_wait_oscsf_clear()

ra8_err_t priv_ra8_cgc_wait_oscsf_clear

(

uint8_t

bit

)

Bounded poll on a single OSCSF flag becoming clear.

Shared between the core PLL1 bring-up (ra8_cgc.c) and the PLL2 path (ra8_cgc_usb.c). Spins up to k_ra8_cgc_pll_spin_limit iterations.

Parameters

[in]

bit

OSCSF bit number to wait on.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Flag observed clear.
k_ra8_err_hw_timeout	Spin limit exhausted.

Precondition

The associated oscillator / PLL has just been stopped.

Caller is single-threaded init context.

Postcondition

On k_ra8_ok return, the polled bit reads as 0.

Iteration count is bounded.

Note

Not thread-safe.

Since

0.1.0

Definition at line 243 of file ra8_cgc.c.

References k_ra8_cgc_pll_spin_limit, ra8_hw_wait_flag_clear8(), and ra8_sys_oscsf().

Referenced by internal_pll2_program_protected(), and internal_stop_pll1().

priv_ra8_cgc_wait_oscsf_set()

ra8_err_t priv_ra8_cgc_wait_oscsf_set

(

uint8_t

bit

)

Bounded poll on a single OSCSF flag becoming set.

Shared between the core PLL1 bring-up (ra8_cgc.c) and the PLL2 / USB paths (ra8_cgc_usb.c). Spins up to k_ra8_cgc_osc_spin_limit iterations.

Parameters

[in]

bit

OSCSF bit number to wait on (e.g. k_ra8_oscsf_bit_pll1sf).

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Flag observed set.
k_ra8_err_hw_timeout	Spin limit exhausted.

Precondition

The associated oscillator / PLL has been started.

Caller is single-threaded init context.

Postcondition

On k_ra8_ok return, the polled bit reads as 1.

Iteration count is bounded.

Note

Not thread-safe.

Since

0.1.0

Definition at line 233 of file ra8_cgc.c.

References k_ra8_cgc_osc_spin_limit, ra8_hw_wait_flag_set8(), and ra8_sys_oscsf().

Referenced by internal_pll2_program_protected(), internal_program_and_start_pll1(), internal_start_main_osc(), priv_ra8_cgc_ensure_hoco_running_for_usb_ck(), ra8_cgc_usbfs_clock_enable(), ra8_cgc_usbhs_pll_enable(), and ra8_cgc_use_hoco().

ra8_cgc_disable_stop_detection()

ra8_err_t ra8_cgc_disable_stop_detection ( void )

nodiscard

Disable oscillation-stop detection.

Returns

ra8_err_t error code.

Return values

k_ra8_ok

Detector disabled.

Precondition

IRQs masked or single-threaded init context.

Postcondition

OSTDCR.OSTDE is clear.

Previously-registered callback is cleared.

Note

Thread safety: not thread-safe.

Since

0.1.0

Definition at line 874 of file ra8_cgc.c.

References k_ra8_ok, ra8_log_info, s_ostd_ctx, s_ostd_enabled, s_ostd_handler, and s_tag.

ra8_cgc_enable_stop_detection()

ra8_err_t ra8_cgc_enable_stop_detection ( ra8_cgc_ostd_fn_t handler, void * ctx )

nodiscard

Enable oscillation-stop detection on the main crystal.

Programmes OSTDCR to enable the OST detector and installs a callback that fires when the OSTDSR flag is set (oscillator has stopped unexpectedly). The callback runs from the CGC interrupt handler after the driver clears the latched flag.

Parameters

[in]	handler	Callback invoked on oscillation-stop event. Must not be NULL.
[in]	ctx	Stored context passed to the callback.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Detector armed.
k_ra8_err_null_ptr	handler was NULL.

Precondition

ra8_cgc_init has been called.

Postcondition

OSTDCR.OSTDE is set.

Callback will fire on the next detected stop event.

Note

Thread safety: not thread-safe.

Since

0.1.0

Definition at line 857 of file ra8_cgc.c.

References k_ra8_err_null_ptr, k_ra8_ok, ra8_log_info, s_ostd_ctx, s_ostd_enabled, s_ostd_handler, and s_tag.

ra8_cgc_fake_trigger_stop_detection()

void ra8_cgc_fake_trigger_stop_detection

(

void

)

Test helper: invoke the registered OSTD callback.

Unit tests call this to simulate a CGC oscillation-stop interrupt firing, verifying that the callback + context are correctly stored and that OSTDSR is cleared before the handler runs. Target builds use the real ICU / NVIC path plumbed through ra8_isr_dispatch instead.

Precondition

ra8_cgc_enable_stop_detection has been called.

Postcondition

OSTDSR is cleared.

The registered callback ran exactly once.

Note

Thread safety: not thread-safe.

Since

0.1.0

Precondition

Module state is consistent.

Definition at line 883 of file ra8_cgc.c.

References s_ostd_ctx, s_ostd_enabled, and s_ostd_handler.

ra8_cgc_get_clock_hz()

ra8_err_t ra8_cgc_get_clock_hz ( ra8_clock_id_t id, uint32_t * out_hz )

nodiscard

Query the current frequency of a clock-tree domain.

Returns the value last programmed by ra8_cgc_init() (or the reset default MOCO value if ra8_cgc_init() has not yet run). Drivers that need to compute baud rates or sampling periods should always go through this function rather than hard-coding values from ra8_time_constants.h.

Parameters

[in]	id	Clock identifier.
[out]	out_hz	On success, current frequency in Hz.

Returns

k_ra8_ok on success, k_ra8_err_invalid_arg if out_hz is NULL or id is out of range.

Since

0.1.0

Definition at line 132 of file ra8_cgc.c.

References k_ra8_err_invalid_arg, k_ra8_err_null_ptr, k_ra8_ok, and s_clock_hz.

Referenced by adc_diag_setup_or_halt(), al_setup_or_halt(), app_bringup_clocks(), blc_setup_or_halt(), bm_setup_or_halt(), bs_setup_or_halt(), c6_fwver_setup_or_halt(), c6_hosted_setup_or_halt(), c6_join_setup_or_halt(), c6_probe_clocks_or_halt(), c6_wifi_setup_or_halt(), cam_bringup(), cdc_setup_or_halt(), ch_setup_or_halt(), cm_bringup_clocks(), combo_clocks_or_halt(), crc_demo_setup_or_halt(), demo_setup_or_halt(), demo_setup_or_halt(), dfu_setup_or_halt(), drw_blend_setup_or_halt(), drw_demo_setup_or_halt(), dtc_arm_setup_or_halt(), dtc_demo_setup_or_halt(), ec_setup_or_halt(), ef_setup_or_halt(), ehb_setup_or_halt(), eoh_setup_or_halt(), eop_setup_or_halt(), ep_bringup_core(), ep_setup_or_halt(), er_try_load_font(), erb_setup_or_halt(), es_setup_or_halt(), est_setup_or_halt(), etoc_setup_or_halt(), ez_bringup_clocks(), fileops_setup_or_halt(), flash_journal_setup_or_halt(), fs_fmt_setup_or_halt(), gh_setup_or_halt(), gpt_ecc_clocks_or_halt(), gptp_setup_or_halt(), hid_setup_or_halt(), i3c_demo_clocks_or_halt(), iic_setup_or_halt(), imp_setup_or_halt(), imu_demo_clocks_or_halt(), internal_acmphs_demo_setup(), internal_agt_periodic_setup_or_halt(), internal_audio_loopback_init_clocks_and_led(), internal_bkup_demo_setup_or_halt(), internal_can_demo_setup_or_halt(), internal_canfd_demo_setup_or_halt(), internal_canfd_filter_setup_or_halt(), internal_clock_check_verify_all(), internal_clocks_or_halt(), internal_clocks_or_halt(), internal_dac_b_demo_setup_or_halt(), internal_dac_demo_setup_or_halt(), internal_demo_clocks_or_halt(), internal_demo_setup_or_halt(), internal_dotf_demo_setup_or_halt(), internal_eth_loopback_setup_or_halt(), internal_gpio_demo_setup_or_halt(), internal_gpt_3p_demo_setup_or_halt(), internal_gpt_irq_demo_setup_or_halt(), internal_gpt_pwm_demo_setup_or_halt(), internal_icu_extint_demo_setup_or_halt(), internal_iic_peripheral_setup_or_halt(), internal_kat_setup_or_halt(), internal_kint_demo_setup_or_halt(), internal_lcd_bringup_clocks(), internal_lpm_deep_setup_or_halt(), internal_lpm_demo_setup_or_halt(), internal_lpm_dpsby1_setup_or_halt(), internal_lpm_dpsby2_setup_or_halt(), internal_lpm_dpsby3_setup_or_halt(), internal_lpm_swstd_setup_or_halt(), internal_lpm_wake_setup_or_halt(), internal_lus_setup_or_halt(), internal_lvd_demo_setup_or_halt(), internal_mecc_setup_or_halt(), internal_motor_3phase_init_clocks_and_led(), internal_mpu_simple_setup_or_halt(), internal_pc_setup_or_halt(), internal_pdg_demo_setup_or_halt(), internal_poeg_demo_setup_or_halt(), internal_program_data_phase(), internal_rc_setup_or_halt(), internal_rcs_setup_or_halt(), internal_rng_demo_setup_or_halt(), internal_rtc_demo_setup_or_halt(), internal_sd_demo_setup_or_halt(), internal_setup_or_halt(), internal_ssie_loop_setup_or_halt(), internal_tc_setup_or_halt(), internal_td_setup_or_halt(), internal_uart_hello_setup_or_halt(), internal_usb_audio_clocks_or_halt(), internal_wdt_demo_setup_or_halt(), ipc_demo_setup_or_halt(), iu_setup_or_halt(), iv_setup_or_halt(), kat_setup_or_halt(), kb_setup_or_halt(), l3_setup_or_halt(), lcd_bringup_clocks(), lin_hil_setup_or_halt(), lk_setup_or_halt(), lpi_setup_or_halt(), main(), mem_setup_or_halt(), mg_bringup_clocks(), microsd_setup_or_halt(), mlun_setup_or_halt(), modem_clocks_or_halt(), ospirw_setup_or_halt(), pp_demo_clocks_or_halt(), priv_ra8_esp_hosted_rtos_init(), ra8_board_camera_xclk_start(), ra8_board_touch_open(), ra8_board_uart_console_init(), ra8_canfd_set_bitrate(), ra8_nsc_cgc_get_clock_hz(), ra8_pwr_get_clock_hz(), ra8_threadx_systick_retune(), riic_target_clocks_or_halt(), rot_setup_or_halt(), sb_setup_or_halt(), scb_demo_setup_or_halt(), sd_demo_setup_or_halt(), sd_setup_or_halt(), sdhi_card_setup_or_halt(), sdhi_demo_setup_or_halt(), sdmsc_setup_or_halt(), sdram_demo_setup_or_halt(), selftest_setup_or_halt(), sfr_bringup_clocks(), sh_sd_mount(), sh_setup_or_halt(), tb_setup_or_halt(), timer_demo_setup_or_halt(), tsn_setup_or_halt(), tx_application_define(), uart_irq_setup_or_halt(), wa_setup_or_halt(), wc_setup_or_halt(), wd_setup_or_halt(), wdt_rr_setup_or_halt(), wdt_window_demo_setup_or_halt(), webp_demo_setup_or_halt(), wifi_hal_setup_or_halt(), wk_setup_or_halt(), and wlun_setup_or_halt().

ra8_cgc_init()

ra8_err_t ra8_cgc_init ( void )

nodiscard

Configure the clock tree to a safe default.

For v0.x bring-up this function is intentionally a no-op: the firmware runs on MOCO (8 MHz) until a real PLL bring-up lands. Returning k_ra8_ok lets main() keep the pattern:

ra8_infrastructure_init();
RA8_ERROR_CHECK(ra8_cgc_init());
// ... drivers ...

which will automatically start using the real implementation once this function is filled out.

Returns

Always k_ra8_ok today. Will return clock-setup errors once a real PLL routine is wired in.

Since

0.1.0

Definition at line 727 of file ra8_cgc.c.

References internal_cgc_init_protected(), internal_clear_pfb(), internal_publish_clocks(), internal_route_sciclk(), internal_set_pfb(), k_ra8_ok, k_ra8_prcr_unlock_cgc, ra8_log_error_val, ra8_log_info, RA8_PROTECTED_WRITE, and s_tag.

Referenced by adc_diag_setup_or_halt(), al_setup_or_halt(), app_bringup_clocks(), app_launch_hil_console_init(), app_setup(), app_shell_hil_console_init(), blc_setup_or_halt(), bm_setup_or_halt(), bs_setup_or_halt(), c6_fwver_setup_or_halt(), c6_hosted_setup_or_halt(), c6_join_setup_or_halt(), c6_probe_clocks_or_halt(), c6_wifi_setup_or_halt(), cache_hal_setup(), cache_mpu_setup(), cam_bringup(), cdc_setup_or_halt(), ch_setup_or_halt(), cm_bringup_clocks(), combo_clocks_or_halt(), crc_demo_setup_or_halt(), demo_setup_or_halt(), demo_setup_or_halt(), dfu_setup_or_halt(), drw_blend_setup_or_halt(), drw_demo_setup_or_halt(), dtc_arm_setup_or_halt(), dtc_coh_setup_or_halt(), dtc_demo_setup_or_halt(), dualcore_bg_hil_console_init(), dualcore_mailbox_hil_console_init(), ec_setup_or_halt(), ef_setup_or_halt(), ehb_setup_or_halt(), eoh_setup_or_halt(), eop_setup_or_halt(), ep_bringup_core(), ep_setup_or_halt(), erb_setup_or_halt(), es_setup_or_halt(), est_setup_or_halt(), etoc_setup_or_halt(), ez_bringup_clocks(), fc_setup_or_halt(), fileops_setup_or_halt(), flash_journal_setup_or_halt(), fs_fmt_setup_or_halt(), gh_setup_or_halt(), gpt_ecc_clocks_or_halt(), gptp_setup_or_halt(), hid_setup_or_halt(), i3c_demo_clocks_or_halt(), iic_setup_or_halt(), imp_setup_or_halt(), imu_demo_clocks_or_halt(), internal_acmphs_demo_setup(), internal_agt_periodic_setup_or_halt(), internal_audio_loopback_init_clocks_and_led(), internal_bkup_demo_setup_or_halt(), internal_can_demo_setup_or_halt(), internal_canfd_demo_setup_or_halt(), internal_canfd_filter_setup_or_halt(), internal_clocks_or_halt(), internal_clocks_or_halt(), internal_console_init(), internal_dac_b_demo_setup_or_halt(), internal_dac_demo_setup_or_halt(), internal_demo_clocks_or_halt(), internal_demo_setup_or_halt(), internal_dotf_demo_setup_or_halt(), internal_eth_loopback_setup_or_halt(), internal_gpio_demo_setup_or_halt(), internal_gpt_3p_demo_setup_or_halt(), internal_gpt_irq_demo_setup_or_halt(), internal_gpt_pwm_demo_setup_or_halt(), internal_icu_extint_demo_setup_or_halt(), internal_iic_peripheral_setup_or_halt(), internal_kat_setup_or_halt(), internal_kint_demo_setup_or_halt(), internal_lcd_bringup_clocks(), internal_lpm_deep_setup_or_halt(), internal_lpm_demo_setup_or_halt(), internal_lpm_dpsby1_setup_or_halt(), internal_lpm_dpsby2_setup_or_halt(), internal_lpm_dpsby3_setup_or_halt(), internal_lpm_swstd_setup_or_halt(), internal_lpm_wake_setup_or_halt(), internal_lus_setup_or_halt(), internal_lvd_demo_setup_or_halt(), internal_mecc_setup_or_halt(), internal_motor_3phase_init_clocks_and_led(), internal_mpu_simple_setup_or_halt(), internal_npu_infer_setup_or_halt(), internal_npu_smoke_setup_or_halt(), internal_npu_vela_setup_or_halt(), internal_pc_setup_or_halt(), internal_pdg_demo_setup_or_halt(), internal_poeg_demo_setup_or_halt(), internal_rc_setup_or_halt(), internal_rcs_setup_or_halt(), internal_rng_demo_setup_or_halt(), internal_rtc_demo_setup_or_halt(), internal_sd_demo_setup_or_halt(), internal_setup_or_halt(), internal_ssie_loop_setup_or_halt(), internal_tc_setup_or_halt(), internal_td_setup_or_halt(), internal_uart_hello_setup_or_halt(), internal_usb_audio_clocks_or_halt(), internal_wdt_demo_setup_or_halt(), ipc_demo_setup_or_halt(), iu_setup_or_halt(), iv_setup_or_halt(), kat_setup_or_halt(), kb_setup_or_halt(), l3_setup_or_halt(), lcd_bringup_clocks(), lin_hil_setup_or_halt(), lk_setup_or_halt(), lpi_setup_or_halt(), main(), mem_setup_or_halt(), mg_bringup_clocks(), microsd_setup_or_halt(), mlun_setup_or_halt(), modem_clocks_or_halt(), mpu_boot_setup(), ospirw_setup_or_halt(), pp_demo_clocks_or_halt(), ra8_board_clocks_init(), riic_target_clocks_or_halt(), rot_setup_or_halt(), sb_setup_or_halt(), scb_demo_setup_or_halt(), sd_demo_setup_or_halt(), sd_setup_or_halt(), sdhi_card_setup_or_halt(), sdhi_demo_setup_or_halt(), sdmsc_setup_or_halt(), sdram_demo_setup_or_halt(), selftest_setup_or_halt(), sfr_bringup_clocks(), sh_setup_or_halt(), SystemInit(), tb_setup_or_halt(), timer_demo_setup_or_halt(), tsn_setup_or_halt(), uart_irq_setup_or_halt(), wa_setup_or_halt(), wc_setup_or_halt(), wd_setup_or_halt(), wdt_rr_setup_or_halt(), wdt_window_demo_setup_or_halt(), webp_demo_setup_or_halt(), wifi_hal_setup_or_halt(), wk_setup_or_halt(), and wlun_setup_or_halt().

ra8_cgc_switch_pll1_target()

ra8_err_t ra8_cgc_switch_pll1_target ( uint32_t new_cpuclk_hz )

nodiscard

Retune PLL1 to a new CPUCLK0 target without a full deinit.

Walks through the safe transition sequence from HUM Ch 9.2 (p 317):

1. Switch SCKSCR to MOCO so the CPU runs on a simple source while PLL1 is being reprogrammed.
2. Stop PLL1 via PLLCR.PLLSTP.
3. Compute the new PLLCCR / PLLCCR2 integer + fractional multipliers from new_cpuclk_hz.
4. Start PLL1 and wait for OSCSF.PLL1SF.
5. Switch SCKSCR back to PLL1.
6. Republish the clock-tree frequencies so subsequent ra8_cgc_get_clock_hz calls see the new value.

Parameters

[in]

new_cpuclk_hz

Target CPUCLK0 frequency in Hz. Must be a multiple of the crystal divided by 32 (the PLLCCR2 fractional step).

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Clock switched to the new target.
k_ra8_err_invalid_arg	new_cpuclk_hz is 0.
k_ra8_err_hw_timeout	PLL lock or MOCO wait timed out.

Precondition

ra8_cgc_init has been called (PLL1 is the current source).

IRQs masked or single-threaded init context.

Postcondition

On success, SCKSCR == PLL1 and the reported CPUCLK0 frequency matches new_cpuclk_hz to within the PLL2 fractional resolution.

Note

Thread safety: not thread-safe.

Since

0.1.0

Definition at line 814 of file ra8_cgc.c.

References internal_program_and_start_pll1(), internal_publish_clocks(), internal_stop_pll1(), k_ra8_cksel_moco, k_ra8_cksel_pll1, k_ra8_clock_id_cpuclk0, k_ra8_err_invalid_arg, k_ra8_ok, k_ra8_prcr_unlock_cgc, ra8_log_error_val, ra8_log_info_val, RA8_PROTECTED_WRITE, ra8_sys_sckscr(), s_clock_hz, and s_tag.

ra8_cgc_use_hoco()

ra8_err_t ra8_cgc_use_hoco ( void )

nodiscard

Switch the system clock source to HOCO (20 MHz).

Starts the HOCO if it is stopped, waits for it to stabilise, then writes k_ra8_cksel_hoco to SCKSCR. Requires a PRCR unlock around the SCKSCR write.

Returns

ra8_err_t error code.

Return values

k_ra8_ok	Clock switched.
k_ra8_err_hw_timeout	HOCO failed to report ready within the timeout window.

Since

0.1.0

Definition at line 763 of file ra8_cgc.c.

References k_ra8_cksel_hoco, k_ra8_hococr_hcstp, k_ra8_ok, k_ra8_oscsf_bit_hocosf, k_ra8_prcr_unlock_cgc, priv_ra8_cgc_wait_oscsf_set(), ra8_log_info, RA8_PROTECTED_WRITE, ra8_sys_hococr(), ra8_sys_sckscr(), and s_tag.

Variable Documentation

s_clock_hz

uint32_t s_clock_hz[k_ra8_cgc_clock_count]

static

Initial value:

                           = {
  [k_ra8_clock_id_cpuclk0] = k_ra8_moco_hz,
  [k_ra8_clock_id_cpuclk1] = k_ra8_moco_hz,
  [k_ra8_clock_id_iclk]    = k_ra8_moco_hz,
  [k_ra8_clock_id_pclka]   = k_ra8_moco_hz,
  [k_ra8_clock_id_pclkb]   = k_ra8_moco_hz,
  [k_ra8_clock_id_pclkc]   = k_ra8_moco_hz,
  [k_ra8_clock_id_pclkd]   = k_ra8_moco_hz,
  [k_ra8_clock_id_pclke]   = k_ra8_moco_hz,
  [k_ra8_clock_id_fclk]    = k_ra8_moco_hz,
  [k_ra8_clock_id_mriclk]  = k_ra8_moco_hz,
}

Most-recently programmed frequency for each clock-tree domain.

Reset default is MOCO (~8 MHz). ra8_cgc_init() updates the table after the PLL has locked and the new dividers are committed, so ra8_cgc_get_clock_hz() always returns the current rate.

Note

Mutated only from CGC bring-up paths; callers must not write.

Warning

Direct modification breaks every BRR / sample-rate calculator downstream.

Since

0.1.0

Definition at line 95 of file ra8_cgc.c.

Referenced by internal_publish_clocks(), ra8_cgc_get_clock_hz(), and ra8_cgc_switch_pll1_target().

s_ostd_ctx

void* s_ostd_ctx = nullptr

static

Stored context passed to s_ostd_handler.

Note

Mutated only via the OSTD enable/disable pair.

Since

0.1.0

Definition at line 804 of file ra8_cgc.c.

Referenced by ra8_cgc_disable_stop_detection(), ra8_cgc_enable_stop_detection(), and ra8_cgc_fake_trigger_stop_detection().

s_ostd_enabled

bool s_ostd_enabled = false

static

true while the stop-detection path is armed.

Note

Mutated only via the OSTD enable/disable pair.

Since

0.1.0

Definition at line 812 of file ra8_cgc.c.

Referenced by ra8_cgc_disable_stop_detection(), ra8_cgc_enable_stop_detection(), and ra8_cgc_fake_trigger_stop_detection().

s_ostd_handler

ra8_cgc_ostd_fn_t s_ostd_handler = nullptr

static

Registered oscillation-stop-detection callback.

Note

Mutated only via ra8_cgc_enable_stop_detection / ra8_cgc_disable_stop_detection.

Warning

Direct modification breaks the disarm path.

Since

0.1.0

Definition at line 796 of file ra8_cgc.c.

Referenced by ra8_cgc_disable_stop_detection(), ra8_cgc_enable_stop_detection(), and ra8_cgc_fake_trigger_stop_detection().

s_tag

const char* s_tag = "CGC"

static

Definition at line 71 of file ra8_cgc.c.