ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
Loading...
Searching...
No Matches
main.c
Go to the documentation of this file.
1
40
41#include <stdint.h>
42
43#include "ra8_attributes.h"
44#include "ra8_board_ek_ra8d2.h"
45#include "ra8_boot_entry.h"
46#include "ra8_cgc.h"
47#include "ra8_check.h"
48#include "ra8_err.h"
49#include "ra8_isr.h"
50#include "ra8_mstp.h"
51#include "ra8_pdg.h"
52#include "ra8_time.h"
53
55static const char* s_tag = "pdg_demo";
56
58typedef enum : uint32_t {
59 k_pdg_demo_baud = 115200U,
62
64typedef enum : uint8_t {
69
71static const uint8_t s_pdg_demo_ok_msg[] = "pdg: dll=on ch0=on delay=0x40 cfg=ok\r\n";
72static const uint8_t s_pdg_demo_bad_msg[] = "pdg: cfg=BAD\r\n";
73
80volatile uint32_t g_pdg_cfg_ok = 0U;
81
88volatile uint32_t g_pdg_delay_readback = 0U;
89
96volatile uint32_t g_pdg_dll = 0U;
97
104volatile uint32_t g_pdg_heartbeat = 0U;
105
120{
121 while (1) {
122 __asm__ volatile("wfi");
123 }
124}
125
165
189{
190 const ra8_pdg_config_t cfg = {
192 .channel_mask = (uint8_t)k_pdg_demo_chan_mask,
193 .auto_tune = 0U,
194 .gptclk_hz = 0U,
195 };
196 const ra8_err_t ierr = ra8_pdg_init(&cfg);
197 if (ierr != k_ra8_ok) {
198 return ierr;
199 }
203 (uint8_t)k_pdg_demo_delay_code);
204}
205
231[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_pdg_demo_sample(uint8_t* out_ok)
232{
233 RA8_CHECK_NULL_PTR(out_ok, s_tag, "out_ok must not be nullptr");
234
235 uint8_t code = 0U;
236 const ra8_err_t derr =
238 if (derr != k_ra8_ok) {
239 return derr;
240 }
241 ra8_pdg_status_full_t st = {};
242 const ra8_err_t err = ra8_pdg_get_status_full(&st);
243 if (err != k_ra8_ok) {
244 return err;
245 }
246 /* GTDLYRnA is not read-exposed on RA8D2 silicon: a write stages the delay
247 * but the register reads back its 0x0000 reset value (confirmed by a debugger
248 * probe; FSP never reads it back either). ra8_emulator shadows it as plain R/W,
249 * which is why the read-back only appears to work there. So this is recorded
250 * for the emulator but NOT gated on. */
251 g_pdg_delay_readback = (uint32_t)code;
252 g_pdg_dll = (st.dll_enabled != 0U) ? 1U : 0U;
253
254 const uint8_t powered = (st.per_channel_powered[k_pdg_demo_channel] != 0U) ? 1U : 0U;
255 const uint8_t bypass_n = (st.per_channel_bypass_off[k_pdg_demo_channel] != 0U) ? 1U : 0U;
256 /* Validate the software-observable bring-up: DLL locked + channel 0 powered
257 * and un-bypassed. The delay's actual edge-shift effect needs a scope. */
258 *out_ok = (st.dll_enabled != 0U && powered != 0U && bypass_n != 0U) ? 1U : 0U;
259 return k_ra8_ok;
260}
261
262void main(void)
263{
265 /* Clear PRIMASK so SysTick can dispatch and ra8_delay_ms() uses the
266 * SysTick path (ra8_emulator does not advance DWT_CYCCNT). No NVIC sources
267 * are armed by this demo. */
269
272 }
273
274 while (1) {
275 uint8_t ok = 0U;
276 const ra8_err_t err = internal_pdg_demo_sample(&ok);
277 const uint8_t good = (err == k_ra8_ok && ok != 0U) ? 1U : 0U;
278 g_pdg_cfg_ok = (uint32_t)good;
279 if (good != 0U) {
281 (size_t)(sizeof(s_pdg_demo_ok_msg) - 1U));
283 } else {
285 (size_t)(sizeof(s_pdg_demo_bad_msg) - 1U));
287 }
290 }
292}
void main(void)
Secure fallback main entry point.
Definition main.c:37
static const uint8_t s_pdg_demo_ok_msg[]
Output line tags.
Definition main.c:71
volatile uint32_t g_pdg_heartbeat
Bumps once per main-loop pass – liveness for headless probes.
Definition main.c:104
volatile uint32_t g_pdg_delay_readback
Last delay code read back from the PDG temporary register.
Definition main.c:88
volatile uint32_t g_pdg_dll
1 when GTDLYCR.DLLEN reads back enabled.
Definition main.c:96
static ra8_err_t internal_pdg_demo_sample(uint8_t *out_ok)
Read the PDG status and fold the bring-up into the verdict.
Definition main.c:231
static void internal_pdg_demo_panic_halt(void)
Park the processor after a fatal initialization failure.
Definition main.c:119
static ra8_err_t internal_pdg_demo_configure(void)
Bring up the PDG DLL on channel 0 and programme a delay code.
Definition main.c:188
static void internal_pdg_demo_setup_or_halt(void)
Bring CGC, SysTick, SCI8, LEDs, and MSTP support up.
Definition main.c:139
pdg_demo_chan_t
PDG channel + delay programmed by this demo.
Definition main.c:64
@ k_pdg_demo_chan_mask
channel_mask bit 0.
Definition main.c:66
@ k_pdg_demo_delay_code
Mid-range DLY[6:0] code (0..7F).
Definition main.c:67
@ k_pdg_demo_channel
PDG / GPT32 channel 0.
Definition main.c:65
pdg_demo_config_t
Compile-time settings.
Definition main.c:58
@ k_pdg_demo_baud
SCI8 baud rate.
Definition main.c:59
@ k_pdg_demo_period_ms
Delay between reports.
Definition main.c:60
volatile uint32_t g_pdg_cfg_ok
1 when the DLL + channel + delay read back as configured.
Definition main.c:80
static const uint8_t s_pdg_demo_bad_msg[]
Definition main.c:72
static const char * s_tag
Logging / check tag.
Definition ra8_app.c:17
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led2
LED2, GREEN, P303 (jumper E26).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
Definition ra8_cgc.h:70
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_CHECK_NULL_PTR(ptr, tag, message)
Reject nullptr pointer, returning k_ra8_err_null_ptr.
Definition ra8_check.h:243
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
NVIC + ICU IELSR allocator.
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Definition ra8_isr.c:439
Ref-counted Module Stop Control wrapper for the RA8D2.
ra8_err_t ra8_mstp_init(void)
Re-establish the ra8_mstp ref-count table from current hardware state.
Definition ra8_mstp.c:291
PWM Delay Generation Circuit (PDG) driver public API.
ra8_err_t ra8_pdg_set_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t code)
Set the per-edge fine delay for one PDG channel/pin/edge.
Definition ra8_pdg.c:494
ra8_err_t ra8_pdg_get_delay(uint8_t channel, ra8_pdg_pin_t pin, ra8_pdg_edge_t edge, uint8_t *out_code)
Read back the last-programmed delay code.
Definition ra8_pdg.c:512
@ k_ra8_pdg_edge_rising
GTDLYRnA / GTDLYRnB.
Definition ra8_pdg.h:87
ra8_err_t ra8_pdg_get_status_full(ra8_pdg_status_full_t *out)
Read a fully-decoded snapshot of GTDLYCR + GTDLYCR2.
Definition ra8_pdg.c:672
@ k_ra8_pdg_pin_a
GTIOCnA – "A" output of GPT32n.
Definition ra8_pdg.h:100
ra8_err_t ra8_pdg_init(const ra8_pdg_config_t *cfg)
Initialise the PDG block per HUM Figure 23.2 (p 1160).
Definition ra8_pdg.c:438
@ k_ra8_pdg_frange_80_160_mhz
80..160 MHz, 1/128 step.
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
Definition ra8_time.c:59
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Definition ra8_time.c:129
Driver configuration descriptor for ra8_pdg_init.
Definition ra8_pdg.h:173
Decoded snapshot of GTDLYCR / GTDLYCR2 returned by ra8_pdg_get_status_full.
Definition ra8_pdg.h:191
uint8_t per_channel_powered[k_ra8_pdg_channel_count]
!DLYENn.
Definition ra8_pdg.h:196
uint8_t per_channel_bypass_off[k_ra8_pdg_channel_count]
DLYBSn.
Definition ra8_pdg.h:195
uint8_t dll_enabled
GTDLYCR.DLLEN.
Definition ra8_pdg.h:192