- Generated by
1.16.1
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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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I/O-expander, USB, camera, external-memory, MIPI-DSI, UART console, and Ethernet portion of the EK-RA8D2 v1 board-support layer. More...
#include <stddef.h>#include <stdint.h>#include "ra8_attributes.h"#include "ra8_board_ek_ra8d2_connectors.h"#include "ra8_err.h"#include "ra8_port_constants.h"Go to the source code of this file.
Data Structures | |
| struct | ra8_board_clock_rates_t |
| Clock rates published by the standard EK-RA8D2 bring-up. More... | |
Functions | |
| ra8_err_t | ra8_board_clocks_init (ra8_board_clock_rates_t *out_rates) |
| Initialize the standard EK-RA8D2 clock tree and return its rates. | |
| ra8_err_t | ra8_board_io_expander_apply_project_sw4_defaults (void) |
| Program the U15 I/O expander to apply the project's SW4 layout. | |
| ra8_err_t | ra8_board_io_expander_apply_sw4 (uint8_t output_byte) |
| Program an exact U15 SW4 override byte in one bring-up sequence. | |
| ra8_err_t | ra8_board_io_expander_apply_sw4_mask (uint8_t output_byte, uint8_t output_mask) |
| Override selected SW4 positions while releasing every other position. | |
| ra8_err_t | ra8_board_io_expander_set_octospi_active (void) |
| Program the U15 I/O expander to request the Octo-SPI SW4 layout. | |
| ra8_err_t | ra8_board_io_expander_set_usbhs_device_mode (void) |
| Drive the U15 PI4IOE5V6408 I/O expander to select USB-HS device mode. | |
| ra8_err_t | ra8_board_io_expander_set_usbhs_host_mode (void) |
| Drive the U15 I/O expander to select USB-HS HOST mode. | |
| ra8_err_t | ra8_board_usbhs_device_init (void) |
| Bring the chip USBHS module up in device mode (HS PHY). | |
| ra8_err_t | ra8_board_usbhs_host_init (void) |
| Bring the chip USBHS module up in host mode. | |
| ra8_err_t | ra8_board_camera_xclk_start (uint32_t frequency_hz) |
| Start the J35 camera sensor input clock (XCLK) on P501/GTIOC12A. | |
| ra8_err_t | ra8_board_camera_select_parallel (void) |
| Drive only SW4-6 ON through U15, selecting J35 parallel DVP. | |
| ra8_err_t | ra8_board_camera_route_parallel_pins (void) |
| Route J35 D[7:0], VSYNC, HSYNC and PCLK to the CEU peripheral. | |
| ra8_err_t | ra8_board_camera_reset (void) |
| Pulse the J35 camera reset input and leave the sensor released. | |
| ra8_err_t | ra8_board_camera_sccb_read_reg (void *ctx, uint8_t address, uint16_t reg, uint8_t *out_value) |
| Read one 16-bit-addressed SCCB register on the J35 camera bus. | |
| ra8_err_t | ra8_board_camera_sccb_write_reg (void *ctx, uint8_t address, uint16_t reg, uint8_t value) |
| Write one 16-bit-addressed SCCB register on the J35 camera bus. | |
| void | ra8_board_camera_delay_ms (void *ctx, uint32_t milliseconds) |
| Millisecond delay adapter for transport-independent camera drivers. | |
| ra8_err_t | ra8_board_xspi_pins_init (void) |
| Route the 12 OCTA bus pins to the xSPI peripheral and pulse RESET_L. | |
| ra8_err_t | ra8_board_mipi_dsi_init (void) |
| Bring the MIPI-DSI link up (PHY + DSI controller). | |
| ra8_err_t | ra8_board_uart_console_init (uint32_t baud) |
| Configure SCI8 + PD02/PD03 as the debug-console UART. | |
| ra8_err_t | ra8_board_uart_console_write (const uint8_t *data, size_t len) |
| Polled blocking write to the J-Link OB VCOM console. | |
| ra8_err_t | ra8_board_uart_console_read (uint8_t *out, size_t cap, size_t *out_len) |
| Polled non-blocking read from the J-Link OB VCOM console. | |
| ra8_err_t | ra8_board_uart_console_flush (void) |
| Block until every byte queued on the J-Link OB VCOM console has finished clocking out on the wire. | |
| ra8_err_t | ra8_board_ethernet_init (void) |
| Bring up the on-board RGMII Ethernet PHY and RMAC1/ETHA1. | |
I/O-expander, USB, camera, external-memory, MIPI-DSI, UART console, and Ethernet portion of the EK-RA8D2 v1 board-support layer.
Sub-header of ra8_board_ek_ra8d2.h (the thin umbrella). Carries the U15 PI4IOE5V6408 I/O-expander SW4 override functions (Section 6c), the USB-HS / USB-FS routing (Section 7), the parallel-camera connector J35 (Section 8), the Octo-SPI flash + SDRAM external memory (Section 9), the MIPI-DSI graphics expansion port J32 (Section 10), the J-Link OB VCOM serial bridge (Section 11), and the on-board RGMII Ethernet PHY (Section 12).
Every declaration here was moved VERBATIM out of ra8_board_ek_ra8d2.h; no contract, Doxygen block, or HUM/UM citation has changed. The enum that backs the SW4-layout output bytes (ra8_board_pi4ioe_project_t) lives in ra8_board_ek_ra8d2_connectors.h, pulled in below so the I/O-expander functions resolve their referenced constants. Consumers keep including ra8_board_ek_ra8d2.h; this file is pulled in by that umbrella and should not be included directly.
Authoritative source: docs/reference/ek-ra8d2-v1-users-manual.pdf (Rev 1.01, R20UT5523EG0101, October 2025).
Definition in file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_camera_bus_t : uint8_t |
RIIC controller channel wired to the J35 camera SCCB bus.
| Enumerator | |
|---|---|
| k_ra8_board_camera_i2c_channel | RIIC1 serves J35 SCCB. |
Definition at line 454 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_camera_pin_t : uint16_t |
Pins routed to the parallel-camera connector J35 (DVP mode).
UM Table 35 ("Camera Expansion Port Assignments in Parallel mode, SW4-6 ON"). Goes into the chip CEU peripheral. P405/P406 are shared with the audio CODEC – see ra8_board_audio_pin_t and jumper J41. P902/PB02/PB03/PB04 are also shared with the parallel graphics expansion port, so DVP camera and parallel TFT are mutually exclusive.
Definition at line 402 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_eth_index_t : uint8_t |
ETHA / RMAC port and PHY MDIO address for the on-board PHY.
Per UM 6.1 ("Ethernet interface") and the canonical FSP example project ethernet_ek_ra8d2_ep (ra8_cfg.txt: "Channel: 1" for both g_ether0 and g_rmac_phy0). The on-board PHY (MaxLinear PEF7071VV16- LLHU, UM Table 27 p 34) is the only device on the MDIO bus and powers up at MDIO address 0; the RA8D2 has two ETHA / RMAC instances, of which port 1 (not port 0) is the one wired to the RJ45 J33 on the EK-RA8D2. Earlier revisions of this header pointed at port 0 – that was wrong; the chip-side MDIO controller never saw a reply because the MDC / MDIO pads on RMAC0 are not routed to the board's PHY.
Definition at line 952 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_eth_pin_t : uint16_t |
Pin assignments for the on-board MaxLinear PEF7071 (GPY111) PHY.
Per UM Table 26 ("Ethernet Port Assignments") p 33. The PHY is wired to the RA8D2 ETHERC0 / RMAC0 in RGMII mode (UM 6.1: "RGMII Ethernet Physical Layer Transceiver"). The 25 MHz reference clock is sourced from a discrete oscillator (ECS-250-10-37B-CTN-TR, UM Table 27 p 34) connected directly to the PHY – the MCU does not drive REFCLK. Ethernet data rails are gated by trace-cut links E18..E24, E33, E34, E36..E38 (all closed by default).
Definition at line 902 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_extmem_base_t : uintptr_t |
Memory-mapped base addresses for off-chip XSPI / SDRAM.
Per UM Section 6.3 (Octo-SPI flash, IS25LX512M-JHLE 64 MB on the Octo-SPI peripheral) and Section 6.4 (IS42S32160F-6BLI 64 MB SDRAM on the SDRAMC bus). Bases are documented in the chip Hardware User's Manual memory map; the board UM only specifies the parts and their pin connections.
| Enumerator | |
|---|---|
| k_ra8_board_xspi_flash_base | 64 MB IS25LX512M (chip HUM memory map). |
| k_ra8_board_sdram_base | 64 MB IS42S32160F (per linker scripts + ra8_sdramc.c). |
Definition at line 595 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_extmem_size_t : uint32_t |
Sizes of the off-chip memories, in bytes.
| Enumerator | |
|---|---|
| k_ra8_board_xspi_flash_size | 64 MiB. UM Section 6.3 p 35. |
| k_ra8_board_sdram_size | 64 MiB. UM Section 6.4 p 36. |
Definition at line 602 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_i3c0_pin_t : uint16_t |
IIC_B / I3C channel-0 board pins (SCL0 / SDA0), UM Table 20 p 28.
The I3C ch0 I2C-compatibility bus is routed to P400 (SCL0) and P401 (SDA0) when SW4-5 selects I3C mode (UM Table 20 p 28 + Section 5.5.3 p 32). These two pads double as SDHI0 CMD/CLK under the default I2C-mode routing, so use these names only when the board is jumpered for the I3C bus.
| Enumerator | |
|---|---|
| k_ra8_board_i3c0_pin_scl | P400 SCL0. UM Table 20 p 28. |
| k_ra8_board_i3c0_pin_sda | P401 SDA0. UM Table 20 p 28. |
Definition at line 252 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_mipi_dsi_pin_t : uint16_t |
MIPI-DSI display-connector control pins (J32).
UM Table 34 ("MIPI Graphics Expansion Port Assignments"). The high-speed DSI clock + 2 data lanes (MIPI_DSI_CL_P/N, MIPI_DSI_DL0_P/N, MIPI_DSI_DL1_P/N) are dedicated MIPI-PHY balls and are not exposed as general-purpose port pins; only the low-speed control side (TE / reset / backlight / I2C touch / touch INT) is BSP-addressable.
Definition at line 696 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_touch_wiring_t : uint32_t |
Where the on-board GoodIX GT911 capacitive-touch controller sits.
The Parallel Graphics Expansion Board's ER-TFT070-6 carries one GT911, on one bus, at one address. These three values are that wiring, stated once: the I3C block's I2C-compatibility channel it hangs off, its 7-bit target address, and the fast-mode rate the panel's touch bus is specified for. Eight applications used to declare their own copy of each under their own prefix, and all eight also hardcoded a source clock instead of asking CGC – see ra8_board_touch_open, which is the supported way to consume these.
The SOURCE CLOCK is deliberately absent. It is not a board fact: PCLKA is whatever the application's CGC tree settled on, so the bit-rate divider must be solved against ra8_cgc_get_clock_hz at run time, never against a constant.
Definition at line 285 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_uart_console_pin_t : uint16_t |
Pin assignments for the J-Link OB VCOM bridge (UM Table 13 p 24).
PD02 / PD03 are always wired to the debug MCU's CDC bridge. PD04 / PD05 are the optional RTS / CTS lines (links E17 / E9, both closed by default). Chip-coordinate names: P1302 / P1303 / P1304 / P1305 (port 13, pins 2..5).
Definition at line 770 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_uart_sci_channel_t : uint8_t |
SCI channel that backs k_ra8_board_uart_console.
Exposed as an enum (not a macro) so test code and applications can reference the channel without re-encoding the magic number. The value comes from PD02/PD03's Multiplexed Pin Function Selector row in the chip HUM I/O Ports chapter (TXD8/RXD8 alternate).
| Enumerator | |
|---|---|
| k_ra8_board_uart_console_sci_channel | PD02/PD03 -> SCI8 (verified on real EK-RA8D2 v1 silicon). |
Definition at line 756 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_uart_t : uint8_t |
Identifiers for board-routed UART consoles.
The EK-RA8D2 v1 carries the J-Link OB debug MCU's USB-CDC virtual-COM bridge on chip pins PD02 (TXD) / PD03 (RXD) per UM Table 13 p 24. Hardware-flow-control lines PD04 (RTS) and PD05 (CTS) are present on the same connector but are gated by trace-cut links E17 / E9 and are not used by the basic console wiring.
On the RA8D2 PD02/PD03 are the SCI8 TXD8/RXD8 alternate functions (chip HUM "Multiplexed Pin Function Selector"); the BSP forwards to SCI channel 8 via ra8_sci_init / ra8_sci_write_polling / ra8_sci_getc_polling.
| Enumerator | |
|---|---|
| k_ra8_board_uart_console | J-Link OB VCOM bridge: PD02 TXD / PD03 RXD on SCI8. EK-RA8D2 UM Table 13 p 24. |
Definition at line 742 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_usbfs_pin_t : uint16_t |
USB-FS (J11) board-routed port pins, UM Table 22 p 30.
The full-speed peripheral on J11 (USB Type-C) exposes four board-routed pins: the D+/D- differential pair, the VBUS sense input, and the MCU-driven VBUS-enable GPIO. Route D+/D-/VBUS to the USBFS peripheral function (k_ra8_psel_usb_fs) and drive VBUSEN as a GPIO output (LOW = device role, HIGH = supply 5 V VBUS for host role).
These are the single source of truth for the EK-RA8D2 USB-FS pinout: applications reference these names instead of re-encoding the port/pin pair, so the board fact lives in exactly one place.
Definition at line 232 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_usbhs_pin_t : uint16_t |
USBHS host/device routing per UM Table 28 p 34.
USBHS (J7, USB Type-C). The HS PHY DM/DP differential pair (USBH_P/USBH_N) is internal to the chip and not a board-routed port pin. VBUS sense (USBHS_cVBUS_CON) and CC pins are PHY-side. Only the bus signals listed below are exposed to user firmware.
USB-FS (J11, USB Type-C, UM Table 22 p 30) is the host/dev port for the full-speed peripheral and follows the same arrangement.
| Enumerator | |
|---|---|
| k_ra8_board_usbhs_pin_vbus | P4_08 USBHS_VBUS sense. UM Table 28 p 34. |
| k_ra8_board_usbhs_pin_pwr | PD07 J7 host-power switch (HIGH = U18 drives 5 V VBUS). UM 6.2. |
Definition at line 207 of file ra8_board_ek_ra8d2_peripherals.h.
| enum ra8_board_xspi_pin_t : uint16_t |
Pins routed to the on-board IS25LX512M Octo-SPI flash.
UM Table 29 ("Octo-SPI Flash Assignments"). Selection is gated by SW4-3 (Octo-SPI vs Arduino/Pmod1). The chip-select strobe is OSPI_FLASH_S_L, mapped to P104.
Definition at line 616 of file ra8_board_ek_ra8d2_peripherals.h.
| void ra8_board_camera_delay_ms | ( | void * | ctx, |
| uint32_t | milliseconds ) |
Millisecond delay adapter for transport-independent camera drivers.
Ignores ctx and delegates the bounded delay to ra8_delay_ms.
| [in] | ctx | Unused transport context; may be nullptr. |
| [in] | milliseconds | Delay duration. |
milliseconds is acceptable to the platform delay service. Definition at line 179 of file ra8_board_ek_ra8d2_camera.c.
References ra8_delay_ms().
Referenced by cam_sensor_bind(), internal_c6_cam_sensor_bind(), and sensor_bind().
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nodiscard |
Pulse the J35 camera reset input and leave the sensor released.
Claims P709 as an output, holds reset low, then releases it high.
| k_ra8_ok | P709 was driven low, then high. |
| other | Forwarded GPIO initialization/write error. |
Definition at line 128 of file ra8_board_ek_ra8d2_camera.c.
References k_camera_reset_high_ms, k_camera_reset_low_ms, k_ra8_board_cam_rst, k_ra8_level_high, k_ra8_level_low, k_ra8_ok, ra8_delay_ms(), ra8_gpio_output_init(), and ra8_gpio_write().
Referenced by c6_cam_camera_init(), cam_run(), and internal_bring_up_sensor().
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nodiscard |
Route J35 D[7:0], VSYNC, HSYNC and PCLK to the CEU peripheral.
Claims and muxes the eleven parallel-camera pads in board order.
| k_ra8_ok | Every parallel-camera pin was routed. |
| other | First propagated PFS routing error. |
Definition at line 113 of file ra8_board_ek_ra8d2_camera.c.
References k_ra8_ok, k_ra8_psel_ceu, ra8_pfs_route_peripheral(), and s_camera_parallel_pins.
Referenced by c6_cam_camera_init(), cam_prepare_capture(), and internal_bring_up_capture_pipeline().
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nodiscard |
Read one 16-bit-addressed SCCB register on the J35 camera bus.
Signature intentionally matches the transport callback used by ra8_ov5640; the BSP remains independent of that optional sensor library.
| [in] | ctx | Unused transport context; may be nullptr. |
| [in] | address | 7-bit SCCB target address. |
| [in] | reg | 16-bit sensor register address. |
| [out] | out_value | Register value on success. |
| k_ra8_ok | One register byte was read. |
| k_ra8_err_null_ptr | out_value was nullptr. |
| other | Propagated RIIC transfer error. |
out_value contains the addressed register byte. Definition at line 146 of file ra8_board_ek_ra8d2_camera.c.
References k_camera_high_byte_shift, k_camera_reg_address_bytes, k_ra8_board_camera_i2c_channel, RA8_CHECK_NULL_PTR, and ra8_i2c_transfer().
Referenced by cam_sensor_bind(), internal_c6_cam_sensor_bind(), and sensor_sccb_read().
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nodiscard |
Write one 16-bit-addressed SCCB register on the J35 camera bus.
| [in] | ctx | Unused transport context; may be nullptr. |
| [in] | address | 7-bit SCCB target address. |
| [in] | reg | 16-bit sensor register address. |
| [in] | value | Register value to write. |
| k_ra8_ok | The complete address and value payload was written. |
| other | Propagated RIIC write error. |
Definition at line 163 of file ra8_board_ek_ra8d2_camera.c.
References k_camera_high_byte_shift, k_camera_write_bytes, k_ra8_board_camera_i2c_channel, and ra8_i2c_write().
Referenced by cam_sensor_bind(), internal_c6_cam_sensor_bind(), and sensor_sccb_write().
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nodiscard |
Drive only SW4-6 ON through U15, selecting J35 parallel DVP.
Applies a masked U15 override without changing unrelated switches.
| k_ra8_ok | U15 selected the parallel-camera path. |
| other | Propagated expander or RIIC error. |
Definition at line 106 of file ra8_board_ek_ra8d2_camera.c.
References k_camera_sw46_mask, k_camera_sw46_output, and ra8_board_io_expander_apply_sw4_mask().
Referenced by c6_cam_camera_init(), cam_bringup(), and internal_bring_up_sensor().
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nodiscard |
Start the J35 camera sensor input clock (XCLK) on P501/GTIOC12A.
Configures GPT12 saw-PWM from PCLKD and routes its A output to P501.
| [in] | frequency_hz | Requested non-zero camera input-clock frequency. |
| k_ra8_ok | GPT12 is running and P501 is routed. |
| k_ra8_err_invalid_arg | The requested divisor is not representable. |
| other | Propagated clock, GPT, or pin-routing error. |
Definition at line 59 of file ra8_board_ek_ra8d2_camera.c.
References k_camera_gpt_period_max, k_camera_xclk_gpt_channel, k_ra8_board_cam_xclk, k_ra8_clock_id_pclkd, k_ra8_err_invalid_arg, k_ra8_gpt_disable_none, k_ra8_gpt_mode_saw_pwm, k_ra8_gpt_pin_a, k_ra8_gpt_pol_active_high, k_ra8_gpt_ps_div_1, k_ra8_gpt_stop_low, k_ra8_ok, k_ra8_pfs_dscr_high_speed_high, k_ra8_psel_gpt0, ra8_cgc_get_clock_hz(), ra8_gpt_init(), ra8_gpt_pwm_pin_configure(), ra8_pfs_route_peripheral(), and ra8_pfs_set_drive_strength().
Referenced by c6_cam_camera_init(), cam_bringup(), and internal_bring_up_sensor().
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nodiscard |
Initialize the standard EK-RA8D2 clock tree and return its rates.
Keeps chip-specific CGC selection inside the board-composition layer while exposing the fixed rates needed by application-owned timebases and peripheral configurations.
| [out] | out_rates | Initialized CPUCLK0 and PCLKA rates. |
| k_ra8_ok | Clock initialization succeeded and out_rates is valid. |
| k_ra8_err_invalid_arg | out_rates is null. |
| other | Propagated clock-generator initialization error. |
out_rates is unchanged when nonnull. Initialize the standard EK-RA8D2 clock tree and return its rates.
Delegates the register-level transition to the CGC HAL, then returns the board-qualified CPUCLK0 and PCLKA constants without exposing a concrete clock driver to application code.
| [out] | out_rates | Initialized board clock rates. |
| k_ra8_ok | Clock initialization and rate publication succeeded. |
| k_ra8_err_invalid_arg | out_rates is null. |
| other | Propagated clock-generator initialization error. |
out_rates is unchanged when nonnull. Definition at line 58 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_cpuclk0_hz, k_ra8_err_invalid_arg, k_ra8_ok, k_ra8_pclka_hz, and ra8_cgc_init().
Referenced by internal_c6_cam_setup_or_halt(), internal_setup_or_halt(), and pdm_demo_clocks_or_halt().
| ra8_err_t ra8_board_ethernet_init | ( | void | ) |
Bring up the on-board RGMII Ethernet PHY and RMAC1/ETHA1.
Hardware-resets the PEF7071/GPY111 through RSTN (P708), leaving that signal as a GPIO output driven high. The other 15 Ethernet signals are routed to their RGMII alternate functions before the ESWM clocks, power, module-stop gates, and COMA buffer pool are brought up. ETHA1 then walks RESET to CONFIG, the external media mux selects RGMII, and RMAC1 starts with its internal xMII profile at MII, 100 Mbps, full duplex.
After RMAC1 programming, ETHA1 enters OPERATION and this function soft-resets the PHY, applies the RGMII receive skew, advertises the supported 10/100 modes, and restarts PHY auto-negotiation internally.
| k_ra8_ok | Bring-up completed and PHY auto-negotiation restarted. |
| k_ra8_err_gpio_conflict | RSTN or an alternate-function pin is owned. |
| k_ra8_err_invalid_state | An Ethernet module-stop reference is saturated. |
| k_ra8_err_hw_timeout | A clock, module-stop, ETHA, COMA, or MDIO wait timed out. |
Definition at line 626 of file ra8_board_ek_ra8d2_ethernet.c.
References internal_eth_etha_to_operation(), internal_eth_phy_chip_init(), internal_eth_phy_hw_reset(), internal_eth_rmac_program(), internal_eth_route_alt_pins(), k_ra8_board_eth_rmac_port, k_ra8_ok, priv_ra8_board_eth_eswm_bring_up(), priv_ra8_board_eth_etha_to_config(), and ra8_eth_rgmii_select().
Referenced by demo_setup_or_halt(), eop_run_once(), and internal_demo_setup_or_halt().
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nodiscard |
Program the U15 I/O expander to apply the project's SW4 layout.
Equivalent to ra8_board_io_expander_set_usbhs_device_mode but writes k_ra8_board_pi4ioe_output_project_default (0xF2) to the expander's output register instead of 0xFF. After the write the board is forced into "Pmod1 UART, Octo-SPI inactive, Arduino + mikroBUS active, I2C on mikroBUS, USBHS Device" regardless of the physical DIP positions.
| k_ra8_ok | All three U15 register writes succeeded. |
| k_ra8_err_gpio_conflict | P512/P511 already owned by another driver. |
| k_ra8_err_hw_init_failed | RIIC1 initialization failed. |
| k_ra8_err_nack | U15 didn't ACK the register write. |
Program the U15 I/O expander to apply the project's SW4 layout.
Writes k_ra8_board_pi4ioe_output_project_default (0xF2) to the expander's output register, which forces SW4-1 ON + SW4-2 OFF (Pmod1 UART) + SW4-3 ON (Octo-SPI inactive) + SW4-4 ON (Arduino/mikroBUS active) + SW4-5 OFF (I2C), regardless of the physical DIP positions. See the header for the full per-bit table.
| k_ra8_ok | All bring-up steps completed; SW4 layout latched. |
| k_ra8_err_gpio_conflict | P512/P511 already owned. |
| k_ra8_err_hw_init_failed | RIIC1 initialization failed. |
| k_ra8_err_nack | U15 didn't ACK one of the register writes. |
Definition at line 814 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask(), k_ra8_board_pi4ioe_iodir_all_outputs, and k_ra8_board_pi4ioe_output_project_default.
Referenced by combo_setup_or_halt(), internal_setup_or_halt(), and riic_target_setup_or_halt().
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Program an exact U15 SW4 override byte in one bring-up sequence.
Writes the requested output latch before enabling U15's outputs, avoiding an intermediate board-mux layout. Bit n = 1 requests SW4-(n+1) OFF and bit n = 0 requests it ON.
| [in] | output_byte | Exact byte for U15's output register. |
| k_ra8_ok | U15 is driving output_byte. |
| k_ra8_err_gpio_conflict | RIIC1 pins are already owned. |
| k_ra8_err_hw_init_failed | RIIC1 initialization failed. |
| k_ra8_err_nack | U15 did not acknowledge a register write. |
output_byte. Definition at line 820 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask(), and k_ra8_board_pi4ioe_iodir_all_outputs.
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Override selected SW4 positions while releasing every other position.
| [in] | output_byte | Output latch values using the SW4 active-low convention. |
| [in] | output_mask | Bit mask of U15 pins to drive; clear bits remain inputs. |
output_byte and IODIR is output_mask. Definition at line 826 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask().
Referenced by ra8_board_camera_select_parallel().
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Program the U15 I/O expander to request the Octo-SPI SW4 layout.
Writes k_ra8_board_pi4ioe_output_octospi_active (0xF8, the all-SW4-OFF layout with OSPI_OE_L asserted – see that enum's definition) to the U15 output register with the port set to outputs.
IMPORTANT – this does NOT, and CANNOT, connect the flash. A firmware sweep over the entire U15 output space (all 256 output bytes, plus released-inputs / Hi-Z / per-bit single-line overrides; 2026-06, issue #44, docs/HARDWARE_BRINGUP.md) re-read the 1S JEDEC ID after each config and saw zero change: the flash stays silent (bus at the board pull-ups) for every U15 state. The U15 expander is therefore a pure SW4 sense / override whose GPIOs are NOT in the OSPI DQ/CK/CS path; the flash is gated only by the SW4-3 analog mux, which is hardware-only and not reachable from firmware. (When U15 is released to inputs, reg 0x0F reads 0xF8, but the exact U15<->SW4 bit mapping is not published in the UM – it lives in the EK-RA8D2 Design Package schematic – and has not yet been verified on this EVM, so that value is NOT actionable.) This call is kept only as an inert courtesy write; it has no bearing on flash reachability. See examples/.../flash_journal/README.md and issue #44.
| k_ra8_ok | All U15 register writes succeeded. |
| k_ra8_err_busy | RIIC1 bus was held by another controller. |
| k_ra8_err_hw_timeout | U15 did not respond on RIIC1. |
| k_ra8_err_nack | U15 didn't ACK the register write. |
).
Definition at line 831 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask(), k_ra8_board_pi4ioe_iodir_all_outputs, and k_ra8_board_pi4ioe_output_octospi_active.
Referenced by flash_journal_setup_or_halt(), ospirw_ospi_provision(), and selftest_ospi_provision().
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Drive the U15 PI4IOE5V6408 I/O expander to select USB-HS device mode.
The EK-RA8D2 v1 carries a PI4IOE5V6408 8-bit I2C I/O expander at U15 (I2C address 0x43, EK-RA8D2 v1 UM Rev 1.01 Section 5.5.3 p 32 + Section 4 p 16). U15 sits in parallel with the eight DIP switches of SW4 – when configured as outputs, U15's port pins override SW4 and gate the same on-board mux that SW4 drives, including SW4-8 which selects USB function on J7 (USB-HS): OFF = Device, ON = Host.
U15 register convention (from the PI4IOE5V6408 datasheet register map):
Polarity: the PI4IOE5V6408 datasheet defines a HIGH output bit as the released (pulled-up) level, so SW4-8 OFF (the silk-screen "Device" position) corresponds to U15.P7 = 1. The exact bit<->SW4-channel mapping is not in the UM (it is in the Design Package schematic) and is pending on-hardware verification on this EVM. We write 0xFF (all bits HIGH = all SW4 channels in their default OFF position) which puts USB-HS into Device mode and leaves the other muxed peripherals at their EK-RA8D2 default routing.
Routes P512 -> SCL1 and P511 -> SDA1 and initializes RIIC channel 1 at 100 kHz.
| k_ra8_ok | All three register writes succeeded; U15 is driving SW4-8 = OFF (Device mode). |
| k_ra8_err_gpio_conflict | P512/P511 already owned. |
| k_ra8_err_hw_init_failed | RIIC1 initialization failed. |
| k_ra8_err_nack | U15 didn't ACK the register write. |
Definition at line 762 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask(), k_ra8_board_pi4ioe_iodir_all_outputs, and k_ra8_board_pi4ioe_output_all_high.
Referenced by ra8_board_usbhs_device_init().
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Drive the U15 I/O expander to select USB-HS HOST mode.
Same U15 mechanism as ra8_board_io_expander_set_usbhs_device_mode (see that function for the expander register convention), but writes k_ra8_board_pi4ioe_output_usbhs_host (0x72): the project-default SW4 layout with bit 7 (SW4-8, USBHS role) driven LOW = ON = Host. In the host position the board's J7 VBUS switch supplies bus power to an attached device; in the default OFF/device position J7 expects VBUS from an external host and an attached USB stick stays dark.
| k_ra8_ok | U15 is driving SW4-8 = ON (Host mode). |
| k_ra8_err_gpio_conflict | P512/P511 already owned. |
| k_ra8_err_hw_init_failed | RIIC1 initialization failed. |
| k_ra8_err_nack | U15 didn't ACK a register write. |
Drive the U15 I/O expander to select USB-HS HOST mode.
See the public header for the documented contract; applies the project SW4 layout with SW4-8 (USBHS role) driven ON so the board supplies VBUS on J7.
| k_ra8_ok | U15 is driving the host-role layout. |
Definition at line 782 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_io_expander_apply_mask(), k_ra8_board_pi4ioe_iodir_all_outputs, and k_ra8_board_pi4ioe_output_usbhs_host.
Referenced by cdc_route_usb_or_halt(), dfu_route_usb_or_halt(), fileops_route_usb_or_halt(), hid_route_usb_or_halt(), microsd_route_usb_or_halt(), mlun_route_usb_or_halt(), ospirw_route_usb_or_halt(), selftest_route_usb_or_halt(), and wlun_route_usb_or_halt().
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Bring the MIPI-DSI link up (PHY + DSI controller).
| k_ra8_ok | / k_ra8_err_not_supported (until MIPI-DSI HAL lands) |
Definition at line 173 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_ok, ra8_mipi_dsi_hs_clock_start(), ra8_mipi_dsi_init(), ra8_mipi_phy_init(), s_mipi_panel_cfg, and s_mipi_phy_cfg.
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Block until every byte queued on the J-Link OB VCOM console has finished clocking out on the wire.
Thin wrapper around ra8_sci_flush(k_ra8_board_uart_console_sci_channel) that polls CSR.TEND on the SCI8 channel that backs the J-Link OB VCOM bridge (HUM Ch 38.2.17 "CSR : Common Status Register", p 2225). The intended caller is a panic-handler that needs the failure log to reach the host before WFI gates the SCI clock and silently drops the remaining FIFO contents.
| k_ra8_ok | TEND observed (or fake stub). |
| k_ra8_err_not_initialized | ra8_board_uart_console_init not called. |
| k_ra8_err_hw_timeout | Spin budget elapsed without TEND. |
Definition at line 348 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_board_uart_console_sci_channel, k_ra8_err_not_initialized, ra8_sci_flush(), and s_uart_console_initialized.
Referenced by app_launch_hil_emit_pass(), app_shell_hil_emit_pass(), cache_hal_emit(), cache_mpu_emit(), demo_panic_halt(), dtc_coh_report(), dualcore_bg_hil_emit_pass(), dualcore_mailbox_hil_emit_pass(), imp_panic(), internal_emit_pass(), internal_npu_infer_emit(), internal_npu_smoke_emit(), internal_npu_vela_emit(), internal_rcs_panic_halt(), internal_report(), main(), and mpu_boot_emit().
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Configure SCI8 + PD02/PD03 as the debug-console UART.
Routes PD02 -> TXD8 and PD03 -> RXD8 (PSEL = SCI async) and brings SCI8 up via ra8_sci_init with 8N1 framing at the requested baud. The SCI module operating clock on RA8D2 is PCLKA (chip HUM Ch 38.2 "SCI registers"); the BRR divisor is computed from the current PCLKA frequency reported by ra8_cgc_get_clock_hz, so callers must call ra8_cgc_init() before ra8_board_uart_console_init. Applications that retune CGC afterwards must additionally call ra8_sci_set_baud((uint8_t)k_ra8_board_uart_console_sci_channel, baud, new_pclka_hz) to recompute the divisor.
| [in] | baud | Target line rate in bps (e.g. 115200). |
| k_ra8_ok | Console up, ready to TX/RX. |
| k_ra8_err_invalid_arg | baud == 0. |
| k_ra8_err_not_initialized | ra8_cgc_init has not yet published a usable PCLKA value (chip still on MOCO / pre-PLL). |
| k_ra8_err_gpio_conflict | PD02 or PD03 already owned. |
| k_ra8_err_hw_init_failed | Underlying ra8_sci_init failed. |
Definition at line 240 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_board_uart_console_min_pclka_hz, k_ra8_board_uart_console_pin_rxd, k_ra8_board_uart_console_pin_txd, k_ra8_board_uart_console_sci_channel, k_ra8_clock_id_pclka, k_ra8_err_invalid_arg, k_ra8_err_not_initialized, k_ra8_ok, k_ra8_psel_sci_async, k_ra8_sci_data_8, k_ra8_sci_parity_none, k_ra8_sci_stop_1, ra8_cgc_get_clock_hz(), ra8_pfs_route_peripheral(), ra8_sci_init(), and s_uart_console_initialized.
Referenced by adc_diag_setup_or_halt(), al_setup_or_halt(), app_bringup_clocks(), app_launch_hil_console_init(), app_setup(), app_shell_hil_console_init(), bm_setup_or_halt(), bs_setup_or_halt(), c6_fwver_setup_or_halt(), c6_hosted_setup_or_halt(), c6_join_setup_or_halt(), c6_probe_setup_or_halt(), c6_wifi_setup_or_halt(), cache_hal_setup(), cache_mpu_setup(), cam_bringup(), cdc_setup_or_halt(), ch_setup_or_halt(), cm_bringup_clocks(), combo_setup_or_halt(), crc_demo_setup_or_halt(), demo_setup_or_halt(), demo_setup_or_halt(), dfu_setup_or_halt(), drw_blend_setup_or_halt(), drw_demo_setup_or_halt(), dtc_arm_setup_or_halt(), dtc_coh_setup_or_halt(), dtc_demo_setup_or_halt(), dualcore_bg_hil_console_init(), dualcore_mailbox_hil_console_init(), ec_setup_or_halt(), ef_setup_or_halt(), ehb_setup_or_halt(), eoh_setup_or_halt(), eop_setup_or_halt(), ep_bringup_core(), ep_setup_or_halt(), erb_setup_or_halt(), es_setup_or_halt(), est_setup_or_halt(), etoc_setup_or_halt(), ez_bringup_clocks(), fc_setup_or_halt(), fileops_setup_or_halt(), fs_fmt_setup_or_halt(), gh_setup_or_halt(), gptp_setup_or_halt(), hid_setup_or_halt(), i3c_demo_setup_or_halt(), iic_setup_or_halt(), imp_setup_or_halt(), imu_demo_setup_or_halt(), internal_agt_periodic_setup_or_halt(), internal_audio_loopback_init_console(), internal_bkup_demo_setup_or_halt(), internal_c6_cam_setup_or_halt(), internal_console_init(), internal_demo_clocks_or_halt(), internal_demo_setup_or_halt(), internal_dotf_demo_setup_or_halt(), internal_eth_loopback_setup_or_halt(), internal_icu_extint_demo_setup_or_halt(), internal_kat_setup_or_halt(), internal_kint_demo_setup_or_halt(), internal_lpm_deep_setup_or_halt(), internal_lpm_demo_setup_or_halt(), internal_lpm_dpsby1_setup_or_halt(), internal_lpm_dpsby2_setup_or_halt(), internal_lpm_dpsby3_setup_or_halt(), internal_lpm_swstd_setup_or_halt(), internal_lpm_wake_setup_or_halt(), internal_lus_setup_or_halt(), internal_lvd_demo_setup_or_halt(), internal_mecc_setup_or_halt(), internal_motor_3phase_init_console(), internal_mpu_simple_setup_or_halt(), internal_npu_infer_setup_or_halt(), internal_npu_smoke_setup_or_halt(), internal_npu_vela_setup_or_halt(), internal_pc_setup_or_halt(), internal_pdg_demo_setup_or_halt(), internal_poeg_demo_setup_or_halt(), internal_rc_setup_or_halt(), internal_rcs_setup_or_halt(), internal_rng_demo_setup_or_halt(), internal_rtc_demo_setup_or_halt(), internal_sd_demo_setup_or_halt(), internal_setup_or_halt(), internal_ssie_loop_setup_or_halt(), internal_tc_setup_or_halt(), internal_td_setup_or_halt(), internal_uart_hello_setup_or_halt(), internal_usb_audio_setup_or_halt(), internal_wdt_demo_setup_or_halt(), ipc_demo_setup_or_halt(), iu_setup_or_halt(), iv_setup_or_halt(), kat_setup_or_halt(), kb_setup_or_halt(), l3_setup_or_halt(), lin_hil_setup_or_halt(), lk_setup_or_halt(), lpi_setup_or_halt(), main(), mem_setup_or_halt(), mg_bringup_clocks(), microsd_setup_or_halt(), mlun_setup_or_halt(), modem_setup_or_halt(), mpu_boot_setup(), ospirw_setup_or_halt(), pdm_demo_io_or_halt(), pp_demo_clocks_or_halt(), ra8_nsc_periph_init(), riic_target_setup_or_halt(), rot_setup_or_halt(), sb_setup_or_halt(), sbns_console_bringup(), scb_demo_setup_or_halt(), sd_demo_setup_or_halt(), sd_setup_or_halt(), sdhi_card_setup_or_halt(), sdhi_demo_setup_or_halt(), sdmsc_setup_or_halt(), sdram_demo_setup_or_halt(), selftest_setup_or_halt(), sh_setup_or_halt(), tb_setup_or_halt(), timer_demo_setup_or_halt(), tsn_setup_or_halt(), wa_setup_or_halt(), wc_setup_or_halt(), wd_setup_or_halt(), wdt_rr_setup_or_halt(), wdt_window_demo_setup_or_halt(), webp_demo_setup_or_halt(), wifi_hal_setup_or_halt(), wk_setup_or_halt(), and wlun_setup_or_halt().
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Polled non-blocking read from the J-Link OB VCOM console.
Drains up to cap bytes from SCI8 RDR while RDRF stays set. Stops (without error) the first time RDRF clears so the call never blocks waiting for a host that is silent.
| [out] | out | Destination buffer (non-NULL when cap > 0). |
| [in] | cap | Capacity of out in bytes. |
| [out] | out_len | Number of bytes actually read; non-NULL. |
| k_ra8_ok | Read complete; *out_len in [0, cap]. |
| k_ra8_err_invalid_arg | out / out_len NULL with non-zero cap. |
| k_ra8_err_not_initialized | Console not initialized. |
Definition at line 308 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_board_uart_console_sci_channel, k_ra8_err_invalid_arg, k_ra8_err_not_initialized, k_ra8_ok, ra8_sci_getc_polling(), and s_uart_console_initialized.
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Polled blocking write to the J-Link OB VCOM console.
| [in] | data | Bytes to transmit; must be non-NULL when len > 0. |
| [in] | len | Number of bytes in data. |
| k_ra8_ok | All bytes pushed to TDR. |
| k_ra8_err_invalid_arg | data NULL with non-zero len. |
| k_ra8_err_not_initialized | ra8_board_uart_console_init not called. |
Definition at line 294 of file ra8_board_ek_ra8d2_comms.c.
References k_ra8_board_uart_console_sci_channel, k_ra8_err_invalid_arg, k_ra8_err_not_initialized, k_ra8_ok, ra8_sci_write_polling(), and s_uart_console_initialized.
Referenced by adc_diag_write(), al_print(), app_launch_hil_emit_pass(), app_print(), app_shell_hil_emit_pass(), bm_print(), bs_print(), c6_cam_put_u32(), c6_cam_puts(), c6_fwver_put_hex(), c6_fwver_put_text(), c6_fwver_put_u32(), c6_fwver_puts(), c6_hosted_put_hex(), c6_hosted_put_u32(), c6_hosted_puts(), c6_join_put_hex(), c6_join_put_u32(), c6_join_puts(), c6_probe_put_hex(), c6_probe_put_u32(), c6_probe_puts(), c6_wifi_put_hex(), c6_wifi_put_text(), c6_wifi_put_u32(), c6_wifi_puts(), cache_hal_emit(), cache_mpu_emit(), cam_put_hex(), cam_put_u32(), cam_puts(), cdc_sci_write(), ch_print(), cm_print(), crc_demo_one_iter(), demo_drain_print_job(), demo_emit(), demo_print(), demo_puts(), demo_read_test_file(), demo_report(), dfu_sci_write(), dfu_sci_write(), drw_blend_print_hex(), drw_blend_print_pass(), dtc_coh_report(), dualcore_bg_hil_emit_pass(), dualcore_mailbox_hil_emit_pass(), ec_print(), ef_print(), ehb_write(), eoh_print(), eop_log_sink(), eop_print(), ep_emit(), ep_print(), erb_print(), es_print(), est_print(), etoc_print(), ez_print(), fc_log_sink(), fc_print(), fileops_sci_write(), fs_fmt_print(), gh_print(), gptp_write(), hid_sci_write(), hid_sci_write(), iic_print(), imp_print(), imu_demo_tx(), internal_audio_loopback_print_count(), internal_bkup_demo_report_survival(), internal_demo_log(), internal_demo_print(), internal_demo_write_bytes(), internal_emit_pass(), internal_emit_tick(), internal_log_sink(), internal_lpm_demo_one_wake(), internal_motor_3phase_print_duty(), internal_mpu_simple_emit_banner(), internal_npu_infer_write(), internal_npu_smoke_write(), internal_npu_vela_write(), internal_pc_print(), internal_print(), internal_puts(), internal_rc_print(), internal_rcs_print(), internal_report(), internal_rng_demo_emit_one_line(), internal_sd_demo_print(), internal_sdcard_log(), internal_tc_print(), internal_td_print(), internal_usb_audio_log(), ipc_demo_log(), iu_print(), iv_print(), kat_setup_or_halt(), kb_print(), l3_write(), lk_print(), lpi_do_work(), ls_print(), main(), mem_print(), mg_print(), microsd_sci_write(), mlun_sci_write(), modem_tx(), mpu_boot_emit(), ospirw_sci_write(), pdm_demo_tx(), riic_target_on_event(), rot_write(), sb_write(), sbns_console_print_hex32(), sbns_console_say(), scb_demo_write(), sd_demo_print(), sd_print(), sdhi_card_print(), sdhi_demo_print(), sdmsc_sci_write(), selftest_sci_write(), selftest_sci_write(), selftest_sci_write(), selftest_sci_write(), selftest_sci_write(), sh_print(), tb_print(), timer_demo_one_capture(), tsn_write(), wa_print(), wc_print(), wd_print(), wdt_rr_arm_and_wait_for_reset(), wdt_window_demo_banner(), wifi_hal_put_hex(), wifi_hal_put_u32(), wifi_hal_puts(), wk_print(), and wlun_sci_write().
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Bring the chip USBHS module up in device mode (HS PHY).
| k_ra8_ok | / k_ra8_err_not_supported (until USBHS HAL lands) |
Definition at line 912 of file ra8_board_ek_ra8d2_audio_usb.c.
References g_usbhs_probe, internal_usbhs_clock_and_mstp(), internal_usbhs_role_select_device(), k_ra8_ok, k_ra8_usb_speed_hs, k_usbhs_probe_post_usb_dev_init, k_usbhs_probe_pre_usb_dev_init, ra8_board_io_expander_set_usbhs_device_mode(), and ra8_usb_device_init().
Referenced by internal_usb_audio_usb_or_halt().
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Bring the chip USBHS module up in host mode.
| k_ra8_ok | / k_ra8_err_not_supported (until USBHS HAL lands) |
Definition at line 948 of file ra8_board_ek_ra8d2_audio_usb.c.
References internal_usbhs_clock_and_mstp(), k_ra8_ok, k_ra8_usb_speed_hs, and ra8_usb_host_init().
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Route the 12 OCTA bus pins to the xSPI peripheral and pulse RESET_L.
Configures CS / CK / DQS / DQ0..DQ7 under PSEL=k_ra8_psel_qspi (0x1C) per EK-RA8D2 UM Table 29 (p 35), then drives the active-low RESET strap as a GPIO output: low for >= tRLRH, high for >= tRHSL before the first xSPI command. Must run BEFORE any ra8_xspi_* call.
| k_ra8_ok | All pins routed and reset strap pulsed. |
| k_ra8_err_invalid_arg | PFS programming rejected an entry. |
Definition at line 696 of file ra8_board_ek_ra8d2.c.
References k_ra8_board_xspi_reset, k_ra8_board_xspi_reset_high_ms, k_ra8_board_xspi_reset_low_ms, k_ra8_level_high, k_ra8_level_low, k_ra8_ok, k_ra8_psel_qspi, ra8_delay_ms(), ra8_gpio_output_init(), ra8_gpio_write(), ra8_pfs_route_peripheral(), and s_xspi_octa_pins.
Referenced by demo_run(), flash_journal_setup_or_halt(), internal_bus_init_once(), ospirw_ospi_provision(), and selftest_ospi_provision().
1.16.1