main.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_eth_gptp.h"
#include "ra8_etha.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

typedef enum : uint32_t {
  k_tsn_baud          = 115200U, 
  k_tsn_period_ms     = 1000U,   
  k_tsn_win_units     = 125000U, 
  k_tsn_cycle_units   = 250000U, 
  k_tsn_cbs_increment = 1500U,   
  k_tsn_cbs_upper_lim = 65536U,  
} tsn_const_t;

typedef enum : uint8_t {
  k_tsn_radix        = 10U, 
  k_tsn_dec_u32_max  = 10U, 
  k_tsn_dec_u64_max  = 20U, 
  k_tsn_gate_entries = 2U,  
} tsn_fmt_t;

typedef enum : uint32_t {
  k_tsn_gptp_window_ms = 200U,       
  k_tsn_ns_per_ms      = 1000000U,   
  k_tsn_ns_per_sec     = 1000000000U 
} tsn_gptp_const_t;

typedef enum : uint64_t {
  k_tsn_sec_flatten_max = 18446744073ULL, 
} tsn_flatten_limit_t;

typedef enum : uint8_t {
  k_tsn_tolerance_pct = 10U,  
  k_tsn_pct_full      = 100U, 
} tsn_band_t;

typedef enum : uint8_t {
  k_tsn_gate_ptp_only = 0x80U, 
} tsn_gate_t;
 
/* Console line fragments (kept short so each write is one shift-register
 * fill; the periodic log is the only output path). */
static const uint8_t k_tsn_tas_prefix[]   = "tsn: tas_entries=";
static const uint8_t k_tsn_cbs_prefix[]   = "tsn: cbs_en=";
static const uint8_t k_tsn_cbs_gate_sep[] = " gate=";
static const uint8_t k_tsn_cyc_prefix[]   = "tsn: tas_cycle=";
static const uint8_t k_tsn_base_prefix[]  = "tsn: gptp_adv_ns=";
static const uint8_t k_tsn_base_sep[]     = " sys_ms=";
static const uint8_t k_tsn_crlf[]         = "\r\n";
static const uint8_t k_tsn_verdict_pass[] = "tsn: schedule PASS\r\n";
static const uint8_t k_tsn_verdict_fail[] = "tsn: schedule FAIL\r\n";

static void tsn_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

static void tsn_write(const uint8_t* data, uint32_t len)
{
  (void)ra8_board_uart_console_write(data, (size_t)len);
}

static uint32_t tsn_u32_to_dec(uint8_t* buf, uint32_t val)
{
  if (val == 0U) {
    buf[0] = (uint8_t)'0';
    return 1U;
  }
  uint8_t  tmp[k_tsn_dec_u32_max];
  uint32_t n = 0U;
  uint32_t v = val;
  while (v != 0U) {
    tmp[n] = (uint8_t)('0' + (uint8_t)(v % (uint32_t)k_tsn_radix));
    v      = v / (uint32_t)k_tsn_radix;
    n++;
  }
  for (uint32_t i = 0U; i < n; i++) {
    buf[i] = tmp[n - 1U - i];
  }
  return n;
}

static void tsn_write_u32(uint32_t val)
{
  uint8_t        buf[k_tsn_dec_u32_max];
  const uint32_t n = tsn_u32_to_dec(buf, val);
  tsn_write(buf, n);
}

static void tsn_write_u64(uint64_t val)
{
  uint8_t  buf[k_tsn_dec_u64_max];
  uint8_t  tmp[k_tsn_dec_u64_max];
  uint32_t n = 0U;
  uint64_t v = val;
  if (v == 0U) {
    buf[0] = (uint8_t)'0';
    tsn_write(buf, 1U);
    return;
  }
  while (v != 0U) {
    tmp[n] = (uint8_t)('0' + (uint8_t)(v % (uint64_t)k_tsn_radix));
    v      = v / (uint64_t)k_tsn_radix;
    n++;
  }
  for (uint32_t i = 0U; i < n; i++) {
    buf[i] = tmp[n - 1U - i];
  }
  tsn_write(buf, n);
}

static uint64_t tsn_flatten_ns(uint64_t sec, uint32_t nsec)
{
  if (sec > (uint64_t)k_tsn_sec_flatten_max) {
    return UINT64_MAX;
  }
  return (sec * (uint64_t)k_tsn_ns_per_sec) + (uint64_t)nsec;
}

static bool tsn_check_time_base(void)
{
  uint64_t sec0  = 0U;
  uint32_t nsec0 = 0U;
  uint64_t sec1  = 0U;
  uint32_t nsec1 = 0U;
  bool     ok    = true;
 
  const uint32_t ms0 = ra8_time_ms();
  if (ra8_eth_gptp_get_time(k_ra8_gptp_timer_0, &sec0, &nsec0) != k_ra8_ok) {
    ok = false;
  }
  ra8_delay_ms((uint32_t)k_tsn_gptp_window_ms);
  if (ra8_eth_gptp_get_time(k_ra8_gptp_timer_0, &sec1, &nsec1) != k_ra8_ok) {
    ok = false;
  }
  const uint32_t elapsed_ms  = ra8_time_ms() - ms0;
  const uint64_t ns0         = tsn_flatten_ns(sec0, nsec0);
  const uint64_t ns1         = tsn_flatten_ns(sec1, nsec1);
  const uint64_t advance_ns  = (ns1 > ns0) ? (ns1 - ns0) : 0ULL;
  const uint64_t expected_ns = (uint64_t)elapsed_ms * (uint64_t)k_tsn_ns_per_ms;
  const uint64_t band_ns = (expected_ns * (uint64_t)k_tsn_tolerance_pct) / (uint64_t)k_tsn_pct_full;
 
  tsn_write(k_tsn_base_prefix, (uint32_t)(sizeof(k_tsn_base_prefix) - 1U));
  tsn_write_u64(advance_ns);
  tsn_write(k_tsn_base_sep, (uint32_t)(sizeof(k_tsn_base_sep) - 1U));
  tsn_write_u32(elapsed_ms);
  tsn_write(k_tsn_crlf, (uint32_t)(sizeof(k_tsn_crlf) - 1U));
 
  if (elapsed_ms == 0U) {
    return false;
  }
  if (advance_ns > (expected_ns + band_ns)) {
    ok = false;
  }
  if (advance_ns < (expected_ns - band_ns)) {
    ok = false;
  }
  return ok;
}

static bool tsn_tas_entry_matches(uint8_t index, const ra8_etha_tas_entry_t* want)
{
  ra8_etha_tas_entry_t got = {};
  if (ra8_etha_read_tas_entry(k_ra8_etha_port_0, index, &got) != k_ra8_ok) {
    return false;
  }
  if (got.gate_time_ns != want->gate_time_ns) {
    return false;
  }
  return got.gate_open == want->gate_open;
}

static bool tsn_program_tas(void)
{
  bool                              ok                          = true;
  static const ra8_etha_tas_entry_t entries[k_tsn_gate_entries] = {
    {.gate_time_ns = (uint32_t)k_tsn_win_units, .gate_open = true},
    {.gate_time_ns = (uint32_t)k_tsn_win_units, .gate_open = false},
  };
  ra8_etha_tas_queue_t queues[k_ra8_etha_tc_count] = {};
  queues[k_ra8_etha_tc_7].entries                  = entries;
  queues[k_ra8_etha_tc_7].count                    = (uint16_t)k_tsn_gate_entries;
 
  if (ra8_etha_tas_ram_reset(k_ra8_etha_port_0) != k_ra8_ok) {
    ok = false;
  }
  const ra8_err_t sched_err = ra8_etha_set_tas_schedule(k_ra8_etha_port_0,
                                                        queues,
                                                        (uint8_t)k_tsn_gate_ptp_only,
                                                        (uint32_t)k_tsn_cycle_units,
                                                        0U);
  if (sched_err != k_ra8_ok) {
    ok = false;
  }
  /* Read every entry back: this is what makes the verdict mean something. */
  for (uint8_t index = 0U; index < (uint8_t)k_tsn_gate_entries; ++index) {
    if (!tsn_tas_entry_matches(index, &entries[index])) {
      ok = false;
    }
  }
  if (ra8_etha_enable_tas(k_ra8_etha_port_0, 1U) != k_ra8_ok) {
    ok = false;
  }
  tsn_write(k_tsn_tas_prefix, (uint32_t)(sizeof(k_tsn_tas_prefix) - 1U));
  tsn_write_u32((uint32_t)k_tsn_gate_entries);
  tsn_write(k_tsn_crlf, (uint32_t)(sizeof(k_tsn_crlf) - 1U));
  return ok;
}

static bool tsn_program_cbs(void)
{
  bool                       ok    = true;
  const ra8_etha_cbs_param_t param = {
    .increment = (uint32_t)k_tsn_cbs_increment,
    .upper_lim = (uint32_t)k_tsn_cbs_upper_lim,
  };
  if (ra8_etha_configure_cbs(k_ra8_etha_port_0, k_ra8_etha_tc_2, 1U, &param) != k_ra8_ok) {
    ok = false;
  }
  uint8_t              enabled   = 0U;
  uint8_t              gate_open = 0U;
  ra8_etha_cbs_param_t oper      = {};
  const ra8_err_t      st_err =
    ra8_etha_get_cbs_state(k_ra8_etha_port_0, k_ra8_etha_tc_2, &enabled, &gate_open, &oper);
  if (st_err != k_ra8_ok) {
    ok = false;
  }
  tsn_write(k_tsn_cbs_prefix, (uint32_t)(sizeof(k_tsn_cbs_prefix) - 1U));
  tsn_write_u32((uint32_t)enabled);
  tsn_write(k_tsn_cbs_gate_sep, (uint32_t)(sizeof(k_tsn_cbs_gate_sep) - 1U));
  tsn_write_u32((uint32_t)gate_open);
  tsn_write(k_tsn_crlf, (uint32_t)(sizeof(k_tsn_crlf) - 1U));
  return ok;
}

static bool tsn_log_status(void)
{
  bool              ok  = true;
  ra8_etha_status_t sts = {};
  const ra8_err_t   err = ra8_etha_get_status(k_ra8_etha_port_0, &sts);
  if (err != k_ra8_ok) {
    ok = false;
  }
  tsn_write(k_tsn_cyc_prefix, (uint32_t)(sizeof(k_tsn_cyc_prefix) - 1U));
  tsn_write_u32(sts.tas_cycle);
  tsn_write(k_tsn_crlf, (uint32_t)(sizeof(k_tsn_crlf) - 1U));
  return ok;
}

static bool tsn_run_cycle(void)
{
  bool ok = true;
  if (!tsn_check_time_base()) {
    ok = false;
  }
  if (!tsn_program_tas()) {
    ok = false;
  }
  if (!tsn_program_cbs()) {
    ok = false;
  }
  if (!tsn_log_status()) {
    ok = false;
  }
  return ok;
}

static void tsn_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
  if (ra8_cgc_init() != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_mstp_init() != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_board_uart_console_init((uint32_t)k_tsn_baud) != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    tsn_panic_halt();
  }
  if (ra8_cgc_eswclk_init() != k_ra8_ok) {
    tsn_panic_halt();
  }
}

[[nodiscard]] static ra8_err_t tsn_arm_time_base(void)
{
  uint32_t        eswclk_hz = 0U;
  const ra8_err_t hz_err    = ra8_cgc_eswclk_hz(&eswclk_hz);
  if (hz_err != k_ra8_ok) {
    return hz_err;
  }
  const ra8_eth_gptp_cfg_t cfg      = {.clk_hz = eswclk_hz};
  const ra8_err_t          init_err = ra8_eth_gptp_init(&cfg);
  if (init_err != k_ra8_ok) {
    return init_err;
  }
  return ra8_eth_gptp_timer_enable(k_ra8_gptp_timer_0);
}

[[nodiscard]] static ra8_err_t tsn_arm(void)
{
  const ra8_err_t gptp_err = tsn_arm_time_base();
  if (gptp_err != k_ra8_ok) {
    return gptp_err;
  }
  const ra8_etha_config_t cfg = {
    .initial_mode = k_ra8_etha_opc_config,
    .eaeie0_mask  = 0U,
    .eaeie1_mask  = 0U,
    .eaeie2_mask  = 0U,
  };
  return ra8_etha_init(k_ra8_etha_port_0, &cfg);
}
 
void main(void)
{
  tsn_setup_or_halt();
  ra8_isr_globals_enable();
 
  if (tsn_arm() != k_ra8_ok) {
    tsn_panic_halt();
  }
 
  while (1) {
    const bool healthy = tsn_run_cycle();
    if (healthy) {
      tsn_write(k_tsn_verdict_pass, (uint32_t)(sizeof(k_tsn_verdict_pass) - 1U));
    } else {
      tsn_write(k_tsn_verdict_fail, (uint32_t)(sizeof(k_tsn_verdict_fail) - 1U));
    }
    if (ra8_board_led_toggle(k_ra8_board_led1) != k_ra8_ok) {
      break;
    }
    ra8_delay_ms((uint32_t)k_tsn_period_ms);
  }
  tsn_panic_halt();
}