ra8_ether_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"
 
typedef enum : uintptr_t {
  k_ra8_etha0_base_addr = 0x403CA000UL, 
  k_ra8_etha1_base_addr = 0x403CC000UL, 
  k_ra8_rmac0_base_addr = 0x403CB000UL, 
  k_ra8_rmac1_base_addr = 0x403CD000UL, 
  k_ra8_mfwd_base_addr  = 0x403C0000UL, 
  k_ra8_coma_base_addr  = 0x403C9000UL, 
  k_ra8_gptp_base_addr  = 0x403E0000UL, 
  k_ra8_eswm_base_addr  = 0x403C8000UL, 
  k_ra8_gwca0_base_addr = 0x403CE000UL, 
} ra8_ether_addr_t;

typedef enum : uint16_t {
  k_ra8_coma_off_ric     = 0x000U, 
  k_ra8_coma_off_rrc     = 0x004U, 
  k_ra8_coma_off_rcec    = 0x008U, 
  k_ra8_coma_off_cabpirm = 0x140U, 
} ra8_coma_offset_t;

typedef enum : uint32_t {
  k_ra8_coma_rrc_rr        = (1UL << 0U),  
  k_ra8_coma_rcec_rce      = (1UL << 16U), 
  k_ra8_coma_rcec_ace_mask = 0x7FUL,       
  k_ra8_coma_cabpirm_bpiog = (1UL << 0U),  
  k_ra8_coma_cabpirm_bpr   = (1UL << 1U),  
} ra8_coma_bit_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_coma_rrc(void)
{
  return (volatile uint32_t*)(k_ra8_coma_base_addr + (uintptr_t)k_ra8_coma_off_rrc);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_coma_rcec(void)
{
  return (volatile uint32_t*)(k_ra8_coma_base_addr + (uintptr_t)k_ra8_coma_off_rcec);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_coma_cabpirm(void)
{
  return (volatile uint32_t*)(k_ra8_coma_base_addr + (uintptr_t)k_ra8_coma_off_cabpirm);
}

typedef struct {
  volatile uint32_t ESWM_CTRL; 
  volatile uint32_t ESWM_STS;  
  volatile uint32_t ESWM_IE;   
  volatile uint32_t ESWM_ICLR; 
} r_eswm_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_eswm_regs_t* ra8_eswm(void)
{
  return (volatile r_eswm_regs_t*)k_ra8_eswm_base_addr;
}

typedef enum : uint32_t {
  k_ra8_eswm_off_miirr  = 0x19400UL, 
  k_ra8_eswm_off_miicr0 = 0x19404UL, 
  k_ra8_eswm_off_miicr1 = 0x19408UL, 
} ra8_eswm_mii_offset_t;

typedef enum : uint32_t {
  k_ra8_eswm_miirr_rgrst0 = (1UL << 0U), 
  k_ra8_eswm_miirr_rgrst1 = (1UL << 1U), 
  k_ra8_eswm_miirr_rmrst0 = (1UL << 8U), 
  k_ra8_eswm_miirr_rmrst1 = (1UL << 9U), 
} ra8_eswm_miirr_bit_t;

typedef enum : uint32_t {
  k_ra8_eswm_miicr_miisel_mii   = 0UL,          
  k_ra8_eswm_miicr_miisel_rgmii = 1UL,          
  k_ra8_eswm_miicr_miisel_rmii  = 2UL,          
  k_ra8_eswm_miicr_miisel_mask  = 0x3UL,        
  k_ra8_eswm_miicr_divstp       = (1UL << 8U),  
  k_ra8_eswm_miicr_txcide       = (1UL << 12U), 
} ra8_eswm_miicr_field_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_eswm_miirr(void)
{
  return (volatile uint32_t*)(k_ra8_eswm_base_addr + (uintptr_t)k_ra8_eswm_off_miirr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_eswm_miicr0(void)
{
  return (volatile uint32_t*)(k_ra8_eswm_base_addr + (uintptr_t)k_ra8_eswm_off_miicr0);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_eswm_miicr1(void)
{
  return (volatile uint32_t*)(k_ra8_eswm_base_addr + (uintptr_t)k_ra8_eswm_off_miicr1);
}

typedef struct {
  volatile uint32_t MFWD_CTRL; 
  volatile uint32_t MFWD_STS;  
  volatile uint32_t MFWD_IE;   
  volatile uint32_t MFWD_ICLR; 
} r_mfwd_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_mfwd_regs_t* ra8_mfwd(void)
{
  return (volatile r_mfwd_regs_t*)k_ra8_mfwd_base_addr;
}

typedef struct {
  volatile uint32_t COMA_CTRL; 
  volatile uint32_t COMA_STS;  
  volatile uint32_t COMA_IE;   
  volatile uint32_t COMA_ICLR; 
} r_coma_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_coma_regs_t* ra8_coma(void)
{
  /* COMA shares the MFWD window in the documented layout; if a
   * future revision moves it out, the linker constant above
   * needs a separate k_ra8_coma_base_addr entry. */
  return (volatile r_coma_regs_t*)k_ra8_mfwd_base_addr;
}

typedef struct {
  volatile uint32_t GWCA_CTRL; 
  volatile uint32_t GWCA_STS;  
  volatile uint32_t GWCA_IE;   
  volatile uint32_t GWCA_ICLR; 
} r_gwca_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_gwca_regs_t* ra8_gwca(void)
{
  return (volatile r_gwca_regs_t*)k_ra8_gwca0_base_addr;
}

typedef enum : uint32_t {
  k_ra8_gwmc_opc_reset     = 0x0U, 
  k_ra8_gwmc_opc_disable   = 0x1U, 
  k_ra8_gwmc_opc_config    = 0x2U, 
  k_ra8_gwmc_opc_operation = 0x3U, 
  k_ra8_gwmc_opc_mask      = 0x3U, 
} ra8_gwmc_opc_t;

typedef enum : uint8_t {
  k_ra8_gwdcc_dt_linkfix   = 0U,  
  k_ra8_gwdcc_dt_fempty_is = 1U,  
  k_ra8_gwdcc_dt_fempty_ic = 2U,  
  k_ra8_gwdcc_dt_fempty_nd = 3U,  
  k_ra8_gwdcc_dt_fempty    = 4U,  
  k_ra8_gwdcc_dt_fsingle   = 8U,  
  k_ra8_gwdcc_dt_fstart    = 9U,  
  k_ra8_gwdcc_dt_fmid      = 10U, 
  k_ra8_gwdcc_dt_fend      = 11U, 
  k_ra8_gwdcc_dt_lempty    = 12U, 
  k_ra8_gwdcc_dt_eempty    = 13U, 
  k_ra8_gwdcc_dt_link      = 14U, 
  k_ra8_gwdcc_dt_eos       = 15U, 
} ra8_gwdcc_dt_t;

typedef struct {
  volatile uint8_t  ds_l;      
  volatile uint8_t  ds_h : 4;  
  volatile uint8_t  info0 : 4; 
  volatile uint8_t  err : 3;   
  volatile uint8_t  die : 1;   
  volatile uint8_t  dt : 4;    
  volatile uint8_t  ptr_h;     
  volatile uint32_t ptr_l;     
} ra8_gwca_basic_descriptor_t;
 
static_assert(sizeof(ra8_gwca_basic_descriptor_t) == 8U,
              "GWCA basic descriptor must be 8 bytes (HUM Ch 34.5.1.2.1).");

typedef struct {
  volatile uint8_t  ds_l;      
  volatile uint8_t  ds_h : 4;  
  volatile uint8_t  info0 : 4; 
  volatile uint8_t  err : 3;   
  volatile uint8_t  die : 1;   
  volatile uint8_t  dt : 4;    
  volatile uint8_t  ptr_h;     
  volatile uint32_t ptr_l;     
  volatile uint32_t info1_lo;  
  volatile uint32_t info1_hi;  
} ra8_gwca_ext_descriptor_t;
 
static_assert(sizeof(ra8_gwca_ext_descriptor_t) == 16U,
              "GWCA extended descriptor must be 16 bytes (HUM Ch 34.5.1.2.1).");

typedef enum : uint32_t {
  k_ra8_gwca_info1_tx_fmt_direct = (1UL << 2U),   
  k_ra8_gwca_info1_tx_dv_shift   = 16U,           
  k_ra8_gwca_info1_tx_dv_mask    = 0x7FUL << 16U, 
} ra8_gwca_info1_tx_t;

typedef enum : uint16_t {
  k_ra8_gwca_off_gwmc       = 0x0000U, 
  k_ra8_gwca_off_gwms       = 0x0004U, 
  k_ra8_gwca_off_gwdcbac0   = 0x0194U, 
  k_ra8_gwca_off_gwdcbac1   = 0x0198U, 
  k_ra8_gwca_off_gwtrc0     = 0x0200U, 
  k_ra8_gwca_off_gwtrc1     = 0x0204U, 
  k_ra8_gwca_off_gwarirm    = 0x0380U, 
  k_ra8_gwca_off_gwdcc_base = 0x0400U, 
  k_ra8_gwca_off_gwaarss    = 0x0800U, 
  k_ra8_gwca_off_gwaarsr0   = 0x0804U, 
  k_ra8_gwca_off_gwaarsr1   = 0x0808U, 
} ra8_gwca_offset_t;

typedef enum : uint32_t {
  k_ra8_gwdcc_ede        = 1UL << 8U,    
  k_ra8_gwdcc_ets        = 1UL << 9U,    
  k_ra8_gwdcc_sl         = 1UL << 10U,   
  k_ra8_gwdcc_dqt        = 1UL << 11U,   
  k_ra8_gwdcc_dcp_shift  = 16U,          
  k_ra8_gwdcc_dcp_mask   = 0x7UL << 16U, 
  k_ra8_gwdcc_balr       = 1UL << 24U,   
  k_ra8_gwdcc_osid_shift = 28U,          
  k_ra8_gwdcc_osid_mask  = 0x7UL << 28U, 
} ra8_gwdcc_bits_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_gwca_gwdcc(uint32_t queue_index)
{
  enum : uint32_t { k_ra8_gwca_max_queues = 32U  };
  if (queue_index >= k_ra8_gwca_max_queues) {
    return nullptr;
  }
  return (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwdcc_base +
                              ((uintptr_t)queue_index * sizeof(uint32_t)));
}

typedef enum : uint8_t {
  k_ra8_gptp_timer_0     = 0U, 
  k_ra8_gptp_timer_1     = 1U, 
  k_ra8_gptp_timer_count = 2U, 
} ra8_gptp_timer_idx_t;

typedef enum : uint8_t {
  k_ra8_gptp_off_ptpipv       = 0x0000U, 
  k_ra8_gptp_off_ptptmec      = 0x0010U, 
  k_ra8_gptp_off_ptptmdc      = 0x0014U, 
  k_ra8_gptp_off_timer0       = 0x0020U, 
  k_ra8_gptp_timer_stride     = 0x0040U, 
  k_ra8_gptp_off_t_ptptivc    = 0x0000U, 
  k_ra8_gptp_off_t_ptptovcl   = 0x0010U, 
  k_ra8_gptp_off_t_ptptovcm   = 0x0014U, 
  k_ra8_gptp_off_t_ptptovcu   = 0x0018U, 
  k_ra8_gptp_off_t_ptpavtptml = 0x0020U, 
  k_ra8_gptp_off_t_ptpavtptmu = 0x0024U, 
  k_ra8_gptp_off_t_ptpgptptml = 0x0030U, 
  k_ra8_gptp_off_t_ptpgptptmm = 0x0034U, 
  k_ra8_gptp_off_t_ptpgptptmu = 0x0038U, 
} ra8_gptp_layout_t;

typedef struct {
  volatile uint32_t PTPTIVC;       
  volatile uint32_t reserved04[3]; 
  volatile uint32_t PTPTOVCL;      
  volatile uint32_t PTPTOVCM;      
  volatile uint32_t PTPTOVCU;      
  volatile uint32_t reserved1c;    
  volatile uint32_t PTPAVTPTML;    
  volatile uint32_t PTPAVTPTMU;    
  volatile uint32_t reserved28[2]; 
  volatile uint32_t PTPGPTPTML;    
  volatile uint32_t PTPGPTPTMM;    
  volatile uint32_t PTPGPTPTMU;    
  volatile uint32_t reserved3c;    
} r_gptp_timer_regs_t;

typedef struct {
  volatile uint32_t PTPIPV;        
  volatile uint32_t reserved04[3]; 
  volatile uint32_t PTPTMEC;       
  volatile uint32_t PTPTMDC;       
  volatile uint32_t reserved18[2]; 
  volatile r_gptp_timer_regs_t
    TIMER[k_ra8_gptp_timer_count]; 
} r_gptp_regs_t;
 
static_assert(sizeof(r_gptp_timer_regs_t) == (size_t)k_ra8_gptp_timer_stride,
              "GPTP per-timer block must be 0x40 bytes (HUM Table 35.3)");
static_assert(offsetof(r_gptp_timer_regs_t, PTPTIVC) == (size_t)k_ra8_gptp_off_t_ptptivc,
              "PTPTIVCt offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPTOVCL) == (size_t)k_ra8_gptp_off_t_ptptovcl,
              "PTPTOVCtL offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPTOVCM) == (size_t)k_ra8_gptp_off_t_ptptovcm,
              "PTPTOVCtM offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPTOVCU) == (size_t)k_ra8_gptp_off_t_ptptovcu,
              "PTPTOVCtU offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPAVTPTML) == (size_t)k_ra8_gptp_off_t_ptpavtptml,
              "PTPAVTPTMtL offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPAVTPTMU) == (size_t)k_ra8_gptp_off_t_ptpavtptmu,
              "PTPAVTPTMtU offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPGPTPTML) == (size_t)k_ra8_gptp_off_t_ptpgptptml,
              "PTPGPTPTMtL offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPGPTPTMM) == (size_t)k_ra8_gptp_off_t_ptpgptptmm,
              "PTPGPTPTMtM offset");
static_assert(offsetof(r_gptp_timer_regs_t, PTPGPTPTMU) == (size_t)k_ra8_gptp_off_t_ptpgptptmu,
              "PTPGPTPTMtU offset");
static_assert(offsetof(r_gptp_regs_t, PTPIPV) == (size_t)k_ra8_gptp_off_ptpipv, "PTPIPV offset");
static_assert(offsetof(r_gptp_regs_t, PTPTMEC) == (size_t)k_ra8_gptp_off_ptptmec, "PTPTMEC offset");
static_assert(offsetof(r_gptp_regs_t, PTPTMDC) == (size_t)k_ra8_gptp_off_ptptmdc, "PTPTMDC offset");
static_assert(offsetof(r_gptp_regs_t, TIMER) == (size_t)k_ra8_gptp_off_timer0, "TIMER[0] offset");

RA8_HW_REGISTER_ACCESS
static inline volatile r_gptp_regs_t* ra8_gptp(void)
{
  /* HUM Ch 35.2 "gPTP Register List" Table 35.3 p 1926 -- base GPTP =
   * 0x403E_0000 (secure) / GPTP_NS = 0x503E_0000. */
  return (volatile r_gptp_regs_t*)k_ra8_gptp_base_addr;
}
 
#ifdef __cplusplus
}
#endif