Ethernet controller base addresses for the Renesas RA8D2. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_ether_regs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	r_eswm_regs_t
	Minimal Ethernet Switch Module (ESWM) register window. More...
struct	r_mfwd_regs_t
	Minimal Message Forwarding Engine (MFWD) register window. More...
struct	r_coma_regs_t
	Minimal Common Agent (COMA) register window. More...
struct	r_gwca_regs_t
	Minimal CPU Agent (GWCA) register window. More...
struct	ra8_gwca_basic_descriptor_t
	8-byte basic descriptor (HUM Ch 34.5.1.2 "General Formats"). More...
struct	ra8_gwca_ext_descriptor_t
	16-byte extended descriptor (HUM Ch 34.5.1.2 "Extended descriptor", GWDCCi.ETS == 0 && GWDCCi.EDE == 1). More...
struct	r_gptp_timer_regs_t
	One GPTP timer unit's register block (HUM Ch 35.3.2 / 35.3.3). More...
struct	r_gptp_regs_t
	Ethernet Generic PTP Timer (GPTP) register window, HUM Ch 35. More...

Enumerations
enum	ra8_ether_addr_t : uintptr_t { k_ra8_etha0_base_addr = 0x403CA000UL , k_ra8_etha1_base_addr = 0x403CC000UL , k_ra8_rmac0_base_addr = 0x403CB000UL , k_ra8_rmac1_base_addr = 0x403CD000UL , k_ra8_mfwd_base_addr = 0x403C0000UL , k_ra8_coma_base_addr = 0x403C9000UL , k_ra8_gptp_base_addr = 0x403E0000UL , k_ra8_eswm_base_addr = 0x403C8000UL , k_ra8_gwca0_base_addr = 0x403CE000UL }
enum	ra8_coma_offset_t : uint16_t { k_ra8_coma_off_ric = 0x000U , k_ra8_coma_off_rrc = 0x004U , k_ra8_coma_off_rcec = 0x008U , k_ra8_coma_off_cabpirm = 0x140U }
	Per-register offsets into the COMA (Common Agent) block. More...
enum	ra8_coma_bit_t : uint32_t { k_ra8_coma_rrc_rr = (1UL << 0U) , k_ra8_coma_rcec_rce = (1UL << 16U) , k_ra8_coma_rcec_ace_mask = 0x7FUL , k_ra8_coma_cabpirm_bpiog = (1UL << 0U) , k_ra8_coma_cabpirm_bpr = (1UL << 1U) }
	Bit positions in the COMA bring-up registers. More...
enum	ra8_eswm_mii_offset_t : uint32_t { k_ra8_eswm_off_miirr = 0x19400UL , k_ra8_eswm_off_miicr0 = 0x19404UL , k_ra8_eswm_off_miicr1 = 0x19408UL }
	Offsets into the ESWM Media-Interface configuration window. More...
enum	ra8_eswm_miirr_bit_t : uint32_t { k_ra8_eswm_miirr_rgrst0 = (1UL << 0U) , k_ra8_eswm_miirr_rgrst1 = (1UL << 1U) , k_ra8_eswm_miirr_rmrst0 = (1UL << 8U) , k_ra8_eswm_miirr_rmrst1 = (1UL << 9U) }
	Bit positions in ESWM.MIIRR (Media Interface Reset Register). More...
enum	ra8_eswm_miicr_field_t : uint32_t { k_ra8_eswm_miicr_miisel_mii = 0UL , k_ra8_eswm_miicr_miisel_rgmii = 1UL , k_ra8_eswm_miicr_miisel_rmii = 2UL , k_ra8_eswm_miicr_miisel_mask = 0x3UL , k_ra8_eswm_miicr_divstp = (1UL << 8U) , k_ra8_eswm_miicr_txcide = (1UL << 12U) }
	Field encodings for ESWM.MIICRn (Media Interface Control n). More...
enum	ra8_gwmc_opc_t : uint32_t { k_ra8_gwmc_opc_reset = 0x0U , k_ra8_gwmc_opc_disable = 0x1U , k_ra8_gwmc_opc_config = 0x2U , k_ra8_gwmc_opc_operation = 0x3U , k_ra8_gwmc_opc_mask = 0x3U }
	GWMC.OPC operation-mode values (HUM Ch 34.3.1 "GWMC" p 1797). More...
enum	ra8_gwdcc_dt_t : uint8_t { k_ra8_gwdcc_dt_linkfix = 0U , k_ra8_gwdcc_dt_fempty_is = 1U , k_ra8_gwdcc_dt_fempty_ic = 2U , k_ra8_gwdcc_dt_fempty_nd = 3U , k_ra8_gwdcc_dt_fempty = 4U , k_ra8_gwdcc_dt_fsingle = 8U , k_ra8_gwdcc_dt_fstart = 9U , k_ra8_gwdcc_dt_fmid = 10U , k_ra8_gwdcc_dt_fend = 11U , k_ra8_gwdcc_dt_lempty = 12U , k_ra8_gwdcc_dt_eempty = 13U , k_ra8_gwdcc_dt_link = 14U , k_ra8_gwdcc_dt_eos = 15U }
	Descriptor type field values (HUM Ch 34.5.1.2.2 "Descriptor Types"). More...
enum	ra8_gwca_info1_tx_t : uint32_t { k_ra8_gwca_info1_tx_fmt_direct = (1UL << 2U) , k_ra8_gwca_info1_tx_dv_shift = 16U , k_ra8_gwca_info1_tx_dv_mask = 0x7FUL << 16U }
	Bit composition of the INFO1 half of a TX extended descriptor. More...
enum	ra8_gwca_offset_t : uint16_t { k_ra8_gwca_off_gwmc = 0x0000U , k_ra8_gwca_off_gwms = 0x0004U , k_ra8_gwca_off_gwdcbac0 = 0x0194U , k_ra8_gwca_off_gwdcbac1 = 0x0198U , k_ra8_gwca_off_gwtrc0 = 0x0200U , k_ra8_gwca_off_gwtrc1 = 0x0204U , k_ra8_gwca_off_gwarirm = 0x0380U , k_ra8_gwca_off_gwdcc_base = 0x0400U , k_ra8_gwca_off_gwaarss = 0x0800U , k_ra8_gwca_off_gwaarsr0 = 0x0804U , k_ra8_gwca_off_gwaarsr1 = 0x0808U }
	Offsets into R_GWCA0 for the registers the upcoming port needs. More...
enum	ra8_gwdcc_bits_t : uint32_t { k_ra8_gwdcc_ede = 1UL << 8U , k_ra8_gwdcc_ets = 1UL << 9U , k_ra8_gwdcc_sl = 1UL << 10U , k_ra8_gwdcc_dqt = 1UL << 11U , k_ra8_gwdcc_dcp_shift = 16U , k_ra8_gwdcc_dcp_mask = 0x7UL << 16U , k_ra8_gwdcc_balr = 1UL << 24U , k_ra8_gwdcc_osid_shift = 28U , k_ra8_gwdcc_osid_mask = 0x7UL << 28U }
	Bit positions/masks for GWDCC[i] (HUM Ch 34 + FSP CMSIS header). More...
enum	ra8_gptp_timer_idx_t : uint8_t { k_ra8_gptp_timer_0 = 0U , k_ra8_gptp_timer_1 = 1U , k_ra8_gptp_timer_count = 2U }
	GPTP timer instance index (HUM Table 35.3 lists t = 0, 1). More...
enum	ra8_gptp_layout_t : uint8_t { k_ra8_gptp_off_ptpipv = 0x0000U , k_ra8_gptp_off_ptptmec = 0x0010U , k_ra8_gptp_off_ptptmdc = 0x0014U , k_ra8_gptp_off_timer0 = 0x0020U , k_ra8_gptp_timer_stride = 0x0040U , k_ra8_gptp_off_t_ptptivc = 0x0000U , k_ra8_gptp_off_t_ptptovcl = 0x0010U , k_ra8_gptp_off_t_ptptovcm = 0x0014U , k_ra8_gptp_off_t_ptptovcu = 0x0018U , k_ra8_gptp_off_t_ptpavtptml = 0x0020U , k_ra8_gptp_off_t_ptpavtptmu = 0x0024U , k_ra8_gptp_off_t_ptpgptptml = 0x0030U , k_ra8_gptp_off_t_ptpgptptmm = 0x0034U , k_ra8_gptp_off_t_ptpgptptmu = 0x0038U }
	Byte offsets that r_gptp_regs_t / r_gptp_timer_regs_t must hit. More...

Functions
static volatile uint32_t *	ra8_coma_rrc (void)
	Get pointer to the 32-bit COMA.RRC (Reset Configuration).
static volatile uint32_t *	ra8_coma_rcec (void)
	Get pointer to the 32-bit COMA.RCEC (Clock Enable Configuration).
static volatile uint32_t *	ra8_coma_cabpirm (void)
	Get pointer to the 32-bit COMA.CABPIRM (Buf-pool Init/Reset/Monitor).
static volatile r_eswm_regs_t *	ra8_eswm (void)
	Get pointer to the ESWM register block.
static volatile uint32_t *	ra8_eswm_miirr (void)
	Get pointer to ESWM.MIIRR (32-bit).
static volatile uint32_t *	ra8_eswm_miicr0 (void)
	Get pointer to ESWM.MIICR0 (32-bit, RMAC port 0).
static volatile uint32_t *	ra8_eswm_miicr1 (void)
	Get pointer to ESWM.MIICR1 (32-bit, RMAC port 1).
static volatile r_mfwd_regs_t *	ra8_mfwd (void)
	Get pointer to the MFWD register block.
static volatile r_coma_regs_t *	ra8_coma (void)
	Get pointer to the COMA register block.
static volatile r_gwca_regs_t *	ra8_gwca (void)
	Get pointer to the GWCA register block.
static volatile uint32_t *	ra8_gwca_gwdcc (uint32_t queue_index)
	Get pointer to GWDCC[queue_index] (per-queue descriptor chain cfg).
static volatile r_gptp_regs_t *	ra8_gptp (void)
	Get pointer to the GPTP register block.

Detailed Description

Ethernet controller base addresses for the Renesas RA8D2.

RA8D2 has a gigabit Ethernet subsystem composed of several blocks (GMAC A/B, MII forwarder, TSNSW, GPTP). Base addresses below come from R7KA8D2KF. Drivers land with a real network stack.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_ether_regs.h.

Enumeration Type Documentation

◆ ra8_coma_bit_t

enum ra8_coma_bit_t : uint32_t

Bit positions in the COMA bring-up registers.

Enumerator
k_ra8_coma_rrc_rr	RRC.RR – pulse to reset ESWM IP.
k_ra8_coma_rcec_rce	RCEC.RCE – enable switch clock.
k_ra8_coma_rcec_ace_mask	RCEC.ACE[6:0] – agent clock enable.
k_ra8_coma_cabpirm_bpiog	CABPIRM.BPIOG – buf-pool init kick.
k_ra8_coma_cabpirm_bpr	CABPIRM.BPR – buf-pool ready flag.

Definition at line 65 of file ra8_ether_regs.h.

◆ ra8_coma_offset_t

enum ra8_coma_offset_t : uint16_t

Per-register offsets into the COMA (Common Agent) block.

COMA wraps the ESWM peripheral with the bus-arbitration counters and the shared per-port descriptor fences. The first four registers (RIC / RRC / RCEC / RNS) are the "bring-up" surface; without:

RRC pulsed (reset the ESWM IP),
RCEC.RCE (bit 16) set to 1 (enable the switch clock),
CABPIRM.BPIOG pulsed (reset the COMA buffer pool), the per-port RMAC and ETHA register windows remain inaccessible even after their MSTP gates are released and PDCTRESWM has powered the domain on. Discovered via J-Link MMIO probe on EK-RA8D2 hardware; FSP r_layer3_switch_reset_coma confirms.

Enumerator
k_ra8_coma_off_ric	Interrupt Configuration.
k_ra8_coma_off_rrc	Reset Configuration (RR bit 0).
k_ra8_coma_off_rcec	Clock Enable Cfg (RCE bit 16).
k_ra8_coma_off_cabpirm	Buf-pool Init/Reset (BPIOG / BPR). HUM Ch 31 p 1599.

Definition at line 54 of file ra8_ether_regs.h.

◆ ra8_eswm_mii_offset_t

enum ra8_eswm_mii_offset_t : uint32_t

Offsets into the ESWM Media-Interface configuration window.

HUM Ch 29 (ESWM) – the per-port media-interface registers live far past the CTRL/STS block. Cross-checked against FSP CMSIS header R7KA8D2KF_core0.h (R_ESWM_Type members MIIRR and MIICR0/1 at the offsets below). Used by the RMAC PHY bring-up path to:

Select RGMII vs RMII vs MII for each MAC port.
Enable the per-port media-interface block (MIIRR.RGRST/RMRST).

Without MIIRR's per-port enable bit set, the media interface block stays in reset – no TXC, no MDC, no RGMII clocking.

Enumerator
k_ra8_eswm_off_miirr	Media Interface Reset Register.
k_ra8_eswm_off_miicr0	Media Interface Control 0 (RMAC0).
k_ra8_eswm_off_miicr1	Media Interface Control 1 (RMAC1).

Definition at line 132 of file ra8_ether_regs.h.

◆ ra8_eswm_miicr_field_t

enum ra8_eswm_miicr_field_t : uint32_t

Field encodings for ESWM.MIICRn (Media Interface Control n).

MIISEL[1:0] selects the MII flavour driven onto the n-th MAC pin group: 0 = MII/GMII, 1 = RGMII, 2 = RMII. TXCIDE (bit 12) enables the on-chip TXC internal delay for RGMII (matches the FSP default "RGMII + TX skew" board profile).

Enumerator
k_ra8_eswm_miicr_miisel_mii	MIISEL = MII/GMII.
k_ra8_eswm_miicr_miisel_rgmii	MIISEL = RGMII.
k_ra8_eswm_miicr_miisel_rmii	MIISEL = RMII.
k_ra8_eswm_miicr_miisel_mask	MIISEL field mask (bits 1:0).
k_ra8_eswm_miicr_divstp	DIVSTP – gate the clock div.
k_ra8_eswm_miicr_txcide	TXCIDE – TXC internal delay.

Definition at line 164 of file ra8_ether_regs.h.

◆ ra8_eswm_miirr_bit_t

enum ra8_eswm_miirr_bit_t : uint32_t

Bit positions in ESWM.MIIRR (Media Interface Reset Register).

HUM Ch 29.2.1.2 "MIIRR" p 1289 – each RGRSTn / RMRSTn bit is an ENABLE, not an active-high reset: 0 = Reset (block held in reset), 1 = Enable (block operational). Set the bit to bring the media-interface block out of reset.

Enumerator
k_ra8_eswm_miirr_rgrst0	RGMII0 enable (1 = enable, 0 = reset).
k_ra8_eswm_miirr_rgrst1	RGMII1 enable (1 = enable, 0 = reset).
k_ra8_eswm_miirr_rmrst0	RMII0 enable (1 = enable, 0 = reset).
k_ra8_eswm_miirr_rmrst1	RMII1 enable (1 = enable, 0 = reset).

Definition at line 147 of file ra8_ether_regs.h.

◆ ra8_ether_addr_t

enum ra8_ether_addr_t : uintptr_t

Enumerator
k_ra8_etha0_base_addr	RA8 etha0 base address.
k_ra8_etha1_base_addr	RA8 etha1 base address.
k_ra8_rmac0_base_addr	RA8 rmac0 base address.
k_ra8_rmac1_base_addr	RA8 rmac1 base address.
k_ra8_mfwd_base_addr	RA8 mfwd base address.
k_ra8_coma_base_addr	RA8 coma base address.
k_ra8_gptp_base_addr	RA8 gptp base address.
k_ra8_eswm_base_addr	RA8 eswm base address.
k_ra8_gwca0_base_addr	RA8 gwca0 base address.

Definition at line 26 of file ra8_ether_regs.h.

◆ ra8_gptp_layout_t

enum ra8_gptp_layout_t : uint8_t

Byte offsets that r_gptp_regs_t / r_gptp_timer_regs_t must hit.

Mirrors HUM Table 35.3 "gPTP timer registers" p 1926 so the static_asserts below cannot drift from the manual. Offsets marked _t are relative to a single timer block; the rest are absolute within the GPTP window.

Invariant: Every value is a multiple of 4 (all GPTP registers are 32 bit).

Example:: static_assert(offsetof(r_gptp_regs_t, PTPTMEC) == k_ra8_gptp_off_ptptmec, "");

k_ra8_gptp_off_ptptmec
@ k_ra8_gptp_off_ptptmec
PTPTMEC Timer Enable Cfg.
Definition ra8_ether_regs.h:515

r_gptp_regs_t
Ethernet Generic PTP Timer (GPTP) register window, HUM Ch 35.
Definition ra8_ether_regs.h:609

See also: r_gptp_regs_t

Enumerator
k_ra8_gptp_off_ptpipv	PTPIPV IP Version.
k_ra8_gptp_off_ptptmec	PTPTMEC Timer Enable Cfg.
k_ra8_gptp_off_ptptmdc	PTPTMDC Timer Disable Cfg.
k_ra8_gptp_off_timer0	First per-timer block.
k_ra8_gptp_timer_stride	Per-timer block stride (0x40 x t).
k_ra8_gptp_off_t_ptptivc	PTPTIVCt in-block offset.
k_ra8_gptp_off_t_ptptovcl	PTPTOVCtL in-block offset.
k_ra8_gptp_off_t_ptptovcm	PTPTOVCtM in-block offset.
k_ra8_gptp_off_t_ptptovcu	PTPTOVCtU in-block offset.
k_ra8_gptp_off_t_ptpavtptml	PTPAVTPTMtL in-block offset.
k_ra8_gptp_off_t_ptpavtptmu	PTPAVTPTMtU in-block offset.
k_ra8_gptp_off_t_ptpgptptml	PTPGPTPTMtL in-block offset.
k_ra8_gptp_off_t_ptpgptptmm	PTPGPTPTMtM in-block offset.
k_ra8_gptp_off_t_ptpgptptmu	PTPGPTPTMtU in-block offset.

Definition at line 513 of file ra8_ether_regs.h.

◆ ra8_gptp_timer_idx_t

enum ra8_gptp_timer_idx_t : uint8_t

GPTP timer instance index (HUM Table 35.3 lists t = 0, 1).

The GPTP block instantiates two independent timer units. Every per-timer register is placed at base + 0x0020 + 0x40 * t, which is exactly the stride of r_gptp_timer_regs_t.

Invariant: A timer index is always < k_ra8_gptp_timer_count.

Example:: volatile r_gptp_timer_regs_t* t0 = &ra8_gptp()->TIMER[k_ra8_gptp_timer_0];

k_ra8_gptp_timer_0
@ k_ra8_gptp_timer_0
Timer unit 0 (registers at +0x0020).
Definition ra8_ether_regs.h:489

ra8_gptp
static volatile r_gptp_regs_t * ra8_gptp(void)
Get pointer to the GPTP register block.
Definition ra8_ether_regs.h:646

r_gptp_regs_t::TIMER
volatile r_gptp_timer_regs_t TIMER[k_ra8_gptp_timer_count]
+0x0020 + 0x40 x t Per-timer blocks.
Definition ra8_ether_regs.h:616

r_gptp_timer_regs_t
One GPTP timer unit's register block (HUM Ch 35.3.2 / 35.3.3).
Definition ra8_ether_regs.h:559

See also: r_gptp_timer_regs_t

Enumerator
k_ra8_gptp_timer_0	Timer unit 0 (registers at +0x0020).
k_ra8_gptp_timer_1	Timer unit 1 (registers at +0x0060).
k_ra8_gptp_timer_count	Number of timer units on this part.

Definition at line 488 of file ra8_ether_regs.h.

◆ ra8_gwca_info1_tx_t

enum ra8_gwca_info1_tx_t : uint32_t

Bit composition of the INFO1 half of a TX extended descriptor.

HUM Ch 34.5.3 + FSP st_info1_tx. INFO1[63:0] spans ra8_gwca_ext_descriptor_t info1_lo (INFO1[31:0]) and info1_hi (INFO1[63:32]). The two fields the TX path programs:

FMT (INFO1 bit 2, in info1_lo): 0 = ethernet descriptor (the MFWD forwarding engine routes by destination MAC), 1 = direct descriptor (the DV field routes the frame, forwarding bypassed).
DV[6:0] (INFO1 bits 48..54, in info1_hi bits 22..16): the destination-port bit vector, used only when FMT = direct. FI (INFO1 bit 0) stays 0 so the RMAC appends the FCS.

Enumerator
k_ra8_gwca_info1_tx_fmt_direct	info1_lo: FMT = direct descriptor.
k_ra8_gwca_info1_tx_dv_shift	info1_hi: DV[6:0] field shift.
k_ra8_gwca_info1_tx_dv_mask	info1_hi: DV[6:0] field mask.

Definition at line 395 of file ra8_ether_regs.h.

◆ ra8_gwca_offset_t

enum ra8_gwca_offset_t : uint16_t

Offsets into R_GWCA0 for the registers the upcoming port needs.

Subset of the full R_GWCA0_Type layout from the FSP R7KA8D2KF_core0.h CMSIS header. Reading these via the existing r_gwca_regs_t legacy view is unsafe (the struct only covers the first 16 bytes); use explicit pointer arithmetic from k_ra8_gwca0_base_addr + offset until the full struct lands.

See also: reference_fsp_source memory note for the full register list.

Enumerator
k_ra8_gwca_off_gwmc	Mode Configuration.
k_ra8_gwca_off_gwms	Mode Status.
k_ra8_gwca_off_gwdcbac0	Descriptor chain base addr 0 (upper).
k_ra8_gwca_off_gwdcbac1	Descriptor chain base addr 1 (lower).
k_ra8_gwca_off_gwtrc0	TX Request Cfg, queues 0..31.
k_ra8_gwca_off_gwtrc1	TX Request Cfg, queues 32..63.
k_ra8_gwca_off_gwarirm	AXI RAM Init Req Monitoring (FSP-confirmed offset).
k_ra8_gwca_off_gwdcc_base	GWDCC[0]; stride 4 bytes.
k_ra8_gwca_off_gwaarss	AXI Addr RAM Searching Setting.
k_ra8_gwca_off_gwaarsr0	AXI Addr RAM Searching Result0.
k_ra8_gwca_off_gwaarsr1	AXI Addr RAM Searching Result1.

Definition at line 413 of file ra8_ether_regs.h.

◆ ra8_gwdcc_bits_t

enum ra8_gwdcc_bits_t : uint32_t

Bit positions/masks for GWDCC[i] (HUM Ch 34 + FSP CMSIS header).

Per-queue Descriptor Chain Configuration. SM[1:0] is the Synchronization Mode (00b = Normal / full descriptor write-back, 01b = No-write-back) – always left 0, so it has no named constant here. EDE / ETS toggle extended descriptors; SL selects a "stop-on-last" mode; DQT picks TX (1) vs RX (0); DCP carries the 3-bit class priority; BALR (Base Address Load Request) reloads the AXI address RAM current_address to the chain base; OSID is the outstanding-transaction stream ID.

Enumerator
k_ra8_gwdcc_ede	RA8 gwdcc ede.
k_ra8_gwdcc_ets	RA8 gwdcc ets.
k_ra8_gwdcc_sl	RA8 gwdcc sl.
k_ra8_gwdcc_dqt	0 = RX queue, 1 = TX queue.
k_ra8_gwdcc_dcp_shift	RA8 gwdcc dcp shift.
k_ra8_gwdcc_dcp_mask	RA8 gwdcc dcp mask.
k_ra8_gwdcc_balr	RA8 gwdcc balr.
k_ra8_gwdcc_osid_shift	RA8 gwdcc osid shift.
k_ra8_gwdcc_osid_mask	RA8 gwdcc osid mask.

Definition at line 440 of file ra8_ether_regs.h.

◆ ra8_gwdcc_dt_t

enum ra8_gwdcc_dt_t : uint8_t

Descriptor type field values (HUM Ch 34.5.1.2.2 "Descriptor Types").

Set on the 4-bit DT field of every basic descriptor. See layer3_switch_basic_descriptor_t below.

Enumerator
k_ra8_gwdcc_dt_linkfix	LINKFIX – chain head pointer.
k_ra8_gwdcc_dt_fempty_is	FEMPTY_IS – empty, incremental start.
k_ra8_gwdcc_dt_fempty_ic	FEMPTY_IC – empty, incremental cont.
k_ra8_gwdcc_dt_fempty_nd	FEMPTY_ND – reject data.
k_ra8_gwdcc_dt_fempty	FEMPTY – empty, full frame slot.
k_ra8_gwdcc_dt_fsingle	FSINGLE – single-fragment frame.
k_ra8_gwdcc_dt_fstart	FSTART – multi-fragment start.
k_ra8_gwdcc_dt_fmid	FMID – multi-fragment middle.
k_ra8_gwdcc_dt_fend	FEND – multi-fragment end.
k_ra8_gwdcc_dt_lempty	LEMPTY – queue disabled.
k_ra8_gwdcc_dt_eempty	EEMPTY – TX queue paused.
k_ra8_gwdcc_dt_link	LINK – chain continuation.
k_ra8_gwdcc_dt_eos	EOS – end-of-set.

Definition at line 309 of file ra8_ether_regs.h.

◆ ra8_gwmc_opc_t

enum ra8_gwmc_opc_t : uint32_t

GWMC.OPC operation-mode values (HUM Ch 34.3.1 "GWMC" p 1797).

The ESWM state machine accepts mode transitions written here. The FSP-named LAYER3_SWITCH_AGENT_MODE_xxx enum maps 1:1. Writing the new mode and polling GWMS.OPS until it reflects the value is the "transition request" protocol used by the FSP r_layer3_switch driver.

Enumerator
k_ra8_gwmc_opc_reset	RR: Reset request.
k_ra8_gwmc_opc_disable	DR: Disable request.
k_ra8_gwmc_opc_config	CR: Config request – LINKFIX writable here.
k_ra8_gwmc_opc_operation	OR: Operation request – frames flow.
k_ra8_gwmc_opc_mask	RA8 gwmc opc mask.