ra8_eth.c

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#include "ra8_eth.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_eth_gwca.h"
#include "ra8_eth_internal.h"
#include "ra8_eth_mfwd.h"
#include "ra8_etha.h"
#include "ra8_etha_regs.h"
#include "ra8_ether_regs.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
#include "ra8_rmac.h"
#include "ra8_rmac_regs.h"
#include "ra8_time.h"

static const char* s_tag = "ETH";

static ra8_eth_event_fn_t s_eth_fn;

static void* s_eth_ctx;

typedef enum : uint8_t {
  k_eth_fwpbfc_mask = 0x7FU, 
} eth_fwpbfc_t;

typedef enum : uint16_t {
  k_ra8_eth_linkfix_count = 4U,                                     
  k_ra8_eth_def_rx_q_idx  = 0U,                                     
  k_ra8_eth_def_tx_q_idx  = 1U,                                     
  k_ra8_eth_rx_ring_depth = (uint16_t)(k_ra8_eth_num_rx_desc + 1U), 
  k_ra8_eth_tx_ring_depth = (uint16_t)(k_ra8_eth_num_tx_desc + 1U), 
} ra8_eth_layout_t;

typedef enum : uint32_t {
  k_ra8_eth_step_ok_1   = 1U,    
  k_ra8_eth_step_ok_2   = 2U,    
  k_ra8_eth_step_ok_3   = 3U,    
  k_ra8_eth_step_ok_4   = 4U,    
  k_ra8_eth_step_fail_1 = 0x11U, 
  k_ra8_eth_step_fail_3 = 0x13U, 
  k_ra8_eth_step_fail_4 = 0x14U, 
} ra8_eth_step_t;

alignas(16) static ra8_gwca_basic_descriptor_t s_linkfix_table[k_ra8_eth_linkfix_count];

alignas(16) static ra8_gwca_basic_descriptor_t s_rx_chain[k_ra8_eth_rx_ring_depth];

alignas(16) static ra8_gwca_ext_descriptor_t s_tx_chain[k_ra8_eth_tx_ring_depth];
 
#ifndef UNIT_TEST
alignas(16) static uint8_t s_rx_pool_storage[k_ra8_eth_num_rx_desc * k_ra8_eth_buf_size];

alignas(16) static uint8_t s_tx_pool_storage[k_ra8_eth_num_tx_desc * k_ra8_eth_buf_size];
#endif /* UNIT_TEST */

typedef enum : uintptr_t {
  k_ra8_eth_host_rx_pool_addr = 0x22100000UL, 
  k_ra8_eth_host_tx_pool_addr = 0x22180000UL, 
} ra8_eth_host_pool_layout_t;

RA8_INTERNAL
static inline uint8_t* internal_eth_rx_pool(void)
{
#ifdef UNIT_TEST
  return (uint8_t*)k_ra8_eth_host_rx_pool_addr;
#else
  return s_rx_pool_storage;
#endif
}

RA8_INTERNAL
static inline uint8_t* internal_eth_tx_pool(void)
{
#ifdef UNIT_TEST
  return (uint8_t*)k_ra8_eth_host_tx_pool_addr;
#else
  return s_tx_pool_storage;
#endif
}

static ra8_eth_gwca_default_state_t s_gwca_state;

ra8_eth_state_t s_eth_state;

bool g_eth_mac_speed_resynced = false;

RA8_INTERNAL
static inline void internal_stat_inc(uint32_t* counter)
{
  if (*counter != UINT32_MAX) {
    *counter += 1U;
  }
}

RA8_INTERNAL
static inline void internal_byte_copy(uint8_t* dst, const uint8_t* src, uint32_t n)
{
  for (uint32_t i = 0U; i < n; ++i) {
    dst[i] = src[i];
  }
}
 
ra8_rmac_port_t priv_ra8_eth_channel_to_port(uint8_t channel)
{
  if (channel == 0U) {
    return k_ra8_rmac_port_0;
  }
  return k_ra8_rmac_port_1;
}

RA8_INTERNAL
static ra8_err_t internal_resolve_sizes(const ra8_eth_cfg_t* cfg,
                                        uint16_t*            tx_count,
                                        uint16_t*            rx_count,
                                        uint16_t*            buf_size)
{
  uint16_t tx = cfg->num_tx_descriptors;
  uint16_t rx = cfg->num_rx_descriptors;
  uint16_t bs = cfg->buffer_size;
  if (tx == 0U) {
    tx = k_ra8_eth_num_tx_desc;
  }
  if (rx == 0U) {
    rx = k_ra8_eth_num_rx_desc;
  }
  if (bs == 0U) {
    bs = k_ra8_eth_buf_size;
  }
  if (tx > k_ra8_eth_num_tx_desc) {
    return k_ra8_err_invalid_arg;
  }
  if (rx > k_ra8_eth_num_rx_desc) {
    return k_ra8_err_invalid_arg;
  }
  if ((bs < k_ra8_eth_min_frame) || (bs > k_ra8_eth_buf_size)) {
    return k_ra8_err_invalid_arg;
  }
  *tx_count = tx;
  *rx_count = rx;
  *buf_size = bs;
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_bring_up_rmac(const ra8_eth_cfg_t* cfg)
{
  /* The board-level ``ra8_board_ethernet_init`` (or its equivalent for
   * non-EK boards) is expected to have already programmed RMAC's MPIC
   * (PIS / LSC / PIPP / PSMCS), enabled the MSTP gate, and brought the
   * matching ETHA into OPERATION mode. Overwriting MPIC here would
   * clobber the carefully-computed MDC clock divider (PSMCS) and force
   * the wrong PHY interface mode (MII instead of RGMII). The only
   * RMAC-level state ``ra8_eth_open`` still has to programme is the
   * MAC address the application chose.
   *
   * HUM Ch 33.4 "MRMAC0 / MRMAC1" p 1707 -- the MAC address registers
   * are paired with MPIC under the same write-once gate: silent on
   * MAC writes while ETHA is in OPERATION. Bench-confirmed on
   * EK-RA8D2: without the DISABLE -> CONFIG -> {MAC write} -> DISABLE
   * -> OPERATION bracket, MRMAC0 / MRMAC1 read back as 0 after
   * ra8_eth_open completes, and every wire-side ARP "who-has 192.168.
   * .1.42" gets dropped at the RMAC perfect-match comparator before
   * the GWCA descriptor ring ever sees it.
   *
   * The board layer ran the bracket once during ra8_rmac_init; we have
   * to repeat it here so the application-supplied MAC actually lands
   * in MRMAC0/MRMAC1. */
  const ra8_rmac_port_t rmac_port = priv_ra8_eth_channel_to_port(cfg->channel);
  const ra8_etha_port_t etha_port =
    (cfg->channel == 0U) ? (ra8_etha_port_t)k_ra8_etha_port_0 : (ra8_etha_port_t)k_ra8_etha_port_1;
  uint8_t mac_copy[k_ra8_eth_mac_len];
  for (uint8_t i = 0U; i < (uint8_t)k_ra8_eth_mac_len; ++i) {
    mac_copy[i] = cfg->mac_address[i];
  }
 
  /* HUM Ch 32.3.1.1 "EAMC : Mode Command Register" p 1631 -- ETHA
   * mode-transition sequence. DISABLE before CONFIG so the ESWM
   * accepts the request even if the port was already in OPERATION. */
  ra8_err_t err = ra8_etha_set_mode(etha_port, k_ra8_etha_opc_disable);
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_etha_set_mode(etha_port, k_ra8_etha_opc_config);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* HUM Ch 33.4 "MRMAC0 / MRMAC1" p 1707 -- writes only stick while
   * the paired ETHA is in CONFIG. */
  const ra8_err_t mac_err = ra8_rmac_set_mac_address(rmac_port, mac_copy);
 
  /* Always return to OPERATION even on MAC write failure so the chip
   * doesn't end up parked in CONFIG. */
  const ra8_err_t dis_err = ra8_etha_set_mode(etha_port, k_ra8_etha_opc_disable);
  const ra8_err_t op_err  = ra8_etha_set_mode(etha_port, k_ra8_etha_opc_operation);
  if (mac_err != k_ra8_ok) {
    return mac_err;
  }
  if (dis_err != k_ra8_ok) {
    return dis_err;
  }
  return op_err;
}
 
ra8_err_t ra8_eth_init(void)
{
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C" p 446 */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_eswm);
  /* GCOVR_EXCL_BR_START -- MSTP HW readback */
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "eth_init: mstp enable");
  /* GCOVR_EXCL_BR_STOP */
 
  volatile r_eswm_regs_t* reg = ra8_eswm();
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  reg->ESWM_CTRL = 0U;
  reg->ESWM_STS  = 0U;
  reg->ESWM_IE   = 0U;
  reg->ESWM_ICLR = 0U;
  ra8_log_info(s_tag, "eth_init (ESWM)");
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_deinit(void)
{
  volatile r_eswm_regs_t* reg = ra8_eswm();
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  reg->ESWM_CTRL = 0U;
  reg->ESWM_IE   = 0U;
  s_eth_fn       = nullptr;
  s_eth_ctx      = nullptr;
  return ra8_mstp_disable(k_ra8_mstp_eswm);
}
 
ra8_err_t ra8_eth_get_status(uint32_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "out_mask must not be nullptr");
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  *out_mask = ra8_eswm()->ESWM_STS;
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_clear_status(uint32_t mask)
{
  volatile r_eswm_regs_t* reg = ra8_eswm();
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  reg->ESWM_ICLR = mask;
  reg->ESWM_STS  = reg->ESWM_STS & ~mask;
  return k_ra8_ok;
}
 
void ra8_eth_attach_handler(ra8_eth_event_fn_t fn, void* ctx)
{
  s_eth_fn  = fn;
  s_eth_ctx = ctx;
}
 
RA8_ISR_SAFE
void ra8_eth_dispatch(void)
{
  volatile r_eswm_regs_t* reg = ra8_eswm();
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  const uint32_t           mask = reg->ESWM_STS;
  const ra8_eth_event_fn_t fn   = s_eth_fn;
  void* const              ctx  = s_eth_ctx;
  reg->ESWM_ICLR                = mask;
  reg->ESWM_STS                 = 0U;
  if (fn != nullptr) {
    fn(ctx, mask);
  }
}
 
ra8_err_t ra8_eth_enter_stop(void)
{
  /* HUM Ch 29 "Layer 3 Ethernet Switch Module (ESWM)" p 1287 */
  ra8_eswm()->ESWM_CTRL = 0U;
  return ra8_mstp_disable(k_ra8_mstp_eswm);
}
 
ra8_err_t ra8_eth_exit_stop(void)
{
  return ra8_mstp_enable(k_ra8_mstp_eswm);
}
 
/* -----------------------------------------------------------------------
 * Frame-level NIC API.
 * -------------------------------------------------------------------- */

RA8_INTERNAL
static void internal_capture_state(const ra8_eth_cfg_t* cfg)
{
  s_eth_state.opened       = 1U;
  s_eth_state.cfg          = *cfg;
  s_eth_state.stats.tx_ok  = 0U;
  s_eth_state.stats.rx_ok  = 0U;
  s_eth_state.stats.tx_err = 0U;
  s_eth_state.stats.rx_err = 0U;
}

RA8_INTERNAL
static void internal_populate_gwca_state(const ra8_eth_cfg_t* cfg)
{
  s_gwca_state.linkfix_table  = s_linkfix_table;
  s_gwca_state.linkfix_count  = (uint32_t)k_ra8_eth_linkfix_count;
  s_gwca_state.rx_chain       = s_rx_chain;
  s_gwca_state.rx_depth       = (uint32_t)k_ra8_eth_rx_ring_depth;
  s_gwca_state.rx_slot_bytes  = (uint32_t)k_ra8_eth_buf_size;
  s_gwca_state.rx_pool        = internal_eth_rx_pool();
  s_gwca_state.rx_queue_index = (uint32_t)k_ra8_eth_def_rx_q_idx;
  s_gwca_state.rx_head        = 0U;
  s_gwca_state.tx_chain       = s_tx_chain;
  s_gwca_state.tx_depth       = (uint32_t)k_ra8_eth_tx_ring_depth;
  s_gwca_state.tx_slot_bytes  = (uint32_t)k_ra8_eth_buf_size;
  s_gwca_state.tx_pool        = internal_eth_tx_pool();
  s_gwca_state.tx_queue_index = (uint32_t)k_ra8_eth_def_tx_q_idx;
  s_gwca_state.tx_tail        = 0U;
  s_gwca_state.mac_port       = cfg->channel;
}

RA8_INTERNAL
static ra8_err_t internal_open_prep(const ra8_eth_cfg_t* cfg)
{
  if (cfg->channel > 1U) {
    ra8_log_error(s_tag, "open: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  uint16_t        tx_count   = 0U;
  uint16_t        rx_count   = 0U;
  uint16_t        buf_size   = 0U;
  const ra8_err_t resolve_rc = internal_resolve_sizes(cfg, &tx_count, &rx_count, &buf_size);
  if (resolve_rc != k_ra8_ok) {
    return resolve_rc;
  }
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_eswm);
  if (mst_err != k_ra8_ok) {
    return mst_err;
  }
  return internal_bring_up_rmac(cfg);
}

volatile uint32_t g_ra8_eth_open_step;

RA8_INTERNAL
static ra8_err_t internal_open_gwca_path(void)
{
  /* Note: ``ra8_board_ethernet_init`` already runs its own COMA reset
   * (RR pulse + RCEC|ACE enable) via ``internal_eth_coma_reset`` --
   * the full FSP CABPIRM.BPIOG/BPR handshake is intentionally skipped
   * there because BPR never asserts on EK-RA8D2 silicon unless GWCA
   * is also being brought up, and the board can't depend on that. */
 
  /* Per FSP r_layer3_switch_open: program the per-port forwarding
   * destination masks BEFORE bringing the GWCA up. 0x7F = allow all
   * destinations (permissive baseline; tightens once L3 filtering
   * lands). */
  static const uint8_t local_fwpbfc_masks[3] = {k_eth_fwpbfc_mask,
                                                k_eth_fwpbfc_mask,
                                                k_eth_fwpbfc_mask};
  (void)ra8_eth_mfwd_set_forwarding_masks(local_fwpbfc_masks);
 
  const ra8_err_t err = ra8_eth_gwca_default_open(&s_gwca_state);
  if (err != k_ra8_ok) {
    g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_fail_3;
    return err;
  }
  g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_ok_3;
  const ra8_err_t mfwd_err =
    ra8_eth_mfwd_route_queue(s_gwca_state.mac_port, (uint8_t)s_gwca_state.rx_queue_index);
  if (mfwd_err != k_ra8_ok) {
    g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_fail_4;
    return mfwd_err;
  }
  g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_ok_4;
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_open(const ra8_eth_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "open: cfg must not be nullptr");
 
  g_ra8_eth_open_step     = 0U;
  const ra8_err_t prep_rc = internal_open_prep(cfg);
  if (prep_rc != k_ra8_ok) {
    g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_fail_1;
    return prep_rc;
  }
  g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_ok_1;
 
  internal_populate_gwca_state(cfg);
  g_ra8_eth_open_step = (uint32_t)k_ra8_eth_step_ok_2;
 
  const ra8_err_t bring_up_rc = internal_open_gwca_path();
  if (bring_up_rc != k_ra8_ok) {
    return bring_up_rc;
  }
 
  /* Force a fresh MPIC re-sync on the next ::ra8_eth_link_status call
   * so the on-chip RMAC's MPIC.LSC matches whatever speed the PHY
   * actually negotiated (HUM Ch 33.4.1.2 "MPIC : PHY Interfaces
   * Configuration Register" p 1707). */
  g_eth_mac_speed_resynced = false;
 
  internal_capture_state(cfg);
 
  /* Bench-confirmed (issue #1 follow-up): leaving MPIC.PIS at the
   * default GMII (1000mbit) configured by ra8_board_ethernet_init
   * silently drops every RX frame when the actual link auto-
   * negotiates to 100 Mbps. The PIS must match the *internal* xMII
   * timing (MII for 10/100, GMII for 1G). Force a resync at the end
   * of open so the MAC is ready for RX before the IP stack hits the
   * driver -- without it MRGFCE stays at zero until something else
   * calls ra8_eth_link_status, which NetX never does at boot. */
  ra8_eth_link_t link = {.link_up = 0U, .speed_mbps = 0U, .full_duplex = 0U, .bmsr = 0U};
  (void)ra8_eth_link_status(&link);
 
  ra8_log_info(s_tag, "eth_open: gwca rings ready");
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_close(void)
{
  if (s_eth_state.opened == 0U) {
    return k_ra8_err_not_initialized;
  }
 
  /* Park the GWCA state machine in DISABLE. Best-effort -- ignore
   * the err so teardown always reaches the MSTP-gate balance below.
   * HUM Ch 34.3.1 "GWMC : Mode Configuration Register" p 1797 */
  (void)ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
 
  /* Tear down the local RMAC port (MSTP-gate ref-counted). */
  const ra8_rmac_port_t rmac_port = priv_ra8_eth_channel_to_port(s_eth_state.cfg.channel);
  (void)ra8_rmac_deinit(rmac_port);
 
  /* Balance the second ESWM-MSTP enable that ::ra8_eth_gwca_default_open
   * acquired via ::ra8_eth_gwca_init. The first enable, owned by
   * ::internal_open_prep, is balanced by the final ra8_mstp_disable
   * call below. */
  (void)ra8_eth_gwca_deinit();
 
  s_eth_state.opened       = 0U;
  g_eth_mac_speed_resynced = false;
  return ra8_mstp_disable(k_ra8_mstp_eswm);
}
 
ra8_err_t ra8_eth_write(const uint8_t* buf, uint32_t len)
{
  RA8_CHECK_NULL_PTR(buf, s_tag, "write: buf must not be nullptr");
  if (s_eth_state.opened == 0U) {
    return k_ra8_err_not_initialized;
  }
  if ((len < k_ra8_eth_min_frame) || (len > k_ra8_eth_max_frame)) {
    ra8_log_error(s_tag, "write: frame length out of range");
    return k_ra8_err_invalid_arg;
  }
 
  const ra8_err_t err = ra8_eth_gwca_default_send(&s_gwca_state, buf, len);
  if (err == k_ra8_ok) {
    internal_stat_inc(&s_eth_state.stats.tx_ok);
    return k_ra8_ok;
  }
  internal_stat_inc(&s_eth_state.stats.tx_err);
  return err;
}
 
ra8_err_t ra8_eth_read(uint8_t* buf, uint32_t max_len, uint32_t* got_len)
{
  RA8_CHECK_NULL_PTR(buf, s_tag, "read: buf must not be nullptr");
  RA8_CHECK_NULL_PTR(got_len, s_tag, "read: got_len must not be nullptr");
  if (s_eth_state.opened == 0U) {
    return k_ra8_err_not_initialized;
  }
  if (max_len == 0U) {
    return k_ra8_err_invalid_arg;
  }
 
  const ra8_err_t err = ra8_eth_gwca_default_recv(&s_gwca_state, buf, max_len, got_len);
  if (err == k_ra8_ok) {
    internal_stat_inc(&s_eth_state.stats.rx_ok);
    return k_ra8_ok;
  }
  internal_stat_inc(&s_eth_state.stats.rx_err);
  if (err == k_ra8_err_no_data) {
    *got_len = 0U;
    return k_ra8_err_no_data;
  }
  return err;
}
 
ra8_err_t ra8_eth_get_stats(ra8_eth_stats_t* out_stats)
{
  RA8_CHECK_NULL_PTR(out_stats, s_tag, "get_stats: out must not be nullptr");
  if (s_eth_state.opened == 0U) {
    return k_ra8_err_not_initialized;
  }
  *out_stats = s_eth_state.stats;
  return k_ra8_ok;
}
 
#ifdef UNIT_TEST
typedef enum : uint32_t {
  k_ra8_eth_test_ds_low_mask   = 0xFFU, 
  k_ra8_eth_test_ds_high_shift = 8U,    
  k_ra8_eth_test_ds_high_mask  = 0x0FU, 
} ra8_eth_test_ds_bits_t;

RA8_INTERNAL
static uint32_t internal_test_rx_slot(void)
{
  const uint32_t data_slots = s_gwca_state.rx_depth - 1U;
  return s_gwca_state.rx_head % data_slots;
}

ra8_err_t ra8_eth_test_inject_rx(const uint8_t* payload, uint32_t len)
{
  RA8_CHECK_NULL_PTR(payload, s_tag, "test_inject_rx: payload nullptr");
  if (s_eth_state.opened == 0U) {
    return k_ra8_err_not_initialized;
  }
  const uint32_t               slot     = internal_test_rx_slot();
  ra8_gwca_basic_descriptor_t* desc     = &s_rx_chain[slot];
  uint32_t                     copy_len = len;
  if (copy_len > (uint32_t)k_ra8_eth_buf_size) {
    copy_len = (uint32_t)k_ra8_eth_buf_size;
  }
  /* The descriptor's PTR was set by ::ra8_eth_gwca_attach_buffers
   * during open. ::internal_eth_rx_pool returns the same low-address
   * (or BSS-on-chip) base; copy the payload to the matching slice so
   * default_recv pops the same bytes. */
  uint8_t* const pool_slot =
    internal_eth_rx_pool() + ((uintptr_t)slot * (uintptr_t)k_ra8_eth_buf_size);
  internal_byte_copy(pool_slot, payload, copy_len);
  desc->ds_l = (uint8_t)(copy_len & (uint32_t)k_ra8_eth_test_ds_low_mask);
  desc->ds_h = (uint8_t)((copy_len >> (uint32_t)k_ra8_eth_test_ds_high_shift) &
                         (uint32_t)k_ra8_eth_test_ds_high_mask);
  desc->dt   = (uint8_t)k_ra8_gwdcc_dt_fsingle;
  return k_ra8_ok;
}
#endif /* UNIT_TEST */