ra8_etha.c

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#include "ra8_etha.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_etha_internal.h"
#include "ra8_etha_regs.h"
#include "ra8_ether_regs.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"

static const char* s_tag = "ETHA";

volatile uint32_t g_ra8_etha_diag_last_eams[2] = {0U, 0U};

typedef enum : uint32_t {
  k_etha_vem_mask = 0x7U, 
} etha_field_t;

typedef enum : uint32_t {
  k_ra8_etha_local_all_bits_set = 0xFFFFFFFFUL, 
  k_ra8_etha_local_byte_mask    = 0xFFU,        
  k_ra8_etha_local_9bit_mask    = 0x1FFUL,      
} ra8_etha_local_mask_t;

ra8_etha_slot_t s_etha_slots[k_ra8_etha_port_count];

RA8_INTERNAL
static inline bool internal_tc_ok(ra8_etha_tc_t tc)
{
  return (uint8_t)tc < k_ra8_etha_tc_count;
}

RA8_INTERNAL
static inline bool internal_irq_block_ok(ra8_etha_irq_class_t block)
{
  return (uint8_t)block < k_ra8_etha_irq_class_count;
}
 
ra8_err_t ra8_etha_init(ra8_etha_port_t port, const ra8_etha_config_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "etha_init: cfg must not be nullptr");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_init: port out of range");
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C" p 446 */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_eswm);
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "etha_init: mstp enable");
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
 
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  reg->EAMC = (uint32_t)cfg->initial_mode & k_ra8_etha_mask_opc;
  /* HUM Ch 32.3.7.1.3 "EAEID0 : Error Interrupt Disable Register 0" p 1662 */
  reg->EAEID0 = k_ra8_etha_local_all_bits_set;
  /* HUM Ch 32.3.7.1.6 "EAEID1 : Error Interrupt Disable Register 1" p 1665 */
  reg->EAEID1 = k_ra8_etha_local_all_bits_set;
  /* HUM Ch 32.3.7.1.9 "EAEID2 : Error Interrupt Disable Register 2" p 1668 */
  reg->EAEID2 = k_ra8_etha_local_all_bits_set;
  /* HUM Ch 32.3.7.1.2 "EAEIE0 : Error Interrupt Enable Register 0" p 1661 */
  reg->EAEIE0 = cfg->eaeie0_mask;
  /* HUM Ch 32.3.7.1.5 "EAEIE1 : Error Interrupt Enable Register 1" p 1664 */
  reg->EAEIE1 = cfg->eaeie1_mask;
  /* HUM Ch 32.3.7.1.8 "EAEIE2 : Error Interrupt Enable Register 2" p 1667 */
  reg->EAEIE2 = cfg->eaeie2_mask;
 
  s_etha_slots[(uint8_t)port].cb    = nullptr;
  s_etha_slots[(uint8_t)port].ctx   = nullptr;
  s_etha_slots[(uint8_t)port].stats = (ra8_etha_port_stats_t){};
  ra8_log_info(s_tag, "etha_init");
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_deinit(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_deinit: port out of range");
    return k_ra8_err_invalid_arg;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  reg->EAMC = (uint32_t)k_ra8_etha_opc_reset;
  /* HUM Ch 32.3.7.1.2 "EAEIE0 : Error Interrupt Enable Register 0" p 1661 */
  reg->EAEIE0 = 0U;
  /* HUM Ch 32.3.7.1.5 "EAEIE1 : Error Interrupt Enable Register 1" p 1664 */
  reg->EAEIE1 = 0U;
  /* HUM Ch 32.3.7.1.8 "EAEIE2 : Error Interrupt Enable Register 2" p 1667 */
  reg->EAEIE2 = 0U;
 
  s_etha_slots[(uint8_t)port].cb    = nullptr;
  s_etha_slots[(uint8_t)port].ctx   = nullptr;
  s_etha_slots[(uint8_t)port].stats = (ra8_etha_port_stats_t){};
  /* MSTP gate is shared with the rest of the Ethernet subsystem; do
   * NOT drop it here. ra8_eth_deinit owns the final reference. */
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_get_status(ra8_etha_port_t port, ra8_etha_status_t* out)
{
  RA8_CHECK_NULL_PTR(out, s_tag, "etha_get_status: out must not be nullptr");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_get_status: port out of range");
    return k_ra8_err_invalid_arg;
  }
 
  volatile const r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.1.2 "EAMS : Mode Status Register" p 1631 */
  const uint32_t ops = reg->EAMS & k_ra8_etha_mask_ops;
  /* HUM Ch 32.3.7.1.1 "EAEIS0 : Error Interrupt Status Register 0" p 1659 */
  const uint32_t eaeis0 = reg->EAEIS0;
  /* HUM Ch 32.3.7.1.4 "EAEIS1 : Error Interrupt Status Register 1" p 1662 */
  const uint32_t eaeis1 = reg->EAEIS1;
  /* HUM Ch 32.3.7.1.7 "EAEIS2 : Error Interrupt Status Register 2" p 1665 */
  const uint32_t eaeis2 = reg->EAEIS2;
  /* HUM Ch 32.3.5.12 "EATASCTM : TAS Cycle Time Monitoring Register" p 1651 */
  const uint32_t tasctm = reg->EATASCTM;
  out->ops              = (ra8_etha_ops_t)(uint8_t)ops;
  out->eaeis0           = eaeis0;
  out->eaeis1           = eaeis1;
  out->eaeis2           = eaeis2;
  out->tas_cycle        = tasctm;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_clear_status(ra8_etha_port_t port, ra8_etha_irq_class_t block, uint32_t mask)
{
  if (!internal_port_ok(port) || !internal_irq_block_ok(block)) {
    ra8_log_error(s_tag, "etha_clear_status: port/block out of range");
    return k_ra8_err_invalid_arg;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  switch (block) {
    case k_ra8_etha_irq_class_0:
      /* HUM Ch 32.3.7.1.3 "EAEID0 : Error Interrupt Disable Register 0" p 1662 */
      reg->EAEID0 = mask;
      /* HUM Ch 32.3.7.1.1 "EAEIS0 : Error Interrupt Status Register 0" p 1659 */
      reg->EAEIS0 = reg->EAEIS0 & ~mask;
      break;
    case k_ra8_etha_irq_class_1:
      /* HUM Ch 32.3.7.1.6 "EAEID1 : Error Interrupt Disable Register 1" p 1665 */
      reg->EAEID1 = mask;
      /* HUM Ch 32.3.7.1.4 "EAEIS1 : Error Interrupt Status Register 1" p 1662 */
      reg->EAEIS1 = reg->EAEIS1 & ~mask;
      break;
    case k_ra8_etha_irq_class_2:
      /* HUM Ch 32.3.7.1.9 "EAEID2 : Error Interrupt Disable Register 2" p 1668 */
      reg->EAEID2 = mask;
      /* HUM Ch 32.3.7.1.7 "EAEIS2 : Error Interrupt Status Register 2" p 1665 */
      reg->EAEIS2 = reg->EAEIS2 & ~mask;
      break;
    case k_ra8_etha_irq_class_count:
    default:
      return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_enable_irq(ra8_etha_port_t port, ra8_etha_irq_class_t block, uint32_t mask)
{
  if (!internal_port_ok(port) || !internal_irq_block_ok(block)) {
    ra8_log_error(s_tag, "etha_enable_irq: bad arg");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  switch (block) {
    case k_ra8_etha_irq_class_0:
      /* HUM Ch 32.3.7.1.2 "EAEIE0 : Error Interrupt Enable Register 0" p 1661 */
      reg->EAEIE0 = reg->EAEIE0 | mask;
      break;
    case k_ra8_etha_irq_class_1:
      /* HUM Ch 32.3.7.1.5 "EAEIE1 : Error Interrupt Enable Register 1" p 1664 */
      reg->EAEIE1 = reg->EAEIE1 | mask;
      break;
    case k_ra8_etha_irq_class_2:
      /* HUM Ch 32.3.7.1.8 "EAEIE2 : Error Interrupt Enable Register 2" p 1667 */
      reg->EAEIE2 = reg->EAEIE2 | mask;
      break;
    case k_ra8_etha_irq_class_count:
    default:
      return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_disable_irq(ra8_etha_port_t port, ra8_etha_irq_class_t block, uint32_t mask)
{
  if (!internal_port_ok(port) || !internal_irq_block_ok(block)) {
    ra8_log_error(s_tag, "etha_disable_irq: bad arg");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  switch (block) {
    case k_ra8_etha_irq_class_0:
      /* HUM Ch 32.3.7.1.2 "EAEIE0 : Error Interrupt Enable Register 0" p 1661 */
      reg->EAEIE0 = reg->EAEIE0 & ~mask;
      break;
    case k_ra8_etha_irq_class_1:
      /* HUM Ch 32.3.7.1.5 "EAEIE1 : Error Interrupt Enable Register 1" p 1664 */
      reg->EAEIE1 = reg->EAEIE1 & ~mask;
      break;
    case k_ra8_etha_irq_class_2:
      /* HUM Ch 32.3.7.1.8 "EAEIE2 : Error Interrupt Enable Register 2" p 1667 */
      reg->EAEIE2 = reg->EAEIE2 & ~mask;
      break;
    case k_ra8_etha_irq_class_count:
    default:
      return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_attach_handler(ra8_etha_port_t port, ra8_etha_event_fn_t cb, void* ctx)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_attach_handler: port out of range");
    return k_ra8_err_invalid_arg;
  }
  s_etha_slots[(uint8_t)port].cb  = cb;
  s_etha_slots[(uint8_t)port].ctx = ctx;
  return k_ra8_ok;
}
 
RA8_ISR_SAFE
void ra8_etha_dispatch(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    return;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.7.1.1 "EAEIS0 : Error Interrupt Status Register 0" p 1659 */
  const uint32_t s0 = reg->EAEIS0;
  /* HUM Ch 32.3.7.1.4 "EAEIS1 : Error Interrupt Status Register 1" p 1662 */
  const uint32_t s1 = reg->EAEIS1;
  /* HUM Ch 32.3.7.1.7 "EAEIS2 : Error Interrupt Status Register 2" p 1665 */
  const uint32_t s2 = reg->EAEIS2;
 
  const ra8_etha_event_fn_t fn  = s_etha_slots[(uint8_t)port].cb;
  void* const               ctx = s_etha_slots[(uint8_t)port].ctx;
 
  /* HUM Ch 32.3.7.1.3 "EAEID0 : Error Interrupt Disable Register 0" p 1662 */
  reg->EAEID0 = s0;
  /* HUM Ch 32.3.7.1.6 "EAEID1 : Error Interrupt Disable Register 1" p 1665 */
  reg->EAEID1 = s1;
  /* HUM Ch 32.3.7.1.9 "EAEID2 : Error Interrupt Disable Register 2" p 1668 */
  reg->EAEID2 = s2;
  /* HUM Ch 32.3.7.1.1 "EAEIS0 : Error Interrupt Status Register 0" p 1659 */
  reg->EAEIS0 = 0U;
  /* HUM Ch 32.3.7.1.4 "EAEIS1 : Error Interrupt Status Register 1" p 1662 */
  reg->EAEIS1 = 0U;
  /* HUM Ch 32.3.7.1.7 "EAEIS2 : Error Interrupt Status Register 2" p 1665 */
  reg->EAEIS2 = 0U;
 
  if (fn != nullptr) {
    fn(ctx, port, s0, s1, s2);
  }
}
 
ra8_err_t ra8_etha_enter_stop(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_enter_stop: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  ra8_etha(port)->EAMC = (uint32_t)k_ra8_etha_opc_disable;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_exit_stop(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_exit_stop: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  ra8_etha(port)->EAMC = (uint32_t)k_ra8_etha_opc_operation;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_reset(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_reset: port out of range");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  reg->EAMC = (uint32_t)k_ra8_etha_opc_reset;
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  reg->EAMC = (uint32_t)k_ra8_etha_opc_config;
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t
internal_etha_wait_for_mode(ra8_etha_port_t port, volatile r_etha_regs_t* reg, ra8_etha_opc_t mode)
{
  /* Only CONFIG and DISABLE are load-bearing: writes to MRMAC require
   * the port to actually be in CONFIG, and the OPERATION -> DISABLE
   * step has to land before the next CONFIG attempt. RESET and
   * OPERATION transitions are fire-and-forget on this silicon -- the
   * bench's eth_loopback test exercises OPERATION on the unwired
   * ETHA0 port where EAMS never advances past CONFIG (no PHY, no
   * media); polling there hangs the test. */
  if (mode != k_ra8_etha_opc_config) {
    if (mode != k_ra8_etha_opc_disable) {
      return k_ra8_ok;
    }
  }
  enum : uint32_t {
    k_ms_budget = 500U,    
    k_inner     = 200000U, 
  };
  const uint32_t target = (uint32_t)mode & k_ra8_etha_mask_ops;
  for (uint32_t ms = 0U; ms < (uint32_t)k_ms_budget; ++ms) {
    for (uint32_t i = 0U; i < (uint32_t)k_inner; ++i) {
      const uint32_t eams                            = reg->EAMS & k_ra8_etha_mask_ops;
      g_ra8_etha_diag_last_eams[(uint32_t)port & 1U] = eams;
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
      if (ra8_fake_mmio_wait_eval(&reg->EAMS, i, (eams == target))) {
        return k_ra8_ok;
      }
#else
      if (eams == target) {
        return k_ra8_ok;
      }
#endif
    }
  }
  ra8_log_error(s_tag, "etha_set_mode: EAMS.OPS never reached requested mode");
  return k_ra8_err_hw_timeout;
}
 
ra8_err_t ra8_etha_set_mode(ra8_etha_port_t port, ra8_etha_opc_t mode)
{
  if (!internal_port_ok(port) || (uint32_t)mode > k_ra8_etha_mask_opc) {
    ra8_log_error(s_tag, "etha_set_mode: bad arg");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630 */
  reg->EAMC = (uint32_t)mode & k_ra8_etha_mask_opc;
  return internal_etha_wait_for_mode(port, reg, mode);
}
 
ra8_err_t ra8_etha_set_queue_arb(ra8_etha_port_t port, ra8_etha_tc_t tc, uint8_t arb)
{
  if (!internal_port_ok(port) || !internal_tc_ok(tc) || (uint32_t)arb > k_ra8_etha_mask_tdqa) {
    ra8_log_error(s_tag, "etha_set_queue_arb: bad arg");
    return k_ra8_err_invalid_arg;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.2.4 "EATDQAC : TX Descriptor Queue Arbitration Configuration Register" p 1634 */
  const uint32_t shift = (uint32_t)((uint8_t)tc * 4U);
  /* HUM Ch 32.3.2.4 "EATDQAC : TX Descriptor Queue Arbitration Configuration Register" p 1634 */
  const uint32_t mask = k_ra8_etha_mask_tdqa << shift;
  /* HUM Ch 32.3.2.4 "EATDQAC : TX Descriptor Queue Arbitration Configuration Register" p 1634 */
  reg->EATDQAC = (reg->EATDQAC & ~mask) | (((uint32_t)arb & k_ra8_etha_mask_tdqa) << shift);
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_queue_depth(ra8_etha_port_t port, ra8_etha_tc_t tc, uint16_t depth)
{
  if (!internal_port_ok(port) || !internal_tc_ok(tc) || (uint32_t)depth > k_ra8_etha_mask_dqd) {
    ra8_log_error(s_tag, "etha_set_queue_depth: bad arg");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.2.7 "EATDQDCq" p 1636 */
  ra8_etha(port)->EATDQDC[(uint8_t)tc] = (uint32_t)depth & k_ra8_etha_mask_dqd;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_get_queue_level(ra8_etha_port_t port,
                                   ra8_etha_tc_t   tc,
                                   uint16_t*       cur_level,
                                   uint16_t*       peak)
{
  RA8_CHECK_NULL_PTR(cur_level, s_tag, "etha_get_queue_level: cur_level null");
  RA8_CHECK_NULL_PTR(peak, s_tag, "etha_get_queue_level: peak null");
  if (!internal_port_ok(port) || !internal_tc_ok(tc)) {
    ra8_log_error(s_tag, "etha_get_queue_level: bad arg");
    return k_ra8_err_invalid_arg;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.2.8 "EATDQMq : Transmission Descriptor Queue q Monitoring (q = 0 to 7)" p 1636 */
  *cur_level = (uint16_t)(reg->EATDQM[(uint8_t)tc] & k_ra8_etha_mask_dnq);
  /* HUM Ch 32.3.2.9 "EATDQMLMq : Transmission Descriptor Queue q Max Level Monitoring" p 1637 */
  *peak = (uint16_t)(reg->EATDQMLM[(uint8_t)tc] & k_ra8_etha_mask_dnq);
  return k_ra8_ok;
}
 
ra8_err_t
ra8_etha_set_preemption(ra8_etha_port_t port, uint8_t preempt, uint8_t cut_thru, ra8_etha_afs_t afs)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_preemption: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.2.5 "EATPEC : TX Preemption Configuration Register" p 1635 */
  uint32_t v = (uint32_t)preempt & k_ra8_etha_local_byte_mask;
  if (cut_thru != 0U) {
    v |= (1U << 8); /* TTQ8 cut-through preemptable */
  }
  v |= ((uint32_t)afs & 0x3U) << (uint32_t)k_ra8_etha_eatpec_afs_pos;
  /* HUM Ch 32.3.2.5 "EATPEC : TX Preemption Configuration Register" p 1635 */
  ra8_etha(port)->EATPEC = v;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_max_frame_size(ra8_etha_port_t port, ra8_etha_tc_t tc, uint16_t max_bytes)
{
  if (!internal_port_ok(port) || !internal_tc_ok(tc)) {
    ra8_log_error(s_tag, "etha_set_max_frame_size: bad arg");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.2.6 "EATMFSCq" p 1635 */
  ra8_etha(port)->EATMFSC[(uint8_t)tc] = (uint32_t)max_bytes & k_ra8_etha_mask_mfs;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_ipv_remap(ra8_etha_port_t port, const uint8_t* map)
{
  RA8_CHECK_NULL_PTR(map, s_tag, "etha_set_ipv_remap: map null");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_ipv_remap: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* Validate every entry first so we never write a partial value. */
  for (uint8_t i = 0U; i < k_ra8_etha_tc_count; ++i) {
    if ((uint32_t)map[i] > k_ra8_etha_mask_ipv) {
      ra8_log_error(s_tag, "etha_set_ipv_remap: entry > 7");
      return k_ra8_err_invalid_arg;
    }
  }
  /* HUM Ch 32.3.2.1 "EAIRC : IPV Remapping Configuration Register [802.1Q]" p 1631 */
  uint32_t packed = 0U;
  for (uint8_t i = 0U; i < k_ra8_etha_tc_count; ++i) {
    /* HUM Ch 32.3.2.1 "EAIRC : IPV Remapping Configuration Register [802.1Q]" p 1631 */
    const uint32_t shift = (uint32_t)i * 4U;
    packed |= ((uint32_t)map[i] & k_ra8_etha_mask_ipv) << shift;
  }
  /* HUM Ch 32.3.2.1 "EAIRC : IPV Remapping Configuration Register [802.1Q]" p 1631 */
  ra8_etha(port)->EAIRC = packed;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_vlan_mode(ra8_etha_port_t port, ra8_etha_vim_t vim, ra8_etha_vem_t vem)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_vlan_mode: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.3.1 "EAVCC : VLAN Control Configuration Register" p 1639 */
  const uint32_t v = ((uint32_t)vim & 0x1U) |
                     (((uint32_t)vem & k_etha_vem_mask) << (uint32_t)k_ra8_etha_eavcc_vem_pos);
  /* HUM Ch 32.3.3.1 "EAVCC : VLAN Control Configuration Register" p 1639 */
  ra8_etha(port)->EAVCC = v;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_vlan_tag(ra8_etha_port_t            port,
                                const ra8_etha_vlan_tag_t* c_tag,
                                const ra8_etha_vlan_tag_t* s_tag_in)
{
  RA8_CHECK_NULL_PTR(c_tag, s_tag, "etha_set_vlan_tag: c_tag null");
  RA8_CHECK_NULL_PTR(s_tag_in, s_tag, "etha_set_vlan_tag: s_tag null");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_vlan_tag: port out of range");
    return k_ra8_err_invalid_arg;
  }
  if ((uint32_t)c_tag->vid > k_ra8_etha_mask_vlan_vid ||
      (uint32_t)s_tag_in->vid > k_ra8_etha_mask_vlan_vid ||
      (uint32_t)c_tag->pcp > k_ra8_etha_mask_vlan_pcp ||
      (uint32_t)s_tag_in->pcp > k_ra8_etha_mask_vlan_pcp ||
      (uint32_t)c_tag->dei > k_ra8_etha_mask_vlan_dei ||
      (uint32_t)s_tag_in->dei > k_ra8_etha_mask_vlan_dei) {
    ra8_log_error(s_tag, "etha_set_vlan_tag: tag fields out of range");
    return k_ra8_err_invalid_arg;
  }
 
  const uint32_t v =
    (((uint32_t)c_tag->vid & k_ra8_etha_mask_vlan_vid) << (uint32_t)k_ra8_etha_eavtc_ctv_pos) |
    (((uint32_t)c_tag->pcp & k_ra8_etha_mask_vlan_pcp) << (uint32_t)k_ra8_etha_eavtc_ctp_pos) |
    (((uint32_t)c_tag->dei & k_ra8_etha_mask_vlan_dei) << (uint32_t)k_ra8_etha_eavtc_ctd_pos) |
    (((uint32_t)s_tag_in->vid & k_ra8_etha_mask_vlan_vid) << (uint32_t)k_ra8_etha_eavtc_stv_pos) |
    (((uint32_t)s_tag_in->pcp & k_ra8_etha_mask_vlan_pcp) << (uint32_t)k_ra8_etha_eavtc_stp_pos) |
    (((uint32_t)s_tag_in->dei & k_ra8_etha_mask_vlan_dei) << (uint32_t)k_ra8_etha_eavtc_std_pos);
  /* HUM Ch 32.3.3.2 "EAVTC : VLAN TAG Configuration Register" p 1640 */
  ra8_etha(port)->EAVTC = v;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_set_rx_tag_filter(ra8_etha_port_t port, uint32_t mask)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_rx_tag_filter: port out of range");
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 32.3.3.3 "EARTFC : Reception TAG Filtering Configuration Register" p 1641 */
  ra8_etha(port)->EARTFC = mask & k_ra8_etha_local_9bit_mask;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_configure_cut_through(ra8_etha_port_t port, uint16_t qd, uint8_t dqd)
{
  if (!internal_port_ok(port) || (uint32_t)dqd > k_ra8_etha_mask_ctdqd) {
    ra8_log_error(s_tag, "etha_configure_cut_through: bad arg");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.2.10 "EACTQC : Cut-Through Queue Configuration Register" p 1637 */
  reg->EACTQC = (uint32_t)qd & k_ra8_etha_mask_ctqd;
  /* HUM Ch 32.3.2.11 "EACTDQDC : Cut-Through Descriptor Queue Depth Configuration" p 1638 */
  reg->EACTDQDC = (uint32_t)dqd & k_ra8_etha_mask_ctdqd;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_configure_cbs(ra8_etha_port_t             port,
                                 ra8_etha_tc_t               tc,
                                 uint8_t                     enable,
                                 const ra8_etha_cbs_param_t* param)
{
  if (!internal_port_ok(port) || !internal_tc_ok(tc)) {
    ra8_log_error(s_tag, "etha_configure_cbs: bad arg");
    return k_ra8_err_invalid_arg;
  }
  if (enable != 0U) {
    RA8_CHECK_NULL_PTR(param, s_tag, "etha_configure_cbs: param null");
    if (param->increment > k_ra8_etha_mask_civ || param->upper_lim > k_ra8_etha_mask_cul) {
      ra8_log_error(s_tag, "etha_configure_cbs: param range");
      return k_ra8_err_invalid_arg;
    }
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  if (enable != 0U) {
    /* HUM Ch 32.3.4.3 "EACAIVCq : CBS Admin Increment Value Configuration q (q = 0 to 7)" p 1643 */
    reg->EACAIVC[(uint8_t)tc] = param->increment & k_ra8_etha_mask_civ;
    /* HUM Ch 32.3.4.4 "EACAULCq : CBS Admin Upper Limit Configuration q (q = 0 to 7)" p 1643 */
    reg->EACAULC[(uint8_t)tc] = param->upper_lim & k_ra8_etha_mask_cul;
  }
  /* HUM Ch 32.3.4.1 "EACAEC : CBS Admin Enable Configuration Register" p 1642 */
  const uint32_t bit = 1U << (uint8_t)tc;
  if (enable != 0U) {
    reg->EACAEC = reg->EACAEC | bit;
    /* HUM Ch 32.3.4.2 "EACC : CBS Configuration Register" p 1642 */
    reg->EACC = reg->EACC | bit;
  } else {
    reg->EACAEC = reg->EACAEC & ~bit;
    /* HUM Ch 32.3.4.2 "EACC : CBS Configuration Register" p 1642 */
    reg->EACC = reg->EACC & ~bit;
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_get_cbs_state(ra8_etha_port_t       port,
                                 ra8_etha_tc_t         tc,
                                 uint8_t*              enabled,
                                 uint8_t*              gate_open,
                                 ra8_etha_cbs_param_t* oper_param)
{
  RA8_CHECK_NULL_PTR(enabled, s_tag, "etha_get_cbs_state: enabled null");
  RA8_CHECK_NULL_PTR(gate_open, s_tag, "etha_get_cbs_state: gate_open null");
  RA8_CHECK_NULL_PTR(oper_param, s_tag, "etha_get_cbs_state: oper_param null");
  if (!internal_port_ok(port) || !internal_tc_ok(tc)) {
    ra8_log_error(s_tag, "etha_get_cbs_state: bad arg");
    return k_ra8_err_invalid_arg;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  const uint32_t          bit = 1U << (uint8_t)tc;
  /* HUM Ch 32.3.4.5 "EACOEM : CBS Oper Enable Monitoring Register" p 1644 */
  *enabled = (uint8_t)((reg->EACOEM & bit) != 0U ? 1U : 0U);
  /* HUM Ch 32.3.4.8 "EACGSM : CBS Gate State Monitoring Register" p 1645 */
  *gate_open = (uint8_t)((reg->EACGSM & bit) != 0U ? 1U : 0U);
  /* HUM Ch 32.3.4.6 "EACOIVMq : CBS Oper Increment Value Monitoring q (q = 0 to 7)" p 1644 */
  oper_param->increment = reg->EACOIVM[(uint8_t)tc] & k_ra8_etha_mask_civ;
  /* HUM Ch 32.3.4.7 "EACOULMq : CBS Oper Upper Limit Monitoring Register q (q = 0 to 7)" p 1645 */
  oper_param->upper_lim = reg->EACOULM[(uint8_t)tc] & k_ra8_etha_mask_cul;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_read_stats(ra8_etha_port_t port, ra8_etha_stats_t* out)
{
  RA8_CHECK_NULL_PTR(out, s_tag, "etha_read_stats: out null");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_read_stats: port out of range");
    return k_ra8_err_invalid_arg;
  }
 
  volatile const r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.6.1 "EAUSMFSECN : Under Minimum Frame Size Error Counter Register" p 1656 */
  out->switch_min_frame_err = (uint16_t)(reg->EAUSMFSECN & k_ra8_etha_mask_mfs);
  /* HUM Ch 32.3.6.2 "EATFECN : TAG Filtering Error Counter Register" p 1657 */
  out->tag_filter_err = (uint16_t)(reg->EATFECN & k_ra8_etha_mask_mfs);
  /* HUM Ch 32.3.6.3 "EAFSECN : Frame Size Error Counter Register" p 1658 */
  out->frame_size_err = (uint16_t)(reg->EAFSECN & k_ra8_etha_mask_mfs);
  /* HUM Ch 32.3.6.4 "EADQOECN : Descriptor Queue Overflow Error Counter Register" p 1658 */
  out->queue_overflow_err = (uint16_t)(reg->EADQOECN & k_ra8_etha_mask_mfs);
  /* HUM Ch 32.3.6.5 "EADQSECN : Descriptor Queue Security Error Counter Register" p 1659 */
  out->queue_security_err = (uint16_t)(reg->EADQSECN & k_ra8_etha_mask_mfs);
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_clear_stats(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_clear_stats: port out of range");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.6.1 "EAUSMFSECN : Under Minimum Frame Size Error Counter Register" p 1656 */
  reg->EAUSMFSECN = 0U;
  /* HUM Ch 32.3.6.2 "EATFECN : TAG Filtering Error Counter Register" p 1657 */
  reg->EATFECN = 0U;
  /* HUM Ch 32.3.6.3 "EAFSECN : Frame Size Error Counter Register" p 1658 */
  reg->EAFSECN = 0U;
  /* HUM Ch 32.3.6.4 "EADQOECN : Descriptor Queue Overflow Error Counter Register" p 1658 */
  reg->EADQOECN = 0U;
  /* HUM Ch 32.3.6.5 "EADQSECN : Descriptor Queue Security Error Counter Register" p 1659 */
  reg->EADQSECN = 0U;
  return k_ra8_ok;
}