ra8_etha_regs.h File Reference

Ethernet Agent (ETHA) per-port register layout for the RA8D2. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_ether_regs.h"

Include dependency graph for ra8_etha_regs.h:

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Go to the source code of this file.

Data Structures
struct	r_etha_regs_t
	Full ETHA per-port register window (HUM Ch 32, FSP R_ETHA0_Type). More...

Enumerations
enum	ra8_etha_port_t : uint8_t {   k_ra8_etha_port_0 = 0U ,   k_ra8_etha_port_1 = 1U ,   k_ra8_etha_port_count = 2U }
	ETHA port index (m = 0, 1). More...
enum	ra8_etha_tc_t : uint8_t {   k_ra8_etha_tc_0 = 0U ,   k_ra8_etha_tc_1 = 1U ,   k_ra8_etha_tc_2 = 2U ,   k_ra8_etha_tc_3 = 3U ,   k_ra8_etha_tc_4 = 4U ,   k_ra8_etha_tc_5 = 5U ,   k_ra8_etha_tc_6 = 6U ,   k_ra8_etha_tc_7 = 7U ,   k_ra8_etha_tc_count = 8U }
	Traffic-class index (q = 0..7) used by every per-class array. More...
enum	ra8_etha_offset_t : uint16_t {   k_ra8_etha_off_eamc = 0x0000U ,   k_ra8_etha_off_eams = 0x0004U ,   k_ra8_etha_off_eairc = 0x0010U ,   k_ra8_etha_off_eatdqsc = 0x0014U ,   k_ra8_etha_off_eatdqc = 0x0018U ,   k_ra8_etha_off_eatdqac = 0x001CU ,   k_ra8_etha_off_eatpec = 0x0020U ,   k_ra8_etha_off_eatmfsc0 = 0x0040U ,   k_ra8_etha_off_eatdqdc0 = 0x0060U ,   k_ra8_etha_off_eatdqm0 = 0x0080U ,   k_ra8_etha_off_eatdqmlm0 = 0x00A0U ,   k_ra8_etha_off_eactqc = 0x0100U ,   k_ra8_etha_off_eactdqdc = 0x0104U ,   k_ra8_etha_off_eactdqm = 0x0108U ,   k_ra8_etha_off_eactdqmlm = 0x010CU ,   k_ra8_etha_off_eavcc = 0x0130U ,   k_ra8_etha_off_eavtc = 0x0134U ,   k_ra8_etha_off_eartfc = 0x0138U ,   k_ra8_etha_off_eacaec = 0x0200U ,   k_ra8_etha_off_eacc = 0x0204U ,   k_ra8_etha_off_eacaivc0 = 0x0220U ,   k_ra8_etha_off_eacaulc0 = 0x0240U ,   k_ra8_etha_off_eacoem = 0x0260U ,   k_ra8_etha_off_eacoivm0 = 0x0280U ,   k_ra8_etha_off_eacoulm0 = 0x02A0U ,   k_ra8_etha_off_eacgsm = 0x02C0U ,   k_ra8_etha_off_eatasc = 0x0300U ,   k_ra8_etha_off_eatasigsc = 0x0304U ,   k_ra8_etha_off_eatasenc0 = 0x0320U ,   k_ra8_etha_off_eatasctenc = 0x0340U ,   k_ra8_etha_off_eatasenm0 = 0x0360U ,   k_ra8_etha_off_eatasctenm = 0x0380U ,   k_ra8_etha_off_eatascstc0 = 0x03A0U ,   k_ra8_etha_off_eatascstc1 = 0x03A4U ,   k_ra8_etha_off_eatascstm0 = 0x03A8U ,   k_ra8_etha_off_eatascstm1 = 0x03ACU ,   k_ra8_etha_off_eatasctc = 0x03B0U ,   k_ra8_etha_off_eatasctm = 0x03B4U ,   k_ra8_etha_off_eatasgl0 = 0x03C0U ,   k_ra8_etha_off_eatasgl1 = 0x03C4U ,   k_ra8_etha_off_eatasglr = 0x03C8U ,   k_ra8_etha_off_eatasgr = 0x03D0U ,   k_ra8_etha_off_eatasgrr = 0x03D4U ,   k_ra8_etha_off_eatashcc = 0x03E0U ,   k_ra8_etha_off_eatasrirm = 0x03E4U ,   k_ra8_etha_off_eatassm = 0x03E8U ,   k_ra8_etha_off_eausmfsecn = 0x0400U ,   k_ra8_etha_off_eatfecn = 0x0404U ,   k_ra8_etha_off_eafsecn = 0x0408U ,   k_ra8_etha_off_eadqoecn = 0x040CU ,   k_ra8_etha_off_eadqsecn = 0x0410U ,   k_ra8_etha_off_eaeis0 = 0x0500U ,   k_ra8_etha_off_eaeie0 = 0x0504U ,   k_ra8_etha_off_eaeid0 = 0x0508U ,   k_ra8_etha_off_eaeis1 = 0x0510U ,   k_ra8_etha_off_eaeie1 = 0x0514U ,   k_ra8_etha_off_eaeid1 = 0x0518U ,   k_ra8_etha_off_eaeis2 = 0x0520U ,   k_ra8_etha_off_eaeie2 = 0x0524U ,   k_ra8_etha_off_eaeid2 = 0x0528U }
	Selected ETHA per-port register byte offsets (HUM Ch 32.3). More...
enum	ra8_etha_opc_t : uint8_t {   k_ra8_etha_opc_reset = 0U ,   k_ra8_etha_opc_disable = 1U ,   k_ra8_etha_opc_config = 2U ,   k_ra8_etha_opc_operation = 3U }
	ETHA EAMC.OPC[1:0] operating mode commands. More...
enum	ra8_etha_ops_t : uint8_t {   k_ra8_etha_ops_reset = 0U ,   k_ra8_etha_ops_disable = 1U ,   k_ra8_etha_ops_config = 2U ,   k_ra8_etha_ops_operation = 3U }
	ETHA EAMS.OPS[1:0] operating-mode status flag values. More...
enum	ra8_etha_mask_t : uint32_t {   k_ra8_etha_mask_opc = 0x00000003UL ,   k_ra8_etha_mask_ops = 0x00000003UL ,   k_ra8_etha_mask_ipv = 0x00000007UL ,   k_ra8_etha_mask_tc = 0x000000FFUL ,   k_ra8_etha_mask_tdqa = 0x0000000FUL ,   k_ra8_etha_mask_mfs = 0x0000FFFFUL ,   k_ra8_etha_mask_dqd = 0x000007FFUL ,   k_ra8_etha_mask_dnq = 0x000007FFUL ,   k_ra8_etha_mask_ctqd = 0x0000FFFFUL ,   k_ra8_etha_mask_ctdqd = 0x0000000FUL ,   k_ra8_etha_mask_ctqdn = 0x000003FFUL ,   k_ra8_etha_mask_vlan_vid = 0x00000FFFUL ,   k_ra8_etha_mask_vlan_pcp = 0x00000007UL ,   k_ra8_etha_mask_vlan_dei = 0x00000001UL ,   k_ra8_etha_mask_civ = 0x000FFFFFUL ,   k_ra8_etha_mask_cul = 0x7FFFFFFFUL ,   k_ra8_etha_mask_aen = 0x000001FFUL ,   k_ra8_etha_mask_tas_cycle = 0xFFFFFFFFUL ,   k_ra8_etha_mask_tas_jit = 0x0000FFFFUL ,   k_ra8_etha_mask_tas_gtl = 0x0FFFFFFFUL ,   k_ra8_etha_mask_tas_gal = 0x000000FFUL ,   k_ra8_etha_mask_tas_igs = 0x000000FFUL }
	ETHA bit masks for EAMC / EAMS / per-class fields. More...
enum	ra8_etha_tas_bits_t : uint8_t {   k_ra8_etha_eatasgl1_tasgsl_pos = 28U ,   k_ra8_etha_eatasglr_gl_pos = 31U ,   k_ra8_etha_eatasgrr_gr_pos = 31U ,   k_ra8_etha_eatasgrr_tasgsr_pos = 28U ,   k_ra8_etha_eatasrirm_tasriog_pos = 0U ,   k_ra8_etha_eatasrirm_tasrr_pos = 1U }
	Single-bit positions in the TAS learn / read / RAM-init registers. More...
enum	ra8_etha_tas_limits_t : uint16_t {   k_ra8_etha_tas_entries_max = 119U ,   k_ra8_etha_tas_addr_max = 255U ,   k_ra8_etha_tas_aen_max = 511U }
	Capacity limits the TAS RAM imposes on a schedule. More...
enum	ra8_etha_field_pos_t : uint8_t {   k_ra8_etha_eatpec_afs_pos = 16U ,   k_ra8_etha_eavcc_vem_pos = 16U ,   k_ra8_etha_eavtc_ctv_pos = 0U ,   k_ra8_etha_eavtc_ctp_pos = 12U ,   k_ra8_etha_eavtc_ctd_pos = 15U ,   k_ra8_etha_eavtc_stv_pos = 16U ,   k_ra8_etha_eavtc_stp_pos = 28U ,   k_ra8_etha_eavtc_std_pos = 31U ,   k_ra8_etha_eatasc_tase_pos = 0U ,   k_ra8_etha_eatasc_tascc_pos = 1U ,   k_ra8_etha_eatasc_tasci_pos = 2U ,   k_ra8_etha_eatasc_tasts_pos = 8U ,   k_ra8_etha_eatasc_tasca_pos = 16U ,   k_ra8_etha_pos_eaeis0_usmfses = 5U ,   k_ra8_etha_pos_eaeis0_tfes = 6U ,   k_ra8_etha_pos_eaeis0_fses = 8U ,   k_ra8_etha_pos_eaeis0_tasgees = 16U ,   k_ra8_etha_pos_eaeis0_tasctgees = 24U ,   k_ra8_etha_pos_eaeis2_dqoes = 0U ,   k_ra8_etha_pos_eaeis2_ctdqoes = 8U ,   k_ra8_etha_pos_eaeis2_dqses = 16U ,   k_ra8_etha_pos_eaeis1_cules = 0U ,   k_ra8_etha_pos_eaeis1_tasges = 16U ,   k_ra8_etha_pos_eaeis1_tasctges = 24U }
	Convenience right-shift positions for EATPEC / EAVCC bit fields. More...
enum	ra8_etha_irq_class_t : uint8_t {   k_ra8_etha_irq_class_0 = 0U ,   k_ra8_etha_irq_class_1 = 1U ,   k_ra8_etha_irq_class_2 = 2U ,   k_ra8_etha_irq_class_count = 3U }
	Identifier for one of the three error-interrupt blocks. More...
enum	ra8_etha_eaeis0_bits_t : uint32_t {   k_ra8_etha_eaeis0_decces = (1UL << 0) ,   k_ra8_etha_eaeis0_tecces = (1UL << 1) ,   k_ra8_etha_eaeis0_pecces = (1UL << 2) ,   k_ra8_etha_eaeis0_dsecces = (1UL << 3) ,   k_ra8_etha_eaeis0_l23ueecces = (1UL << 4) ,   k_ra8_etha_eaeis0_usmfses = (1UL << 5) ,   k_ra8_etha_eaeis0_tfes = (1UL << 6) ,   k_ra8_etha_eaeis0_fses_mask = 0x0000FF00UL ,   k_ra8_etha_eaeis0_tasgees_mask = 0x00FF0000UL ,   k_ra8_etha_eaeis0_tasctgees = (1UL << 24) }
	Selected EAEIS0 status flags exposed for tests / IRQ dispatch. More...
enum	ra8_etha_eaeis2_bits_t : uint32_t {   k_ra8_etha_eaeis2_dqoes_mask = 0x000000FFUL ,   k_ra8_etha_eaeis2_ctdqoes = (1UL << 8) ,   k_ra8_etha_eaeis2_dqses_mask = 0x00FF0000UL }
	Selected EAEIS2 (descriptor queue) status flags. More...
enum	ra8_etha_vem_t : uint8_t {   k_ra8_etha_vem_none = 0U ,   k_ra8_etha_vem_strip_outer = 1U ,   k_ra8_etha_vem_strip_inner = 2U ,   k_ra8_etha_vem_strip_both = 3U ,   k_ra8_etha_vem_swap = 4U }
	EAVCC.VEM[2:0] VLAN extraction mode. More...
enum	ra8_etha_vim_t : uint8_t {   k_ra8_etha_vim_disabled = 0U ,   k_ra8_etha_vim_enabled = 1U }
	EAVCC.VIM VLAN insertion mode for TX. More...
enum	ra8_etha_afs_t : uint8_t {   k_ra8_etha_afs_64 = 0U ,   k_ra8_etha_afs_128 = 1U ,   k_ra8_etha_afs_192 = 2U ,   k_ra8_etha_afs_256 = 3U }
	EATPEC.AFS[1:0] additional fragment size policy for 802.3br. More...
enum	ra8_etha_rsv_words_t : uint8_t {   k_ra8_etha_rsv_words_eatpec_to_eatmfsc = 7U ,   k_ra8_etha_rsv_words_eartfc_to_eacaec = 49U ,   k_ra8_etha_rsv_words_eacoem_to_eacoivm = 7U ,   k_ra8_etha_rsv_words_eacgsm_to_eatasc = 15U ,   k_ra8_etha_rsv_words_eatasctenc_gap = 7U ,   k_ra8_etha_rsv_words_eatasctenm_gap = 7U ,   k_ra8_etha_rsv_words_eatassm_to_eausm = 5U ,   k_ra8_etha_rsv_words_eadqsecn_to_eaeis = 59U }
	Reserved-word array sizes (in 32-bit words) used inside the ETHA per-port register block. More...
enum	ra8_etha_size_t : uint16_t { k_ra8_etha_window_bytes = 0x52CU }
	ETHA register window total size, per HUM Table 32.3 (p 1628-1630). More...

Functions
static volatile r_etha_regs_t *	ra8_etha (ra8_etha_port_t port)
	Compile-time offset and size insurance for r_etha_regs_t.

Detailed Description

Ethernet Agent (ETHA) per-port register layout for the RA8D2.

Tag

[Ring 3 / HAL] {World: NS}

ETHA is the per-port "Ethernet Agent" block that sits between the top-level Ethernet Switch Module (ESWM, HUM Ch 29) and the on-chip Ethernet MAC (RMAC, HUM Ch 33). One ETHA instance exists per Ethernet port (m = 0, 1) and each instance is mapped 0x2000 apart:

ETHA0 = 0x403C_A000 (k_ra8_etha0_base_addr in ra8_ether_regs.h) ETHA1 = 0x403C_C000 (k_ra8_etha1_base_addr in ra8_ether_regs.h)

The register layout is HUM Table 32.3 "ETHA registers" (p 1628-1630), which runs EAMC (+0x0000) to EAEID2 (+0x0528). Every named register here corresponds 1:1 with a row of that table and every offset is pinned by a static_assert below; reserved gaps are kept as reservedNN placeholders so offset arithmetic matches the chip.

The window was previously sized 0x584 to mirror the Renesas FSP CMSIS type R_ETHA0_Type, which carries a trailing EASCR at +0x0580. Chapter 32 does not mention that symbol anywhere, so it was an FSP artefact rather than a documented register and has been removed along with the driver entry point that wrote it (#539). The manual, not the vendor header, is the authority for what exists.

Eight per-traffic-class arrays (EATMFSC, EATDQDC, EATDQM, EATDQMLM, EACAIVC, EACAULC, EACOIVM, EACOULM, EATASENC, EATASENM) follow the 802.1Q/802.1Qbv (TAS) traffic-class convention used by the chip – index 0 = best-effort, index 7 = highest priority.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_etha_regs.h.

Enumeration Type Documentation

ra8_etha_afs_t

enum ra8_etha_afs_t : uint8_t

EATPEC.AFS[1:0] additional fragment size policy for 802.3br.

Enumerator
k_ra8_etha_afs_64	Minimum fragment size 64 bytes.
k_ra8_etha_afs_128	Minimum fragment size 128 bytes.
k_ra8_etha_afs_192	Minimum fragment size 192 bytes.
k_ra8_etha_afs_256	Minimum fragment size 256 bytes.

Definition at line 374 of file ra8_etha_regs.h.

ra8_etha_eaeis0_bits_t

enum ra8_etha_eaeis0_bits_t : uint32_t

Selected EAEIS0 status flags exposed for tests / IRQ dispatch.

From HUM Ch 32.3.x "EAEIS0 : Error Interrupt Status Register 0", cross-referenced with the FSP EAEIS0_b bit-field layout. Bit positions match the chip; full set lives in the register block.

Enumerator
k_ra8_etha_eaeis0_decces	Descriptor ECC error.
k_ra8_etha_eaeis0_tecces	Transmit data ECC error.
k_ra8_etha_eaeis0_pecces	Per-class ECC error.
k_ra8_etha_eaeis0_dsecces	Descriptor security ECC.
k_ra8_etha_eaeis0_l23ueecces	L2/3 unrecoverable ECC.
k_ra8_etha_eaeis0_usmfses	Switch min frame size err.
k_ra8_etha_eaeis0_tfes	Tag-filter error.
k_ra8_etha_eaeis0_fses_mask	Per-class frame size err.
k_ra8_etha_eaeis0_tasgees_mask	TAS gate-event error.
k_ra8_etha_eaeis0_tasctgees	TAS cut-through gate.

Definition at line 322 of file ra8_etha_regs.h.

ra8_etha_eaeis2_bits_t

enum ra8_etha_eaeis2_bits_t : uint32_t

Selected EAEIS2 (descriptor queue) status flags.

Enumerator
k_ra8_etha_eaeis2_dqoes_mask	TX queue overflow per-TC.
k_ra8_etha_eaeis2_ctdqoes	Cut-through queue overflow.
k_ra8_etha_eaeis2_dqses_mask	TX queue security per-TC.

Definition at line 339 of file ra8_etha_regs.h.

ra8_etha_field_pos_t

enum ra8_etha_field_pos_t : uint8_t

Convenience right-shift positions for EATPEC / EAVCC bit fields.

Enumerator
k_ra8_etha_eatpec_afs_pos	EATPEC.AFS[17:16].
k_ra8_etha_eavcc_vem_pos	EAVCC.VEM[18:16].
k_ra8_etha_eavtc_ctv_pos	EAVTC.CTV[11:0] C-VLAN VID.
k_ra8_etha_eavtc_ctp_pos	EAVTC.CTP[14:12] C-VLAN PCP.
k_ra8_etha_eavtc_ctd_pos	EAVTC.CTD[15] C-VLAN DEI.
k_ra8_etha_eavtc_stv_pos	EAVTC.STV[27:16] S-VLAN VID.
k_ra8_etha_eavtc_stp_pos	EAVTC.STP[30:28] S-VLAN PCP.
k_ra8_etha_eavtc_std_pos	EAVTC.STD[31] S-VLAN DEI.
k_ra8_etha_eatasc_tase_pos	EATASC.TASE.
k_ra8_etha_eatasc_tascc_pos	EATASC.TASCC.
k_ra8_etha_eatasc_tasci_pos	EATASC.TASCI.
k_ra8_etha_eatasc_tasts_pos	EATASC.TASTS.
k_ra8_etha_eatasc_tasca_pos	EATASC.TASCA[23:16].
k_ra8_etha_pos_eaeis0_usmfses	EAEIS0.USMFSES bit position.
k_ra8_etha_pos_eaeis0_tfes	EAEIS0.TFES bit position.
k_ra8_etha_pos_eaeis0_fses	EAEIS0.FSESq base.
k_ra8_etha_pos_eaeis0_tasgees	EAEIS0.TASGEESq base.
k_ra8_etha_pos_eaeis0_tasctgees	EAEIS0.TASCTGEES.
k_ra8_etha_pos_eaeis2_dqoes	EAEIS2.DQOESq base.
k_ra8_etha_pos_eaeis2_ctdqoes	EAEIS2.CTDQOES.
k_ra8_etha_pos_eaeis2_dqses	EAEIS2.DQSESq base.
k_ra8_etha_pos_eaeis1_cules	EAEIS1.CULESq base.
k_ra8_etha_pos_eaeis1_tasges	EAEIS1.TASGESq base.
k_ra8_etha_pos_eaeis1_tasctges	EAEIS1.TASCTGES.

Definition at line 267 of file ra8_etha_regs.h.

ra8_etha_irq_class_t

enum ra8_etha_irq_class_t : uint8_t

Identifier for one of the three error-interrupt blocks.

Each ETHA port has three independent error-interrupt status/enable triplets:

• Block 0 (EAEIS0/E/D0): ECC, switch min frame size, tag filter, per-class frame size errors, TAS gate-event errors.
• Block 1 (EAEIS1/E/D1): CBS upper-limit errors, TAS gate state.
• Block 2 (EAEIS2/E/D2): TX descriptor queue overflow + security.

Enumerator
k_ra8_etha_irq_class_0	Block 0: ECC + frame errors + TAS gate-events.
k_ra8_etha_irq_class_1	Block 1: CBS overflow + TAS gate-states.
k_ra8_etha_irq_class_2	Block 2: descriptor queue overflow + security.
k_ra8_etha_irq_class_count	RA8 etha IRQ class count.

Definition at line 306 of file ra8_etha_regs.h.

ra8_etha_mask_t

enum ra8_etha_mask_t : uint32_t

ETHA bit masks for EAMC / EAMS / per-class fields.

Enumerator
k_ra8_etha_mask_opc	EAMC.OPC[1:0].
k_ra8_etha_mask_ops	EAMS.OPS[1:0].
k_ra8_etha_mask_ipv	EAIRC.IPVRq[2:0].
k_ra8_etha_mask_tc	Per-TC byte mask.
k_ra8_etha_mask_tdqa	EATDQAC.TDQAq[3:0].
k_ra8_etha_mask_mfs	EATMFSCq.MFS[15:0].
k_ra8_etha_mask_dqd	EATDQDCq.DQD[10:0].
k_ra8_etha_mask_dnq	EATDQMq.DNQ[10:0].
k_ra8_etha_mask_ctqd	EACTQC.CTQD[15:0].
k_ra8_etha_mask_ctdqd	EACTDQDC.CTDQD[3:0].
k_ra8_etha_mask_ctqdn	EACTDQM.CTQDN[9:0].
k_ra8_etha_mask_vlan_vid	EAVTC VID 12-bit field.
k_ra8_etha_mask_vlan_pcp	EAVTC PCP 3-bit field.
k_ra8_etha_mask_vlan_dei	EAVTC DEI 1-bit field.
k_ra8_etha_mask_civ	EACAIVCq.CIV[19:0].
k_ra8_etha_mask_cul	EACAULCq.CUL[30:0].
k_ra8_etha_mask_aen	EATASENC.TASAEN[8:0].
k_ra8_etha_mask_tas_cycle	EATASCTC TASACT 32-bit.
k_ra8_etha_mask_tas_jit	EATASHCC.TASJ[15:0].
k_ra8_etha_mask_tas_gtl	EATASGL1.TASGTL[27:0].
k_ra8_etha_mask_tas_gal	EATASGL0.TASGAL[7:0].
k_ra8_etha_mask_tas_igs	EATASIGSC.TASIGS7..0.

Definition at line 193 of file ra8_etha_regs.h.

ra8_etha_offset_t

enum ra8_etha_offset_t : uint16_t

Selected ETHA per-port register byte offsets (HUM Ch 32.3).

Provided for callers that need to reach a register by offset (e.g. generic dump routines). The full layout is captured by r_etha_regs_t and each driver call uses the named field directly.

Enumerator
k_ra8_etha_off_eamc	EAMC: Mode Configuration.
k_ra8_etha_off_eams	EAMS: Mode Status.
k_ra8_etha_off_eairc	EAIRC: IPV remap.
k_ra8_etha_off_eatdqsc	EATDQSC: TX queue security.
k_ra8_etha_off_eatdqc	EATDQC: TX queue control.
k_ra8_etha_off_eatdqac	EATDQAC: TX queue arbitration.
k_ra8_etha_off_eatpec	EATPEC: TX preemption cfg.
k_ra8_etha_off_eatmfsc0	EATMFSC0: per-class max frame.
k_ra8_etha_off_eatdqdc0	EATDQDC0: per-class queue cfg.
k_ra8_etha_off_eatdqm0	EATDQM0: per-class queue mon.
k_ra8_etha_off_eatdqmlm0	EATDQMLM0: max queue level.
k_ra8_etha_off_eactqc	EACTQC: cut-through queue cfg.
k_ra8_etha_off_eactdqdc	EACTDQDC: cut-through depth.
k_ra8_etha_off_eactdqm	EACTDQM: cut-through queue mon.
k_ra8_etha_off_eactdqmlm	EACTDQMLM: cut-through peak.
k_ra8_etha_off_eavcc	EAVCC: VLAN control.
k_ra8_etha_off_eavtc	EAVTC: VLAN tag config.
k_ra8_etha_off_eartfc	EARTFC: RX tag filter cfg.
k_ra8_etha_off_eacaec	EACAEC: CBS admin enable.
k_ra8_etha_off_eacc	EACC: CBS configuration.
k_ra8_etha_off_eacaivc0	EACAIVC0: CBS admin increment.
k_ra8_etha_off_eacaulc0	EACAULC0: CBS admin upper limit.
k_ra8_etha_off_eacoem	EACOEM: CBS oper enable mon.
k_ra8_etha_off_eacoivm0	EACOIVM0: CBS oper increment.
k_ra8_etha_off_eacoulm0	EACOULM0: CBS oper upper limit.
k_ra8_etha_off_eacgsm	EACGSM: CBS gate state monitor.
k_ra8_etha_off_eatasc	EATASC: TAS configuration.
k_ra8_etha_off_eatasigsc	EATASIGSC: TAS init gate state.
k_ra8_etha_off_eatasenc0	EATASENC0: TAS entry-number cfg.
k_ra8_etha_off_eatasctenc	EATASCTENC: TAS cut-through cfg.
k_ra8_etha_off_eatasenm0	EATASENM0: TAS entry-number mon.
k_ra8_etha_off_eatasctenm	EATASCTENM: TAS cut-through mon.
k_ra8_etha_off_eatascstc0	EATASCSTC0: TAS cycle start lo.
k_ra8_etha_off_eatascstc1	EATASCSTC1: TAS cycle start hi.
k_ra8_etha_off_eatascstm0	EATASCSTM0: cycle start mon lo.
k_ra8_etha_off_eatascstm1	EATASCSTM1: cycle start mon hi.
k_ra8_etha_off_eatasctc	EATASCTC: TAS cycle time cfg.
k_ra8_etha_off_eatasctm	EATASCTM: TAS cycle time mon.
k_ra8_etha_off_eatasgl0	EATASGL0: TAS gate learn 0.
k_ra8_etha_off_eatasgl1	EATASGL1: TAS gate learn 1.
k_ra8_etha_off_eatasglr	EATASGLR: TAS gate learn result.
k_ra8_etha_off_eatasgr	EATASGR: TAS gate read.
k_ra8_etha_off_eatasgrr	EATASGRR: TAS gate read result.
k_ra8_etha_off_eatashcc	EATASHCC: TAS HW calibration.
k_ra8_etha_off_eatasrirm	EATASRIRM: TAS RAM init monitor.
k_ra8_etha_off_eatassm	EATASSM: TAS status monitor.
k_ra8_etha_off_eausmfsecn	EAUSMFSECN: under-min FS err.
k_ra8_etha_off_eatfecn	EATFECN: tag filter err.
k_ra8_etha_off_eafsecn	EAFSECN: frame size err.
k_ra8_etha_off_eadqoecn	EADQOECN: queue overflow err.
k_ra8_etha_off_eadqsecn	EADQSECN: queue security err.
k_ra8_etha_off_eaeis0	EAEIS0: error IRQ status 0.
k_ra8_etha_off_eaeie0	EAEIE0: error IRQ enable 0.
k_ra8_etha_off_eaeid0	EAEID0: error IRQ disable 0.
k_ra8_etha_off_eaeis1	EAEIS1: error IRQ status 1.
k_ra8_etha_off_eaeie1	EAEIE1: error IRQ enable 1.
k_ra8_etha_off_eaeid1	EAEID1: error IRQ disable 1.
k_ra8_etha_off_eaeis2	EAEIS2: error IRQ status 2.
k_ra8_etha_off_eaeie2	EAEIE2: error IRQ enable 2.
k_ra8_etha_off_eaeid2	EAEID2: error IRQ disable 2.

Definition at line 98 of file ra8_etha_regs.h.

ra8_etha_opc_t

enum ra8_etha_opc_t : uint8_t

ETHA EAMC.OPC[1:0] operating mode commands.

From HUM Ch 32.3.1.1 "EAMC : Mode Configuration Register" p 1630.

Enumerator
k_ra8_etha_opc_reset	Enter RESET mode.
k_ra8_etha_opc_disable	Enter DISABLE mode.
k_ra8_etha_opc_config	Enter CONFIG mode.
k_ra8_etha_opc_operation	Enter OPERATION mode.

Definition at line 168 of file ra8_etha_regs.h.

ra8_etha_ops_t

enum ra8_etha_ops_t : uint8_t

ETHA EAMS.OPS[1:0] operating-mode status flag values.

From HUM Ch 32.3.1.2 "EAMS : Mode Status Register" p 1631.

Enumerator
k_ra8_etha_ops_reset	RESET mode active.
k_ra8_etha_ops_disable	DISABLE mode active.
k_ra8_etha_ops_config	CONFIG mode active.
k_ra8_etha_ops_operation	OPERATION mode active.

Definition at line 182 of file ra8_etha_regs.h.

ra8_etha_port_t

enum ra8_etha_port_t : uint8_t

ETHA port index (m = 0, 1).

Used as the first argument to every ra8_etha_* call. Maps directly to the per-port base addresses defined in ra8_ether_regs.h.

Enumerator
k_ra8_etha_port_0	ETHA port 0 (base 0x403C_A000).
k_ra8_etha_port_1	ETHA port 1 (base 0x403C_C000).
k_ra8_etha_port_count	Number of ETHA ports.

Definition at line 60 of file ra8_etha_regs.h.

ra8_etha_rsv_words_t

enum ra8_etha_rsv_words_t : uint8_t

Reserved-word array sizes (in 32-bit words) used inside the ETHA per-port register block.

Names each reserved gap so the struct definition does not depend on raw integer literals. Cross-checked against HUM Ch 32 register offset table.

Enumerator
k_ra8_etha_rsv_words_eatpec_to_eatmfsc	+0x0024..0x003F gap.
k_ra8_etha_rsv_words_eartfc_to_eacaec	+0x013C..0x01FF gap.
k_ra8_etha_rsv_words_eacoem_to_eacoivm	+0x0264..0x027F gap.
k_ra8_etha_rsv_words_eacgsm_to_eatasc	+0x02C4..0x02FF gap.
k_ra8_etha_rsv_words_eatasctenc_gap	+0x0344..0x035F gap.
k_ra8_etha_rsv_words_eatasctenm_gap	+0x0384..0x039F gap.
k_ra8_etha_rsv_words_eatassm_to_eausm	+0x03EC..0x03FF gap.
k_ra8_etha_rsv_words_eadqsecn_to_eaeis	+0x0414..0x04FF gap.

Definition at line 391 of file ra8_etha_regs.h.

ra8_etha_size_t

enum ra8_etha_size_t : uint16_t

ETHA register window total size, per HUM Table 32.3 (p 1628-1630).

The window ends at EAEID2 (+0x0528), the last row of Table 32.3, so the block is 0x52C bytes. It was previously sized 0x584 to match the FSP R_ETHA0_Type, whose trailing EASCR at +0x0580 the manual does not publish anywhere in Chapter 32 (#539).

Enumerator
k_ra8_etha_window_bytes	Total MMIO window, EAMC..EAEID2.

Definition at line 515 of file ra8_etha_regs.h.

ra8_etha_tas_bits_t

enum ra8_etha_tas_bits_t : uint8_t

Single-bit positions in the TAS learn / read / RAM-init registers.

Named from the HUM field tables so the TAS entry flow cannot repeat the defect it was written to fix: EATASGL1 bit 28 is TASGSL, the entry's one-bit GATE STATE (HUM Ch 32.3.5.14 "EATASGL1 : TAS Gate Learn Register 1" p 1652), and had been carrying an unrelated "cut-through" flag while the gate state was written into EATASGL0, whose TASGAL[7:0] field is the TAS RAM ENTRY ADDRESS (#539).

Invariant

Every value is a bit index in 0..31.

See also

ra8_etha_set_tas_schedule

Enumerator
k_ra8_etha_eatasgl1_tasgsl_pos	EATASGL1.TASGSL: entry gate state.
k_ra8_etha_eatasglr_gl_pos	EATASGLR.GL: learn in progress.
k_ra8_etha_eatasgrr_gr_pos	EATASGRR.GR: read in progress.
k_ra8_etha_eatasgrr_tasgsr_pos	EATASGRR.TASGSR: read gate state.
k_ra8_etha_eatasrirm_tasriog_pos	EATASRIRM.TASRIOG: init ongoing.
k_ra8_etha_eatasrirm_tasrr_pos	EATASRIRM.TASRR: TAS RAM ready.

Definition at line 233 of file ra8_etha_regs.h.

ra8_etha_tas_limits_t

enum ra8_etha_tas_limits_t : uint16_t

Capacity limits the TAS RAM imposes on a schedule.

TASGAL[7:0] addresses 256 TAS RAM entries, but HUM Ch 32.3.5.3 "EATASENCi : TAS Entry Number Configuration Register i" p 1647 caps the usable total: the sum of every EATASENCi.TASAEN (plus EATASCTENC.TASCTAEN) must be <= 119 when the schedule is changed while EATASC.TASE is already set, and <= 247 otherwise. The driver enforces the conservative 119 so a schedule accepted at bring-up stays legal if it is later re-programmed live.

See also

ra8_etha_set_tas_schedule

Enumerator
k_ra8_etha_tas_entries_max	Max total entries across all queues.
k_ra8_etha_tas_addr_max	Highest TAS RAM address TASGAL can hold.
k_ra8_etha_tas_aen_max	EATASENCi.TASAEN[8:0] field ceiling.

Definition at line 257 of file ra8_etha_regs.h.

ra8_etha_tc_t

enum ra8_etha_tc_t : uint8_t

Traffic-class index (q = 0..7) used by every per-class array.

From HUM Ch 32 figure 32.1 ("Block diagram"): each ETHA port owns eight traffic classes feeding the TX scheduler. Class 0 carries best-effort traffic; class 7 the highest priority. Used as the common index across EATMFSCq, EATDQDCq, EATDQMq, EATDQMLMq, EACAIVCq, EACAULCq, EACOIVMq, EACOULMq, EATASENCi, EATASENMi.

Enumerator
k_ra8_etha_tc_0	Best-effort.
k_ra8_etha_tc_1	AVB class B / general queue.
k_ra8_etha_tc_2	AVB class A.
k_ra8_etha_tc_3	Reserved priority.
k_ra8_etha_tc_4	Reserved priority.
k_ra8_etha_tc_5	Reserved priority.
k_ra8_etha_tc_6	Network control.
k_ra8_etha_tc_7	Highest priority / control / PTP.
k_ra8_etha_tc_count	Number of traffic classes per port.

Definition at line 77 of file ra8_etha_regs.h.

ra8_etha_vem_t

enum ra8_etha_vem_t : uint8_t

EAVCC.VEM[2:0] VLAN extraction mode.

From HUM Ch 32.3.x "EAVCC : Ethernet Agent VLAN Control Configuration". Selects how the agent treats the inner / outer VLAN tag on RX.

Enumerator
k_ra8_etha_vem_none	Pass through unchanged.
k_ra8_etha_vem_strip_outer	Strip outer (S-VLAN) tag on RX.
k_ra8_etha_vem_strip_inner	Strip inner (C-VLAN) tag on RX.
k_ra8_etha_vem_strip_both	Strip both S- and C-VLAN tags.
k_ra8_etha_vem_swap	Swap inner / outer tags on RX.

Definition at line 353 of file ra8_etha_regs.h.

ra8_etha_vim_t

enum ra8_etha_vim_t : uint8_t

EAVCC.VIM VLAN insertion mode for TX.

Enumerator
k_ra8_etha_vim_disabled	No VLAN insertion on TX.
k_ra8_etha_vim_enabled	Insert tag from EAVTC on TX.

Definition at line 365 of file ra8_etha_regs.h.

Function Documentation

ra8_etha()

volatile r_etha_regs_t * ra8_etha ( ra8_etha_port_t port )

inlinestatic

Compile-time offset and size insurance for r_etha_regs_t.

Every offset below is pinned to the value HUM Table 32.3 (p 1628-1630) prints for that register. If any field drifts (e.g. a reserved gap is mis-sized), these assertions fire at compile time before any test runs – silent frame corruption on the wire is avoided.

Get pointer to a per-port ETHA register block.

Parameters

[in]

port

Port identifier (k_ra8_etha_port_0 or k_ra8_etha_port_1).

Returns

Pointer to the requested ETHA register window. If the port index is out of range, returns the port-0 window so the caller still sees deterministic behaviour rather than a null-pointer dereference. The caller is expected to have range-checked the argument before calling.

Precondition

Power to the Ethernet subsystem is on (k_ra8_mstp_eswm enabled).

port is one of ra8_etha_port_t.

Postcondition

Returned pointer is non-null and aligned to 4 bytes.

Note

Not thread-safe; per-port serialisation is the caller's job.

Since

0.1.0

Definition at line 640 of file ra8_etha_regs.h.

References k_ra8_etha0_base_addr, k_ra8_etha1_base_addr, and k_ra8_etha_port_1.

Referenced by internal_etha_to_operation(), ra8_etha_clear_stats(), ra8_etha_clear_status(), ra8_etha_configure_cbs(), ra8_etha_configure_cut_through(), ra8_etha_deinit(), ra8_etha_descriptor_ring_init(), ra8_etha_disable_irq(), ra8_etha_dispatch(), ra8_etha_enable_irq(), ra8_etha_enable_tas(), ra8_etha_enter_stop(), ra8_etha_exit_stop(), ra8_etha_get_cbs_state(), ra8_etha_get_queue_level(), ra8_etha_get_status(), ra8_etha_init(), ra8_etha_read_stats(), ra8_etha_read_tas_entry(), ra8_etha_reset(), ra8_etha_set_ipv_remap(), ra8_etha_set_max_frame_size(), ra8_etha_set_mode(), ra8_etha_set_preemption(), ra8_etha_set_queue_arb(), ra8_etha_set_queue_depth(), ra8_etha_set_rx_tag_filter(), ra8_etha_set_tas_schedule(), ra8_etha_set_vlan_mode(), ra8_etha_set_vlan_tag(), and ra8_etha_tas_ram_reset().