ra8_etha_tas.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_etha.h"
#include "ra8_etha_internal.h"
#include "ra8_etha_regs.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"

static const char* s_tag = "ETHA";

typedef enum : uint32_t {
  k_ra8_etha_tas_learn_spins = 100000U, 
  k_ra8_etha_tas_ram_spins   = 100000U, 
} ra8_etha_tas_poll_t;

typedef enum : uint32_t {
  k_ra8_etha_tas_word_mask = 0xFFFFFFFFUL, 
} ra8_etha_tas_word_t;

RA8_INTERNAL
static ra8_err_t internal_tas_learn_entry(volatile r_etha_regs_t*     reg,
                                          uint8_t                     address,
                                          const ra8_etha_tas_entry_t* entry)
{
  /* HUM Ch 32.3.5.13 "EATASGL0 : TAS Gate Learn Register 0" p 1652 */
  reg->EATASGL0 = (uint32_t)address & k_ra8_etha_mask_tas_gal;
 
  uint32_t gl1 = entry->gate_time_ns & k_ra8_etha_mask_tas_gtl;
  if (entry->gate_open) {
    gl1 |= (uint32_t)1U << (uint32_t)k_ra8_etha_eatasgl1_tasgsl_pos;
  }
  /* HUM Ch 32.3.5.14 "EATASGL1 : TAS Gate Learn Register 1" p 1652 */
  reg->EATASGL1 = gl1;
 
  /* HUM Ch 32.3.5.15 "EATASGLR : TAS Gate Learn Result Register" p 1653 */
  const ra8_err_t err =
    ra8_hw_wait_flag_clear32(&reg->EATASGLR,
                             (uint32_t)1U << (uint32_t)k_ra8_etha_eatasglr_gl_pos,
                             (uint32_t)k_ra8_etha_tas_learn_spins);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_tas: EATASGLR.GL never cleared");
  }
  return err;
}

RA8_INTERNAL
static ra8_err_t internal_tas_validate(const ra8_etha_tas_queue_t* queues)
{
  uint32_t total = 0U;
  RA8_LOOP_BOUND(k_ra8_etha_tc_count);
  for (uint8_t queue = 0U; queue < (uint8_t)k_ra8_etha_tc_count; ++queue) {
    const uint16_t count = queues[queue].count;
    if (count == 0U) {
      continue;
    }
    RA8_CHECK_NULL_PTR(queues[queue].entries, s_tag, "etha_tas: queue entries null");
    RA8_LOOP_BOUND(k_ra8_etha_tas_entries_max);
    for (uint16_t index = 0U; index < count; ++index) {
      if (queues[queue].entries[index].gate_time_ns > k_ra8_etha_mask_tas_gtl) {
        ra8_log_error(s_tag, "etha_tas: gate time exceeds TASGTL[27:0]");
        return k_ra8_err_invalid_arg;
      }
    }
    total += (uint32_t)count;
  }
  if (total > (uint32_t)k_ra8_etha_tas_entries_max) {
    ra8_log_error(s_tag, "etha_tas: total entries exceed TAS RAM capacity");
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_tas_learn_all(volatile r_etha_regs_t*     reg,
                                        const ra8_etha_tas_queue_t* queues,
                                        uint8_t                     base)
{
  uint32_t address = (uint32_t)base;
  RA8_LOOP_BOUND(k_ra8_etha_tc_count);
  for (uint8_t queue = 0U; queue < (uint8_t)k_ra8_etha_tc_count; ++queue) {
    RA8_LOOP_BOUND(k_ra8_etha_tas_entries_max);
    for (uint16_t index = 0U; index < queues[queue].count; ++index) {
      const ra8_err_t err = internal_tas_learn_entry(reg,
                                                     (uint8_t)(address & k_ra8_etha_mask_tas_gal),
                                                     &queues[queue].entries[index]);
      if (err != k_ra8_ok) {
        return err;
      }
      ++address;
    }
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_tas_ram_reset(ra8_etha_port_t port)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_tas_ram_reset: port out of range");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
 
  /* HUM Ch 32.3.5.19 "EATASRIRM : TAS RAM Initialization Register Monitoring" p 1655 */
  reg->EATASRIRM = (uint32_t)1U << (uint32_t)k_ra8_etha_eatasrirm_tasriog_pos;
 
  /* HUM Ch 32.3.5.19 "EATASRIRM : TAS RAM Initialization Register Monitoring" p 1655 */
  const ra8_err_t err =
    ra8_hw_wait_flag_set32(&reg->EATASRIRM,
                           (uint32_t)1U << (uint32_t)k_ra8_etha_eatasrirm_tasrr_pos,
                           (uint32_t)k_ra8_etha_tas_ram_spins);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_tas_ram_reset: EATASRIRM.TASRR never asserted");
  }
  return err;
}

RA8_INTERNAL
static void internal_tas_program_timing(volatile r_etha_regs_t*     reg,
                                        const ra8_etha_tas_queue_t* queues,
                                        uint8_t                     initial_gate_states,
                                        uint32_t                    cycle_time_ns,
                                        uint64_t                    start_time)
{
  /* HUM Ch 32.3.5.2 "EATASIGSC : TAS Initial Gate State Configuration Register" p 1647 */
  reg->EATASIGSC = (uint32_t)initial_gate_states & k_ra8_etha_mask_tas_igs;
  RA8_LOOP_BOUND(k_ra8_etha_tc_count);
  for (uint8_t queue = 0U; queue < (uint8_t)k_ra8_etha_tc_count; ++queue) {
    /* HUM Ch 32.3.5.3 "EATASENCi : TAS Entry Number Configuration Register i" p 1647 */
    reg->EATASENC[queue] = (uint32_t)queues[queue].count & k_ra8_etha_mask_aen;
  }
  /* HUM Ch 32.3.5.7 "EATASCSTC0 : TAS Cycle Start Time Configuration Register 0" p 1649 */
  reg->EATASCSTC0 = (uint32_t)(start_time & (uint64_t)k_ra8_etha_tas_word_mask);
  /* HUM Ch 32.3.5.8 "EATASCSTC1 : TAS Cycle Start Time Configuration Register 1" p 1650 */
  reg->EATASCSTC1 = (uint32_t)((start_time >> 32U) & (uint64_t)k_ra8_etha_tas_word_mask);
  /* HUM Ch 32.3.5.11 "EATASCTC : TAS Cycle Time Configuration Register" p 1651 */
  reg->EATASCTC = cycle_time_ns;
}
 
ra8_err_t ra8_etha_set_tas_schedule(ra8_etha_port_t             port,
                                    const ra8_etha_tas_queue_t* queues,
                                    uint8_t                     initial_gate_states,
                                    uint32_t                    cycle_time_ns,
                                    uint64_t                    start_time)
{
  RA8_CHECK_NULL_PTR(queues, s_tag, "etha_set_tas_schedule: queues null");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_set_tas_schedule: port out of range");
    return k_ra8_err_invalid_arg;
  }
  const ra8_err_t valid_err = internal_tas_validate(queues);
  if (valid_err != k_ra8_ok) {
    return valid_err;
  }
 
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.5.1 "EATASC : TAS Configuration Register" p 1646 */
  const uint32_t tasc = reg->EATASC;
  if ((tasc & ((uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tasci_pos)) != 0U) {
    ra8_log_error(s_tag, "etha_set_tas_schedule: EATASC.TASCI set");
    return k_ra8_err_busy;
  }
  const uint8_t base =
    (uint8_t)((tasc >> (uint32_t)k_ra8_etha_eatasc_tasca_pos) & k_ra8_etha_mask_tas_gal);
  const bool already_enabled =
    (tasc & ((uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tase_pos)) != 0U;
 
  internal_tas_program_timing(reg, queues, initial_gate_states, cycle_time_ns, start_time);
 
  const ra8_err_t learn_err = internal_tas_learn_all(reg, queues, base);
  if (learn_err != k_ra8_ok) {
    return learn_err;
  }
 
  /* Commit: TASE always, TASCC only when this replaces a running schedule
   * (HUM Figure 32.11's two terminal boxes). */
  uint32_t commit = tasc | ((uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tase_pos);
  if (already_enabled) {
    commit |= (uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tascc_pos;
  } else {
    commit &= ~((uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tascc_pos);
  }
  /* HUM Ch 32.3.5.1 "EATASC : TAS Configuration Register" p 1646 */
  reg->EATASC = commit;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_read_tas_entry(ra8_etha_port_t port, uint8_t address, ra8_etha_tas_entry_t* out)
{
  RA8_CHECK_NULL_PTR(out, s_tag, "etha_read_tas_entry: out null");
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_read_tas_entry: port out of range");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
 
  /* HUM Ch 32.3.5.16 "EATASGR : TAS Gate Read Register" p 1653 */
  reg->EATASGR = (uint32_t)address & k_ra8_etha_mask_tas_gal;
 
  /* HUM Ch 32.3.5.17 "EATASGRR : TAS Gate Read Result Register" p 1654 */
  const ra8_err_t err =
    ra8_hw_wait_flag_clear32(&reg->EATASGRR,
                             (uint32_t)1U << (uint32_t)k_ra8_etha_eatasgrr_gr_pos,
                             (uint32_t)k_ra8_etha_tas_learn_spins);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_read_tas_entry: EATASGRR.GR never cleared");
    return err;
  }
  /* HUM Ch 32.3.5.17 "EATASGRR : TAS Gate Read Result Register" p 1654 */
  const uint32_t grr = reg->EATASGRR;
  out->gate_time_ns  = grr & k_ra8_etha_mask_tas_gtl;
  out->gate_open     = (grr & ((uint32_t)1U << (uint32_t)k_ra8_etha_eatasgrr_tasgsr_pos)) != 0U;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_enable_tas(ra8_etha_port_t port, uint8_t enable)
{
  if (!internal_port_ok(port)) {
    ra8_log_error(s_tag, "etha_enable_tas: port out of range");
    return k_ra8_err_invalid_arg;
  }
  volatile r_etha_regs_t* reg = ra8_etha(port);
  /* HUM Ch 32.3.5.1 "EATASC : TAS Configuration Register" p 1646 */
  const uint32_t tasc = reg->EATASC;
  const uint32_t bit  = (uint32_t)1U << (uint32_t)k_ra8_etha_eatasc_tase_pos;
  /* HUM Ch 32.3.5.1 "EATASC : TAS Configuration Register" p 1646 */
  reg->EATASC = (enable != 0U) ? (tasc | bit) : (tasc & ~bit);
  return k_ra8_ok;
}