ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_etha_regs.h
Go to the documentation of this file.
1
39
40#pragma once
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <stddef.h>
47#include <stdint.h>
48
49#include "ra8_attributes.h"
50#include "ra8_ether_regs.h"
51
65
88
98typedef enum : uint16_t {
160
174
188
193typedef enum : uint32_t {
194 k_ra8_etha_mask_opc = 0x00000003UL,
195 k_ra8_etha_mask_ops = 0x00000003UL,
196 k_ra8_etha_mask_ipv = 0x00000007UL,
197 k_ra8_etha_mask_tc = 0x000000FFUL,
198 k_ra8_etha_mask_tdqa = 0x0000000FUL,
199 k_ra8_etha_mask_mfs = 0x0000FFFFUL,
200 k_ra8_etha_mask_dqd = 0x000007FFUL,
201 k_ra8_etha_mask_dnq = 0x000007FFUL,
202 k_ra8_etha_mask_ctqd = 0x0000FFFFUL,
203 k_ra8_etha_mask_ctdqd = 0x0000000FUL,
204 k_ra8_etha_mask_ctqdn = 0x000003FFUL,
208 k_ra8_etha_mask_civ = 0x000FFFFFUL,
209 k_ra8_etha_mask_cul = 0x7FFFFFFFUL,
210 k_ra8_etha_mask_aen = 0x000001FFUL,
212 k_ra8_etha_mask_tas_jit = 0x0000FFFFUL,
213 k_ra8_etha_mask_tas_gtl = 0x0FFFFFFFUL,
214 k_ra8_etha_mask_tas_gal = 0x000000FFUL,
215 k_ra8_etha_mask_tas_igs = 0x000000FFUL,
217
241
262
293
312
334
339typedef enum : uint32_t {
344
360
369
380
401
415typedef struct {
416 volatile uint32_t EAMC;
417 volatile uint32_t EAMS;
418 volatile uint32_t reserved08;
419 volatile uint32_t reserved0C;
420 volatile uint32_t EAIRC;
421 volatile uint32_t EATDQSC;
422 volatile uint32_t EATDQC;
423 volatile uint32_t EATDQAC;
424 volatile uint32_t EATPEC;
425 volatile uint32_t reserved24
427 volatile uint32_t EATMFSC[8];
428 volatile uint32_t EATDQDC[8];
429 volatile uint32_t EATDQM[8];
430 volatile uint32_t EATDQMLM[8];
431 volatile uint32_t reservedC0[16];
432 volatile uint32_t EACTQC;
433 volatile uint32_t EACTDQDC;
434 volatile uint32_t EACTDQM;
435 volatile uint32_t EACTDQMLM;
436 volatile uint32_t reserved110[8];
437 volatile uint32_t EAVCC;
438 volatile uint32_t EAVTC;
439 volatile uint32_t EARTFC;
440 volatile uint32_t
442 volatile uint32_t EACAEC;
443 volatile uint32_t EACC;
444 volatile uint32_t reserved208[6];
445 volatile uint32_t EACAIVC[8];
446 volatile uint32_t EACAULC[8];
447 volatile uint32_t EACOEM;
448 volatile uint32_t reserved264
450 volatile uint32_t EACOIVM[8];
451 volatile uint32_t EACOULM[8];
452 volatile uint32_t EACGSM;
453 volatile uint32_t
455 volatile uint32_t EATASC;
456 volatile uint32_t EATASIGSC;
457 volatile uint32_t reserved308[6];
458 volatile uint32_t EATASENC[8];
459 volatile uint32_t EATASCTENC;
460 volatile uint32_t
462 volatile uint32_t EATASENM[8];
463 volatile uint32_t EATASCTENM;
464 volatile uint32_t
466 volatile uint32_t EATASCSTC0;
467 volatile uint32_t EATASCSTC1;
468 volatile uint32_t EATASCSTM0;
469 volatile uint32_t EATASCSTM1;
470 volatile uint32_t EATASCTC;
471 volatile uint32_t EATASCTM;
472 volatile uint32_t reserved3B8[2];
473 volatile uint32_t EATASGL0;
474 volatile uint32_t EATASGL1;
475 volatile uint32_t EATASGLR;
476 volatile uint32_t reserved3CC;
477 volatile uint32_t EATASGR;
478 volatile uint32_t EATASGRR;
479 volatile uint32_t reserved3D8[2];
480 volatile uint32_t EATASHCC;
481 volatile uint32_t EATASRIRM;
482 volatile uint32_t EATASSM;
483 volatile uint32_t reserved3EC
485 volatile uint32_t EAUSMFSECN;
486 volatile uint32_t EATFECN;
487 volatile uint32_t EAFSECN;
488 volatile uint32_t EADQOECN;
489 volatile uint32_t EADQSECN;
490 volatile uint32_t
492 volatile uint32_t EAEIS0;
493 volatile uint32_t EAEIE0;
494 volatile uint32_t EAEID0;
495 volatile uint32_t reserved50C;
496 volatile uint32_t EAEIS1;
497 volatile uint32_t EAEIE1;
498 volatile uint32_t EAEID1;
499 volatile uint32_t reserved51C;
500 volatile uint32_t EAEIS2;
501 volatile uint32_t EAEIE2;
502 volatile uint32_t EAEID2;
504
515typedef enum : uint16_t {
518
528static_assert(sizeof(r_etha_regs_t) == (size_t)k_ra8_etha_window_bytes,
529 "r_etha_regs_t must span EAMC..EAEID2 (HUM Table 32.3)");
530
531static_assert(offsetof(r_etha_regs_t, EAMC) == (size_t)k_ra8_etha_off_eamc, "EAMC offset");
532static_assert(offsetof(r_etha_regs_t, EAMS) == (size_t)k_ra8_etha_off_eams, "EAMS offset");
533static_assert(offsetof(r_etha_regs_t, EAIRC) == (size_t)k_ra8_etha_off_eairc, "EAIRC offset");
534static_assert(offsetof(r_etha_regs_t, EATDQSC) == (size_t)k_ra8_etha_off_eatdqsc, "EATDQSC offset");
535static_assert(offsetof(r_etha_regs_t, EATDQC) == (size_t)k_ra8_etha_off_eatdqc, "EATDQC offset");
536static_assert(offsetof(r_etha_regs_t, EATDQAC) == (size_t)k_ra8_etha_off_eatdqac, "EATDQAC offset");
537static_assert(offsetof(r_etha_regs_t, EATPEC) == (size_t)k_ra8_etha_off_eatpec, "EATPEC offset");
538static_assert(offsetof(r_etha_regs_t, EATMFSC) == (size_t)k_ra8_etha_off_eatmfsc0,
539 "EATMFSC offset");
540static_assert(offsetof(r_etha_regs_t, EATDQDC) == (size_t)k_ra8_etha_off_eatdqdc0,
541 "EATDQDC offset");
542static_assert(offsetof(r_etha_regs_t, EATDQM) == (size_t)k_ra8_etha_off_eatdqm0, "EATDQM offset");
543static_assert(offsetof(r_etha_regs_t, EATDQMLM) == (size_t)k_ra8_etha_off_eatdqmlm0,
544 "EATDQMLM offset");
545static_assert(offsetof(r_etha_regs_t, EACTQC) == (size_t)k_ra8_etha_off_eactqc, "EACTQC offset");
546static_assert(offsetof(r_etha_regs_t, EAVCC) == (size_t)k_ra8_etha_off_eavcc, "EAVCC offset");
547static_assert(offsetof(r_etha_regs_t, EAVTC) == (size_t)k_ra8_etha_off_eavtc, "EAVTC offset");
548static_assert(offsetof(r_etha_regs_t, EARTFC) == (size_t)k_ra8_etha_off_eartfc, "EARTFC offset");
549static_assert(offsetof(r_etha_regs_t, EACAEC) == (size_t)k_ra8_etha_off_eacaec, "EACAEC offset");
550static_assert(offsetof(r_etha_regs_t, EACC) == (size_t)k_ra8_etha_off_eacc, "EACC offset");
551static_assert(offsetof(r_etha_regs_t, EACAIVC) == (size_t)k_ra8_etha_off_eacaivc0,
552 "EACAIVC offset");
553static_assert(offsetof(r_etha_regs_t, EACAULC) == (size_t)k_ra8_etha_off_eacaulc0,
554 "EACAULC offset");
555static_assert(offsetof(r_etha_regs_t, EACOEM) == (size_t)k_ra8_etha_off_eacoem, "EACOEM offset");
556static_assert(offsetof(r_etha_regs_t, EACOIVM) == (size_t)k_ra8_etha_off_eacoivm0,
557 "EACOIVM offset");
558static_assert(offsetof(r_etha_regs_t, EACOULM) == (size_t)k_ra8_etha_off_eacoulm0,
559 "EACOULM offset");
560static_assert(offsetof(r_etha_regs_t, EACGSM) == (size_t)k_ra8_etha_off_eacgsm, "EACGSM offset");
561static_assert(offsetof(r_etha_regs_t, EATASC) == (size_t)k_ra8_etha_off_eatasc, "EATASC offset");
562static_assert(offsetof(r_etha_regs_t, EATASIGSC) == (size_t)k_ra8_etha_off_eatasigsc,
563 "EATASIGSC offset");
564static_assert(offsetof(r_etha_regs_t, EATASENC) == (size_t)k_ra8_etha_off_eatasenc0,
565 "EATASENC offset");
566static_assert(offsetof(r_etha_regs_t, EATASCTENC) == (size_t)k_ra8_etha_off_eatasctenc,
567 "EATASCTENC offset");
568static_assert(offsetof(r_etha_regs_t, EATASENM) == (size_t)k_ra8_etha_off_eatasenm0,
569 "EATASENM offset");
570static_assert(offsetof(r_etha_regs_t, EATASCTENM) == (size_t)k_ra8_etha_off_eatasctenm,
571 "EATASCTENM offset");
572static_assert(offsetof(r_etha_regs_t, EATASCSTC0) == (size_t)k_ra8_etha_off_eatascstc0,
573 "EATASCSTC0 offset");
574static_assert(offsetof(r_etha_regs_t, EATASCTC) == (size_t)k_ra8_etha_off_eatasctc,
575 "EATASCTC offset");
576static_assert(offsetof(r_etha_regs_t, EATASGL0) == (size_t)k_ra8_etha_off_eatasgl0,
577 "EATASGL0 offset");
578static_assert(offsetof(r_etha_regs_t, EATASGR) == (size_t)k_ra8_etha_off_eatasgr, "EATASGR offset");
579static_assert(offsetof(r_etha_regs_t, EATASHCC) == (size_t)k_ra8_etha_off_eatashcc,
580 "EATASHCC offset");
581static_assert(offsetof(r_etha_regs_t, EATASSM) == (size_t)k_ra8_etha_off_eatassm, "EATASSM offset");
582static_assert(offsetof(r_etha_regs_t, EAUSMFSECN) == (size_t)k_ra8_etha_off_eausmfsecn,
583 "EAUSMFSECN offset");
584static_assert(offsetof(r_etha_regs_t, EATFECN) == (size_t)k_ra8_etha_off_eatfecn, "EATFECN offset");
585static_assert(offsetof(r_etha_regs_t, EAFSECN) == (size_t)k_ra8_etha_off_eafsecn, "EAFSECN offset");
586static_assert(offsetof(r_etha_regs_t, EADQOECN) == (size_t)k_ra8_etha_off_eadqoecn,
587 "EADQOECN offset");
588static_assert(offsetof(r_etha_regs_t, EADQSECN) == (size_t)k_ra8_etha_off_eadqsecn,
589 "EADQSECN offset");
590static_assert(offsetof(r_etha_regs_t, EAEIS0) == (size_t)k_ra8_etha_off_eaeis0, "EAEIS0 offset");
591static_assert(offsetof(r_etha_regs_t, EAEIE0) == (size_t)k_ra8_etha_off_eaeie0, "EAEIE0 offset");
592static_assert(offsetof(r_etha_regs_t, EAEID0) == (size_t)k_ra8_etha_off_eaeid0, "EAEID0 offset");
593static_assert(offsetof(r_etha_regs_t, EAEIS1) == (size_t)k_ra8_etha_off_eaeis1, "EAEIS1 offset");
594static_assert(offsetof(r_etha_regs_t, EAEIE1) == (size_t)k_ra8_etha_off_eaeie1, "EAEIE1 offset");
595static_assert(offsetof(r_etha_regs_t, EAEID1) == (size_t)k_ra8_etha_off_eaeid1, "EAEID1 offset");
596static_assert(offsetof(r_etha_regs_t, EAEIS2) == (size_t)k_ra8_etha_off_eaeis2, "EAEIS2 offset");
597static_assert(offsetof(r_etha_regs_t, EAEIE2) == (size_t)k_ra8_etha_off_eaeie2, "EAEIE2 offset");
598static_assert(offsetof(r_etha_regs_t, EAEID2) == (size_t)k_ra8_etha_off_eaeid2, "EAEID2 offset");
599static_assert(offsetof(r_etha_regs_t, EACTDQDC) == (size_t)k_ra8_etha_off_eactdqdc,
600 "EACTDQDC offset");
601static_assert(offsetof(r_etha_regs_t, EACTDQM) == (size_t)k_ra8_etha_off_eactdqm, "EACTDQM offset");
602static_assert(offsetof(r_etha_regs_t, EACTDQMLM) == (size_t)k_ra8_etha_off_eactdqmlm,
603 "EACTDQMLM offset");
604static_assert(offsetof(r_etha_regs_t, EATASCSTC1) == (size_t)k_ra8_etha_off_eatascstc1,
605 "EATASCSTC1 offset");
606static_assert(offsetof(r_etha_regs_t, EATASCSTM0) == (size_t)k_ra8_etha_off_eatascstm0,
607 "EATASCSTM0 offset");
608static_assert(offsetof(r_etha_regs_t, EATASCSTM1) == (size_t)k_ra8_etha_off_eatascstm1,
609 "EATASCSTM1 offset");
610static_assert(offsetof(r_etha_regs_t, EATASCTM) == (size_t)k_ra8_etha_off_eatasctm,
611 "EATASCTM offset");
612static_assert(offsetof(r_etha_regs_t, EATASGL1) == (size_t)k_ra8_etha_off_eatasgl1,
613 "EATASGL1 offset");
614static_assert(offsetof(r_etha_regs_t, EATASGLR) == (size_t)k_ra8_etha_off_eatasglr,
615 "EATASGLR offset");
616static_assert(offsetof(r_etha_regs_t, EATASGRR) == (size_t)k_ra8_etha_off_eatasgrr,
617 "EATASGRR offset");
618static_assert(offsetof(r_etha_regs_t, EATASRIRM) == (size_t)k_ra8_etha_off_eatasrirm,
619 "EATASRIRM offset");
620
640static inline volatile r_etha_regs_t* ra8_etha(ra8_etha_port_t port)
641{
642 uintptr_t base = k_ra8_etha0_base_addr;
643 if (port == k_ra8_etha_port_1) {
645 }
646 return (volatile r_etha_regs_t*)base;
647}
648
649#ifdef __cplusplus
650}
651#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
ra8_etha_rsv_words_t
Reserved-word array sizes (in 32-bit words) used inside the ETHA per-port register block.
@ k_ra8_etha_rsv_words_eartfc_to_eacaec
+0x013C..0x01FF gap.
@ k_ra8_etha_rsv_words_eatasctenc_gap
+0x0344..0x035F gap.
@ k_ra8_etha_rsv_words_eacoem_to_eacoivm
+0x0264..0x027F gap.
@ k_ra8_etha_rsv_words_eacgsm_to_eatasc
+0x02C4..0x02FF gap.
@ k_ra8_etha_rsv_words_eadqsecn_to_eaeis
+0x0414..0x04FF gap.
@ k_ra8_etha_rsv_words_eatpec_to_eatmfsc
+0x0024..0x003F gap.
@ k_ra8_etha_rsv_words_eatasctenm_gap
+0x0384..0x039F gap.
@ k_ra8_etha_rsv_words_eatassm_to_eausm
+0x03EC..0x03FF gap.
ra8_etha_port_t
ETHA port index (m = 0, 1).
@ k_ra8_etha_port_count
Number of ETHA ports.
@ k_ra8_etha_port_0
ETHA port 0 (base 0x403C_A000).
@ k_ra8_etha_port_1
ETHA port 1 (base 0x403C_C000).
ra8_etha_afs_t
EATPEC.AFS[1:0] additional fragment size policy for 802.3br.
@ k_ra8_etha_afs_64
Minimum fragment size 64 bytes.
@ k_ra8_etha_afs_256
Minimum fragment size 256 bytes.
@ k_ra8_etha_afs_128
Minimum fragment size 128 bytes.
@ k_ra8_etha_afs_192
Minimum fragment size 192 bytes.
ra8_etha_size_t
ETHA register window total size, per HUM Table 32.3 (p 1628-1630).
@ k_ra8_etha_window_bytes
Total MMIO window, EAMC..EAEID2.
ra8_etha_tc_t
Traffic-class index (q = 0..7) used by every per-class array.
@ k_ra8_etha_tc_7
Highest priority / control / PTP.
@ k_ra8_etha_tc_6
Network control.
@ k_ra8_etha_tc_3
Reserved priority.
@ k_ra8_etha_tc_count
Number of traffic classes per port.
@ k_ra8_etha_tc_5
Reserved priority.
@ k_ra8_etha_tc_2
AVB class A.
@ k_ra8_etha_tc_0
Best-effort.
@ k_ra8_etha_tc_1
AVB class B / general queue.
@ k_ra8_etha_tc_4
Reserved priority.
ra8_etha_opc_t
ETHA EAMC.OPC[1:0] operating mode commands.
@ k_ra8_etha_opc_operation
Enter OPERATION mode.
@ k_ra8_etha_opc_config
Enter CONFIG mode.
@ k_ra8_etha_opc_reset
Enter RESET mode.
@ k_ra8_etha_opc_disable
Enter DISABLE mode.
ra8_etha_ops_t
ETHA EAMS.OPS[1:0] operating-mode status flag values.
@ k_ra8_etha_ops_disable
DISABLE mode active.
@ k_ra8_etha_ops_config
CONFIG mode active.
@ k_ra8_etha_ops_reset
RESET mode active.
@ k_ra8_etha_ops_operation
OPERATION mode active.
ra8_etha_eaeis2_bits_t
Selected EAEIS2 (descriptor queue) status flags.
@ k_ra8_etha_eaeis2_ctdqoes
Cut-through queue overflow.
@ k_ra8_etha_eaeis2_dqses_mask
TX queue security per-TC.
@ k_ra8_etha_eaeis2_dqoes_mask
TX queue overflow per-TC.
ra8_etha_irq_class_t
Identifier for one of the three error-interrupt blocks.
@ k_ra8_etha_irq_class_1
Block 1: CBS overflow + TAS gate-states.
@ k_ra8_etha_irq_class_2
Block 2: descriptor queue overflow + security.
@ k_ra8_etha_irq_class_0
Block 0: ECC + frame errors + TAS gate-events.
@ k_ra8_etha_irq_class_count
RA8 etha IRQ class count.
ra8_etha_tas_limits_t
Capacity limits the TAS RAM imposes on a schedule.
@ k_ra8_etha_tas_aen_max
EATASENCi.TASAEN[8:0] field ceiling.
@ k_ra8_etha_tas_entries_max
Max total entries across all queues.
@ k_ra8_etha_tas_addr_max
Highest TAS RAM address TASGAL can hold.
static volatile r_etha_regs_t * ra8_etha(ra8_etha_port_t port)
Compile-time offset and size insurance for r_etha_regs_t.
ra8_etha_vim_t
EAVCC.VIM VLAN insertion mode for TX.
@ k_ra8_etha_vim_disabled
No VLAN insertion on TX.
@ k_ra8_etha_vim_enabled
Insert tag from EAVTC on TX.
ra8_etha_field_pos_t
Convenience right-shift positions for EATPEC / EAVCC bit fields.
@ k_ra8_etha_pos_eaeis0_usmfses
EAEIS0.USMFSES bit position.
@ k_ra8_etha_eavtc_stv_pos
EAVTC.STV[27:16] S-VLAN VID.
@ k_ra8_etha_pos_eaeis0_fses
EAEIS0.FSESq base.
@ k_ra8_etha_eatasc_tasca_pos
EATASC.TASCA[23:16].
@ k_ra8_etha_pos_eaeis2_ctdqoes
EAEIS2.CTDQOES.
@ k_ra8_etha_eavtc_std_pos
EAVTC.STD[31] S-VLAN DEI.
@ k_ra8_etha_eatasc_tase_pos
EATASC.TASE.
@ k_ra8_etha_pos_eaeis1_tasctges
EAEIS1.TASCTGES.
@ k_ra8_etha_pos_eaeis0_tfes
EAEIS0.TFES bit position.
@ k_ra8_etha_eatasc_tasts_pos
EATASC.TASTS.
@ k_ra8_etha_eavtc_ctp_pos
EAVTC.CTP[14:12] C-VLAN PCP.
@ k_ra8_etha_pos_eaeis1_tasges
EAEIS1.TASGESq base.
@ k_ra8_etha_eatasc_tasci_pos
EATASC.TASCI.
@ k_ra8_etha_pos_eaeis1_cules
EAEIS1.CULESq base.
@ k_ra8_etha_eavtc_ctd_pos
EAVTC.CTD[15] C-VLAN DEI.
@ k_ra8_etha_eavtc_stp_pos
EAVTC.STP[30:28] S-VLAN PCP.
@ k_ra8_etha_eavtc_ctv_pos
EAVTC.CTV[11:0] C-VLAN VID.
@ k_ra8_etha_pos_eaeis2_dqses
EAEIS2.DQSESq base.
@ k_ra8_etha_eatpec_afs_pos
EATPEC.AFS[17:16].
@ k_ra8_etha_pos_eaeis0_tasgees
EAEIS0.TASGEESq base.
@ k_ra8_etha_pos_eaeis0_tasctgees
EAEIS0.TASCTGEES.
@ k_ra8_etha_eatasc_tascc_pos
EATASC.TASCC.
@ k_ra8_etha_eavcc_vem_pos
EAVCC.VEM[18:16].
@ k_ra8_etha_pos_eaeis2_dqoes
EAEIS2.DQOESq base.
ra8_etha_tas_bits_t
Single-bit positions in the TAS learn / read / RAM-init registers.
@ k_ra8_etha_eatasglr_gl_pos
EATASGLR.GL: learn in progress.
@ k_ra8_etha_eatasrirm_tasriog_pos
EATASRIRM.TASRIOG: init ongoing.
@ k_ra8_etha_eatasgl1_tasgsl_pos
EATASGL1.TASGSL: entry gate state.
@ k_ra8_etha_eatasrirm_tasrr_pos
EATASRIRM.TASRR: TAS RAM ready.
@ k_ra8_etha_eatasgrr_gr_pos
EATASGRR.GR: read in progress.
@ k_ra8_etha_eatasgrr_tasgsr_pos
EATASGRR.TASGSR: read gate state.
ra8_etha_offset_t
Selected ETHA per-port register byte offsets (HUM Ch 32.3).
@ k_ra8_etha_off_eacaivc0
EACAIVC0: CBS admin increment.
@ k_ra8_etha_off_eatassm
EATASSM: TAS status monitor.
@ k_ra8_etha_off_eatmfsc0
EATMFSC0: per-class max frame.
@ k_ra8_etha_off_eatasenm0
EATASENM0: TAS entry-number mon.
@ k_ra8_etha_off_eaeie0
EAEIE0: error IRQ enable 0.
@ k_ra8_etha_off_eacaulc0
EACAULC0: CBS admin upper limit.
@ k_ra8_etha_off_eactqc
EACTQC: cut-through queue cfg.
@ k_ra8_etha_off_eadqoecn
EADQOECN: queue overflow err.
@ k_ra8_etha_off_eaeie1
EAEIE1: error IRQ enable 1.
@ k_ra8_etha_off_eaeie2
EAEIE2: error IRQ enable 2.
@ k_ra8_etha_off_eatdqac
EATDQAC: TX queue arbitration.
@ k_ra8_etha_off_eaeid0
EAEID0: error IRQ disable 0.
@ k_ra8_etha_off_eavtc
EAVTC: VLAN tag config.
@ k_ra8_etha_off_eafsecn
EAFSECN: frame size err.
@ k_ra8_etha_off_eatascstm1
EATASCSTM1: cycle start mon hi.
@ k_ra8_etha_off_eactdqm
EACTDQM: cut-through queue mon.
@ k_ra8_etha_off_eactdqdc
EACTDQDC: cut-through depth.
@ k_ra8_etha_off_eams
EAMS: Mode Status.
@ k_ra8_etha_off_eacgsm
EACGSM: CBS gate state monitor.
@ k_ra8_etha_off_eatfecn
EATFECN: tag filter err.
@ k_ra8_etha_off_eacc
EACC: CBS configuration.
@ k_ra8_etha_off_eatasctenc
EATASCTENC: TAS cut-through cfg.
@ k_ra8_etha_off_eatpec
EATPEC: TX preemption cfg.
@ k_ra8_etha_off_eatdqmlm0
EATDQMLM0: max queue level.
@ k_ra8_etha_off_eatascstc1
EATASCSTC1: TAS cycle start hi.
@ k_ra8_etha_off_eacoem
EACOEM: CBS oper enable mon.
@ k_ra8_etha_off_eatascstm0
EATASCSTM0: cycle start mon lo.
@ k_ra8_etha_off_eatdqc
EATDQC: TX queue control.
@ k_ra8_etha_off_eacoivm0
EACOIVM0: CBS oper increment.
@ k_ra8_etha_off_eatasctc
EATASCTC: TAS cycle time cfg.
@ k_ra8_etha_off_eatasglr
EATASGLR: TAS gate learn result.
@ k_ra8_etha_off_eairc
EAIRC: IPV remap.
@ k_ra8_etha_off_eatashcc
EATASHCC: TAS HW calibration.
@ k_ra8_etha_off_eatasgr
EATASGR: TAS gate read.
@ k_ra8_etha_off_eatasgrr
EATASGRR: TAS gate read result.
@ k_ra8_etha_off_eadqsecn
EADQSECN: queue security err.
@ k_ra8_etha_off_eatasigsc
EATASIGSC: TAS init gate state.
@ k_ra8_etha_off_eaeid1
EAEID1: error IRQ disable 1.
@ k_ra8_etha_off_eatasctm
EATASCTM: TAS cycle time mon.
@ k_ra8_etha_off_eatdqsc
EATDQSC: TX queue security.
@ k_ra8_etha_off_eaeis2
EAEIS2: error IRQ status 2.
@ k_ra8_etha_off_eatasc
EATASC: TAS configuration.
@ k_ra8_etha_off_eausmfsecn
EAUSMFSECN: under-min FS err.
@ k_ra8_etha_off_eatdqdc0
EATDQDC0: per-class queue cfg.
@ k_ra8_etha_off_eatdqm0
EATDQM0: per-class queue mon.
@ k_ra8_etha_off_eacaec
EACAEC: CBS admin enable.
@ k_ra8_etha_off_eavcc
EAVCC: VLAN control.
@ k_ra8_etha_off_eartfc
EARTFC: RX tag filter cfg.
@ k_ra8_etha_off_eatasgl1
EATASGL1: TAS gate learn 1.
@ k_ra8_etha_off_eamc
EAMC: Mode Configuration.
@ k_ra8_etha_off_eaeid2
EAEID2: error IRQ disable 2.
@ k_ra8_etha_off_eatasgl0
EATASGL0: TAS gate learn 0.
@ k_ra8_etha_off_eatasrirm
EATASRIRM: TAS RAM init monitor.
@ k_ra8_etha_off_eatasctenm
EATASCTENM: TAS cut-through mon.
@ k_ra8_etha_off_eaeis1
EAEIS1: error IRQ status 1.
@ k_ra8_etha_off_eaeis0
EAEIS0: error IRQ status 0.
@ k_ra8_etha_off_eacoulm0
EACOULM0: CBS oper upper limit.
@ k_ra8_etha_off_eactdqmlm
EACTDQMLM: cut-through peak.
@ k_ra8_etha_off_eatascstc0
EATASCSTC0: TAS cycle start lo.
@ k_ra8_etha_off_eatasenc0
EATASENC0: TAS entry-number cfg.
ra8_etha_mask_t
ETHA bit masks for EAMC / EAMS / per-class fields.
@ k_ra8_etha_mask_tas_cycle
EATASCTC TASACT 32-bit.
@ k_ra8_etha_mask_civ
EACAIVCq.CIV[19:0].
@ k_ra8_etha_mask_cul
EACAULCq.CUL[30:0].
@ k_ra8_etha_mask_tas_jit
EATASHCC.TASJ[15:0].
@ k_ra8_etha_mask_tas_gal
EATASGL0.TASGAL[7:0].
@ k_ra8_etha_mask_vlan_dei
EAVTC DEI 1-bit field.
@ k_ra8_etha_mask_ctqd
EACTQC.CTQD[15:0].
@ k_ra8_etha_mask_tas_igs
EATASIGSC.TASIGS7..0.
@ k_ra8_etha_mask_tas_gtl
EATASGL1.TASGTL[27:0].
@ k_ra8_etha_mask_ctdqd
EACTDQDC.CTDQD[3:0].
@ k_ra8_etha_mask_vlan_vid
EAVTC VID 12-bit field.
@ k_ra8_etha_mask_vlan_pcp
EAVTC PCP 3-bit field.
@ k_ra8_etha_mask_opc
EAMC.OPC[1:0].
@ k_ra8_etha_mask_dqd
EATDQDCq.DQD[10:0].
@ k_ra8_etha_mask_mfs
EATMFSCq.MFS[15:0].
@ k_ra8_etha_mask_ops
EAMS.OPS[1:0].
@ k_ra8_etha_mask_ipv
EAIRC.IPVRq[2:0].
@ k_ra8_etha_mask_tc
Per-TC byte mask.
@ k_ra8_etha_mask_ctqdn
EACTDQM.CTQDN[9:0].
@ k_ra8_etha_mask_dnq
EATDQMq.DNQ[10:0].
@ k_ra8_etha_mask_aen
EATASENC.TASAEN[8:0].
@ k_ra8_etha_mask_tdqa
EATDQAC.TDQAq[3:0].
ra8_etha_eaeis0_bits_t
Selected EAEIS0 status flags exposed for tests / IRQ dispatch.
@ k_ra8_etha_eaeis0_tfes
Tag-filter error.
@ k_ra8_etha_eaeis0_fses_mask
Per-class frame size err.
@ k_ra8_etha_eaeis0_l23ueecces
L2/3 unrecoverable ECC.
@ k_ra8_etha_eaeis0_tasctgees
TAS cut-through gate.
@ k_ra8_etha_eaeis0_decces
Descriptor ECC error.
@ k_ra8_etha_eaeis0_tasgees_mask
TAS gate-event error.
@ k_ra8_etha_eaeis0_usmfses
Switch min frame size err.
@ k_ra8_etha_eaeis0_dsecces
Descriptor security ECC.
@ k_ra8_etha_eaeis0_tecces
Transmit data ECC error.
@ k_ra8_etha_eaeis0_pecces
Per-class ECC error.
ra8_etha_vem_t
EAVCC.VEM[2:0] VLAN extraction mode.
@ k_ra8_etha_vem_strip_inner
Strip inner (C-VLAN) tag on RX.
@ k_ra8_etha_vem_swap
Swap inner / outer tags on RX.
@ k_ra8_etha_vem_strip_both
Strip both S- and C-VLAN tags.
@ k_ra8_etha_vem_none
Pass through unchanged.
@ k_ra8_etha_vem_strip_outer
Strip outer (S-VLAN) tag on RX.
Ethernet controller base addresses for the Renesas RA8D2.
@ k_ra8_etha0_base_addr
RA8 etha0 base address.
@ k_ra8_etha1_base_addr
RA8 etha1 base address.
Full ETHA per-port register window (HUM Ch 32, FSP R_ETHA0_Type).
volatile uint32_t EARTFC
+0x0138 RX tag filter configuration.
volatile uint32_t reserved24[k_ra8_etha_rsv_words_eatpec_to_eatmfsc]
+0x0024..0x003F Reserved.
volatile uint32_t EATASENC[8]
+0x0320..0x033F TAS entry-num cfg.
volatile uint32_t EAMC
+0x0000 Mode command.
volatile uint32_t EACTQC
+0x0100 Cut-through queue config.
volatile uint32_t EATASGLR
+0x03C8 TAS gate learn result.
volatile uint32_t EATASGR
+0x03D0 TAS gate read.
volatile uint32_t EATASCTC
+0x03B0 TAS cycle time configuration.
volatile uint32_t EACAULC[8]
+0x0240..0x025F CBS admin upper lim.
volatile uint32_t EACC
+0x0204 CBS configuration.
volatile uint32_t EATASIGSC
+0x0304 TAS initial gate state cfg.
volatile uint32_t reserved414[k_ra8_etha_rsv_words_eadqsecn_to_eaeis]
+0x0414..0x04FF Reserved.
volatile uint32_t EAFSECN
+0x0408 Frame size error counter.
volatile uint32_t EACGSM
+0x02C0 CBS gate state monitor.
volatile uint32_t EATASHCC
+0x03E0 TAS hardware calibration cfg.
volatile uint32_t EATASGL0
+0x03C0 TAS gate learn 0.
volatile uint32_t EATDQAC
+0x001C TX desc queue arbitration.
volatile uint32_t reserved384[k_ra8_etha_rsv_words_eatasctenm_gap]
+0x0384..0x039F Reserved.
volatile uint32_t reserved2C4[k_ra8_etha_rsv_words_eacgsm_to_eatasc]
+0x02C4..0x02FF Reserved.
volatile uint32_t EAIRC
+0x0010 IPV remap (8x 3-bit fields).
volatile uint32_t EATDQM[8]
+0x0080..0x009F Per-class queue mon.
volatile uint32_t EATASCSTC0
+0x03A0 TAS cycle start time cfg lo.
volatile uint32_t EAUSMFSECN
+0x0400 Switch min frame size err cnt.
volatile uint32_t EADQSECN
+0x0410 Queue security error counter.
volatile uint32_t EATASGL1
+0x03C4 TAS gate learn 1.
volatile uint32_t reserved208[6]
+0x0208..0x021F Reserved.
volatile uint32_t EAEID1
+0x0518 Error interrupt disable 1.
volatile uint32_t EATASCSTM0
+0x03A8 TAS cycle start time mon lo.
volatile uint32_t reserved3D8[2]
+0x03D8..0x03DF Reserved.
volatile uint32_t EACTDQMLM
+0x010C Cut-through max queue level.
volatile uint32_t reserved308[6]
+0x0308..0x031F Reserved.
volatile uint32_t reserved0C
+0x000C Reserved.
volatile uint32_t EAEIE0
+0x0504 Error interrupt enable 0.
volatile uint32_t reserved3EC[k_ra8_etha_rsv_words_eatassm_to_eausm]
+0x03EC..0x03FF Reserved.
volatile uint32_t EACTDQDC
+0x0104 Cut-through queue depth.
volatile uint32_t EATDQMLM[8]
+0x00A0..0x00BF Per-class peak level.
volatile uint32_t reserved264[k_ra8_etha_rsv_words_eacoem_to_eacoivm]
+0x0264..0x027F Reserved.
volatile uint32_t EATDQC
+0x0018 TX desc queue control.
volatile uint32_t EADQOECN
+0x040C Queue overflow error counter.
volatile uint32_t reserved344[k_ra8_etha_rsv_words_eatasctenc_gap]
+0x0344..0x035F Reserved.
volatile uint32_t EACTDQM
+0x0108 Cut-through queue monitor.
volatile uint32_t EAEIE2
+0x0524 Error interrupt enable 2.
volatile uint32_t EAVTC
+0x0134 VLAN tag (C+S) configuration.
volatile uint32_t EAVCC
+0x0130 VLAN control configuration.
volatile uint32_t EATASCTM
+0x03B4 TAS cycle time monitor.
volatile uint32_t reservedC0[16]
+0x00C0..0x00FF Reserved.
volatile uint32_t EATPEC
+0x0020 TX preemption config (802.3br).
volatile uint32_t EACAEC
+0x0200 CBS admin enable.
volatile uint32_t EAEIS0
+0x0500 Error interrupt status 0.
volatile uint32_t EATASCTENM
+0x0380 TAS cut-through entry mon.
volatile uint32_t EATDQDC[8]
+0x0060..0x007F Per-class queue depth.
volatile uint32_t EATFECN
+0x0404 Tag filter error counter.
volatile uint32_t EATASENM[8]
+0x0360..0x037F TAS entry-number mon.
volatile uint32_t reserved3B8[2]
+0x03B8..0x03BF Reserved.
volatile uint32_t EATASCSTM1
+0x03AC TAS cycle start time mon hi.
volatile uint32_t EAEID0
+0x0508 Error interrupt disable 0.
volatile uint32_t reserved08
+0x0008 Reserved.
volatile uint32_t EACOULM[8]
+0x02A0..0x02BF CBS oper upper limit.
volatile uint32_t reserved110[8]
+0x0110..0x012F Reserved.
volatile uint32_t EATMFSC[8]
+0x0040..0x005F Per-class max frame.
volatile uint32_t EACOIVM[8]
+0x0280..0x029F CBS oper increment mon.
volatile uint32_t reserved3CC
+0x03CC Reserved.
volatile uint32_t EATASRIRM
+0x03E4 TAS RAM-init register monitor.
volatile uint32_t EAEIS2
+0x0520 Error interrupt status 2.
volatile uint32_t EACAIVC[8]
+0x0220..0x023F CBS admin increment.
volatile uint32_t EACOEM
+0x0260 CBS oper enable monitor.
volatile uint32_t EATASC
+0x0300 TAS configuration.
volatile uint32_t reserved13C[k_ra8_etha_rsv_words_eartfc_to_eacaec]
+0x013C..0x01FF Reserved.
volatile uint32_t EATASGRR
+0x03D4 TAS gate read result.
volatile uint32_t EATASCSTC1
+0x03A4 TAS cycle start time cfg hi.
volatile uint32_t EATASCTENC
+0x0340 TAS cut-through entry cfg.
volatile uint32_t EAMS
+0x0004 Mode status.
volatile uint32_t EATDQSC
+0x0014 TX desc queue security cfg.
volatile uint32_t EAEID2
+0x0528 Error interrupt disable 2.
volatile uint32_t reserved50C
+0x050C Reserved.
volatile uint32_t reserved51C
+0x051C Reserved.
volatile uint32_t EAEIS1
+0x0510 Error interrupt status 1.
volatile uint32_t EAEIE1
+0x0514 Error interrupt enable 1.
volatile uint32_t EATASSM
+0x03E8 TAS status monitor.