ra8_etha_stats.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_etha.h"
#include "ra8_etha_internal.h"
#include "ra8_etha_regs.h"
#include "ra8_log.h"

static const char* s_tag = "ETHA";

typedef enum : uint16_t {
  k_ra8_etha_ring_count_min = 1U,     
  k_ra8_etha_ring_count_max = 4096U,  
  k_ra8_etha_ring_buf_min   = 64U,    
  k_ra8_etha_ring_buf_max   = 16383U, 
} ra8_etha_ring_limits_t;

RA8_INTERNAL
static inline bool internal_ring_args_ok(uint16_t num_tx, uint16_t num_rx, uint16_t buffer_size)
{
  return (num_tx >= k_ra8_etha_ring_count_min) && (num_tx <= k_ra8_etha_ring_count_max) &&
         (num_rx >= k_ra8_etha_ring_count_min) && (num_rx <= k_ra8_etha_ring_count_max) &&
         (buffer_size >= k_ra8_etha_ring_buf_min) && (buffer_size <= k_ra8_etha_ring_buf_max);
}

RA8_INTERNAL
static inline uint32_t internal_sat_add_u32(uint32_t base, uint32_t inc)
{
  if (inc > (UINT32_MAX - base)) {
    return UINT32_MAX;
  }
  return base + inc;
}
 
ra8_err_t ra8_etha_descriptor_ring_init(ra8_etha_port_t channel,
                                        uint16_t        num_tx,
                                        uint16_t        num_rx,
                                        uint16_t        buffer_size)
{
  if (!internal_port_ok(channel)) {
    ra8_log_error(s_tag, "etha_descriptor_ring_init: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  if (!internal_ring_args_ok(num_tx, num_rx, buffer_size)) {
    ra8_log_error(s_tag, "etha_descriptor_ring_init: ring args out of range");
    return k_ra8_err_invalid_arg;
  }
  s_etha_slots[(uint8_t)channel].stats.ring_tx  = num_tx;
  s_etha_slots[(uint8_t)channel].stats.ring_rx  = num_rx;
  s_etha_slots[(uint8_t)channel].stats.ring_buf = buffer_size;
 
  /* Clamp every per-class TX queue depth to num_tx so the hardware
   * never schedules a class deeper than the host-side ring can hold.
   * EATDQDC is 11 bits (k_ra8_etha_mask_dqd = 0x7FF = 2047). */
  uint16_t depth = num_tx;
  if ((uint32_t)depth > k_ra8_etha_mask_dqd) {
    depth = (uint16_t)k_ra8_etha_mask_dqd;
  }
  volatile r_etha_regs_t* reg = ra8_etha(channel);
  for (uint8_t i = 0U; i < k_ra8_etha_tc_count; ++i) {
    /* HUM Ch 32.3.2.7 "EATDQDCq" p 1636 */
    reg->EATDQDC[i] = (uint32_t)depth & k_ra8_etha_mask_dqd;
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_get_stats(ra8_etha_port_t channel, ra8_etha_port_stats_t* out_stats)
{
  RA8_CHECK_NULL_PTR(out_stats, s_tag, "etha_get_stats: out_stats null");
  if (!internal_port_ok(channel)) {
    ra8_log_error(s_tag, "etha_get_stats: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  *out_stats = s_etha_slots[(uint8_t)channel].stats;
  return k_ra8_ok;
}
 
ra8_err_t ra8_etha_account_traffic(ra8_etha_port_t channel,
                                   uint32_t        tx_ok,
                                   uint32_t        tx_err,
                                   uint32_t        rx_ok,
                                   uint32_t        rx_err,
                                   uint32_t        rx_drop)
{
  if (!internal_port_ok(channel)) {
    ra8_log_error(s_tag, "etha_account_traffic: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  ra8_etha_port_stats_t* st = &s_etha_slots[(uint8_t)channel].stats;
  st->tx_ok                 = internal_sat_add_u32(st->tx_ok, tx_ok);
  st->tx_err                = internal_sat_add_u32(st->tx_err, tx_err);
  st->rx_ok                 = internal_sat_add_u32(st->rx_ok, rx_ok);
  st->rx_err                = internal_sat_add_u32(st->rx_err, rx_err);
  st->rx_drop               = internal_sat_add_u32(st->rx_drop, rx_drop);
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_etha_to_operation(ra8_etha_port_t channel)
{
  enum : uint32_t { k_ra8_etha_mode_spin = 200000U  };
  /* HUM Ch 32.3.1.1 "EAMC : Mode Command Register" p 1631 +
   * HUM Ch 32.3.1.2 "EAMS : Mode Status Register" p 1631 */
  volatile r_etha_regs_t* reg = ra8_etha(channel);
  reg->EAMC                   = (uint32_t)k_ra8_etha_opc_operation;
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_etha_mode_spin; ++i) {
    if ((reg->EAMS & k_ra8_etha_mask_ops) == (uint32_t)k_ra8_etha_opc_operation) {
      return k_ra8_ok;
    }
  }
  ra8_log_error(s_tag, "etha_to_operation: EAMS never reached OPERATION");
  return k_ra8_err_hw_timeout;
}
 
ra8_err_t ra8_etha_open(ra8_etha_port_t            channel,
                        const ra8_etha_phy_open_t* phy,
                        ra8_rmac_phy_link_t*       out_link)
{
  RA8_CHECK_NULL_PTR(phy, s_tag, "etha_open: phy null");
  RA8_CHECK_NULL_PTR(out_link, s_tag, "etha_open: out_link null");
  if (!internal_port_ok(channel)) {
    ra8_log_error(s_tag, "etha_open: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  /* Map ETHA channel index 1:1 onto the corresponding RMAC port. */
  const ra8_rmac_port_t rmac_port = (ra8_rmac_port_t)(uint8_t)channel;
 
  const ra8_err_t op_err = internal_etha_to_operation(channel);
  if (op_err != k_ra8_ok) {
    return op_err;
  }
 
  /* Each PHY step below is an MDIO transaction pair (drain + post-wait)
   * polling the RMAC MPSM register. On the host unit-test build those
   * waits consult the ra8_fake_mmio seam, so each error leg is reached by
   * failing the matching MPSM wait-loop (fail_wait / fail_nth_wait). */
  ra8_err_t err = ra8_rmac_phy_reset(rmac_port, phy->phy_addr);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_open: phy_reset");
    return err;
  }
  err = ra8_rmac_phy_set_advertise(rmac_port, phy->phy_addr, phy->advertise);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_open: set_advertise");
    return err;
  }
  err = ra8_rmac_phy_auto_neg_start(rmac_port, phy->phy_addr);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "etha_open: auto_neg_start");
    return err;
  }
  return ra8_rmac_phy_auto_neg_wait(rmac_port, phy->phy_addr, phy->timeout_ms, out_link);
}