ra8_eth_gwca_default.c

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#include <stdint.h>
#include <string.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_eth_gwca.h"
#include "ra8_eth_gwca_internal.h"
#include "ra8_ether_regs.h"
#include "ra8_hw_err.h"
#include "ra8_hw_intrinsics.h"
#include "ra8_log.h"
 
static const char* s_tag = "ETHGWC";

RA8_INTERNAL
static uint32_t internal_decode_ds(const ra8_gwca_basic_descriptor_t* desc)
{
  enum : uint32_t {
    k_ra8_ds_low_mask   = 0xFFU, 
    k_ra8_ds_high_shift = 8U,    
    k_ra8_ds_high_mask  = 0xFU,  
  };
  return ((uint32_t)desc->ds_l & k_ra8_ds_low_mask) |
         (((uint32_t)desc->ds_h & k_ra8_ds_high_mask) << k_ra8_ds_high_shift);
}

RA8_INTERNAL
static ra8_err_t internal_drain_rx_slot(ra8_gwca_basic_descriptor_t* desc,
                                        uint8_t*                     out_frame,
                                        uint32_t                     out_capacity,
                                        uint32_t                     slot_bytes,
                                        uint32_t*                    out_len)
{
  const uint8_t* const buf      = priv_ra8_eth_gwca_decode_ptr(desc);
  const uint32_t       frame_ds = internal_decode_ds(desc);
  if (buf == nullptr || frame_ds > out_capacity) {
    return k_ra8_err_invalid_arg;
  }
  (void)memcpy(out_frame, buf, (size_t)frame_ds);
  *out_len = frame_ds;
  enum : uint32_t {
    k_ra8_ds_byte_mask  = 0xFFU, 
    k_ra8_ds_high_shift = 8U,    
    k_ra8_ds_high_mask  = 0xFU,  
  };
  desc->ds_l = (uint8_t)(slot_bytes & k_ra8_ds_byte_mask);
  desc->ds_h = (uint8_t)((slot_bytes >> k_ra8_ds_high_shift) & k_ra8_ds_high_mask);
  desc->dt   = (uint8_t)k_ra8_gwdcc_dt_fempty;
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_tx_ext_init(ra8_gwca_ext_descriptor_t* chain,
                                      uint32_t                   depth,
                                      uint32_t                   slot_bytes,
                                      const uint8_t*             pool)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "tx_ext_init: chain null");
  RA8_CHECK_NULL_PTR(pool, s_tag, "tx_ext_init: pool null");
  enum : uint32_t {
    k_tx_ext_min_depth = 2U,    
    k_tx_ext_max_bytes = 2048U, 
    k_ds_low_mask      = 0xFFU, 
    k_ds_high_shift    = 8U,    
    k_ds_high_mask     = 0xFU,  
  };
  if (depth < k_tx_ext_min_depth) {
    return k_ra8_err_invalid_arg;
  }
  if (slot_bytes > k_tx_ext_max_bytes) {
    return k_ra8_err_invalid_arg;
  }
  enum : uintptr_t {
    k_ptr_hi_shift = 32U,     
    k_ptr_hi_mask  = 0xFFULL, 
  };
  for (uint32_t i = 0U; i < (depth - 1U); ++i) {
    (void)memset(&chain[i], 0, sizeof(ra8_gwca_ext_descriptor_t));
    chain[i].dt         = (uint8_t)k_ra8_gwdcc_dt_fempty;
    chain[i].ds_l       = (uint8_t)(slot_bytes & k_ds_low_mask);
    chain[i].ds_h       = (uint8_t)((slot_bytes >> k_ds_high_shift) & k_ds_high_mask);
    const uintptr_t buf = (uintptr_t)pool + ((uintptr_t)i * (uintptr_t)slot_bytes);
    chain[i].ptr_h      = (uint8_t)(((uint64_t)buf >> k_ptr_hi_shift) & (uint64_t)k_ptr_hi_mask);
    chain[i].ptr_l      = (uint32_t)buf;
  }
  ra8_gwca_ext_descriptor_t* const term = &chain[depth - 1U];
  (void)memset(term, 0, sizeof(ra8_gwca_ext_descriptor_t));
  const uintptr_t head = (uintptr_t)&chain[0];
  term->ptr_h          = (uint8_t)(((uint64_t)head >> k_ptr_hi_shift) & (uint64_t)k_ptr_hi_mask);
  term->ptr_l          = (uint32_t)head;
  term->dt             = (uint8_t)k_ra8_gwdcc_dt_link;
  return k_ra8_ok;
}

RA8_INTERNAL
static void
internal_tx_ext_rearm(ra8_gwca_ext_descriptor_t* chain, uint32_t depth, uint32_t queue_index)
{
  ra8_gwca_ext_descriptor_t* const term = &chain[depth - 1U];
  if (term->dt != (uint8_t)k_ra8_gwdcc_dt_lempty) {
    return;
  }
  enum : uintptr_t {
    k_ptr_hi_shift = 32U,     
    k_ptr_hi_mask  = 0xFFULL, 
  };
  const uintptr_t head = (uintptr_t)&chain[0];
  term->ptr_h          = (uint8_t)(((uint64_t)head >> k_ptr_hi_shift) & (uint64_t)k_ptr_hi_mask);
  term->ptr_l          = (uint32_t)head;
  term->dt             = (uint8_t)k_ra8_gwdcc_dt_link;
  (void)ra8_eth_gwca_reload_queue(queue_index);
}

RA8_INTERNAL
static ra8_err_t internal_default_open_rings(ra8_eth_gwca_default_state_t* state)
{
  ra8_err_t err = ra8_eth_gwca_init_ring(state->rx_chain, state->rx_depth, state->rx_slot_bytes);
  RA8_RETURN_ON_ERROR(err, s_tag, "default_open: rx init_ring");
  err = ra8_eth_gwca_attach_buffers(state->rx_chain,
                                    state->rx_depth,
                                    state->rx_slot_bytes,
                                    state->rx_pool);
  RA8_RETURN_ON_ERROR(err, s_tag, "default_open: rx attach");
  return internal_tx_ext_init(state->tx_chain,
                              state->tx_depth,
                              state->tx_slot_bytes,
                              state->tx_pool);
}

RA8_INTERNAL
static ra8_err_t internal_default_open_queues(ra8_eth_gwca_default_state_t* state)
{
  const ra8_eth_gwca_queue_cfg_t rx_cfg = {.priority     = 0U,
                                           .is_tx        = false,
                                           .stop_on_last = false,
                                           .chain_head   = state->rx_chain};
  ra8_err_t                      err =
    ra8_eth_gwca_configure_queue(state->linkfix_table, state->rx_queue_index, &rx_cfg);
  RA8_RETURN_ON_ERROR(err, s_tag, "default_open: rx config");
  const ra8_eth_gwca_queue_cfg_t tx_cfg = {.priority     = 0U,
                                           .is_tx        = true,
                                           .stop_on_last = false,
                                           .extended     = true,
                                           .chain_head   = state->tx_chain};
  return ra8_eth_gwca_configure_queue(state->linkfix_table, state->tx_queue_index, &tx_cfg);
}

RA8_INTERNAL
static ra8_err_t internal_default_open_pre(ra8_eth_gwca_default_state_t* state)
{
  g_ra8_eth_gwca_pre_step = 0U;
  ra8_err_t err           = ra8_eth_gwca_init();
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_fail_1;
    return err;
  }
  g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_ok_1;
  err                     = internal_default_open_rings(state);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_fail_2;
    return err;
  }
  g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_ok_2;
  err                     = ra8_eth_gwca_bring_up(state->linkfix_table, state->linkfix_count);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_fail_3;
    return err;
  }
  g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_ok_3;
  const ra8_err_t cfg_err = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_config);
  if (cfg_err != k_ra8_ok) {
    g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_fail_4;
    return cfg_err;
  }
  g_ra8_eth_gwca_pre_step = (uint32_t)k_ra8_eth_gwca_step_ok_4;
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_default_open(ra8_eth_gwca_default_state_t* state)
{
  RA8_CHECK_NULL_PTR(state, s_tag, "default_open: state null");
  g_ra8_eth_gwca_open_step = 0U;
  ra8_err_t err            = internal_default_open_pre(state);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_fail_1;
    return err;
  }
  g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_ok_1;
  err                      = internal_default_open_queues(state);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_fail_2;
    return err;
  }
  g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_ok_2;
  state->rx_head           = 0U;
  state->tx_tail           = 0U;
  const ra8_err_t op_err   = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_operation);
  if (op_err != k_ra8_ok) {
    g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_fail_3;
    return op_err;
  }
  g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_ok_3;
 
  /* Arm both queues now the GWCA is in OPERATION: BALR loads the
   * chain base into the AXI address RAM so the GWCA starts scanning
   * the descriptor chains (HUM Ch 34.3 "GWDCCi"). */
  const ra8_err_t rx_reload = ra8_eth_gwca_reload_queue(state->rx_queue_index);
  if (rx_reload != k_ra8_ok) {
    g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_fail_3;
    return rx_reload;
  }
  const ra8_err_t tx_reload = ra8_eth_gwca_reload_queue(state->tx_queue_index);
  if (tx_reload != k_ra8_ok) {
    g_ra8_eth_gwca_open_step = (uint32_t)k_ra8_eth_gwca_step_fail_3;
    return tx_reload;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static void internal_rearm_queue_if_disabled(ra8_gwca_basic_descriptor_t* chain,
                                             uint32_t                     ring_depth,
                                             uint32_t                     queue_index,
                                             uint32_t*                    cursor)
{
  ra8_gwca_basic_descriptor_t* const term = &chain[ring_depth - 1U];
  if (term->dt != (uint8_t)k_ra8_gwdcc_dt_lempty) {
    return;
  }
  /* Restore the LINK terminator (PTR -> chain[0], dt = LINK), reload
   * the queue so the GWCA resumes from the chain base, and snap the
   * software cursor to 0 so it tracks the GWCA's reset scan position. */
  priv_ra8_eth_gwca_set_linkfix_entry(term, &chain[0]);
  term->dt = (uint8_t)k_ra8_gwdcc_dt_link;
  *cursor  = 0U;
  (void)ra8_eth_gwca_reload_queue(queue_index);
}

RA8_INTERNAL
static uint32_t internal_tx_info1_hi(uint8_t mac_port)
{
  const uint32_t dv = (uint32_t)1U << (uint32_t)mac_port;
  return ((dv << (uint32_t)k_ra8_gwca_info1_tx_dv_shift) & (uint32_t)k_ra8_gwca_info1_tx_dv_mask);
}

RA8_INTERNAL
static ra8_err_t internal_wait_tx0_done(ra8_eth_gwca_default_state_t* state)
{
  for (uint32_t i = 0U; i < k_ra8_eth_gwca_tx_done_spin; ++i) {
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    if (ra8_fake_mmio_wait_eval(&state->tx_chain[0],
                                i,
                                (state->tx_chain[0].dt != (uint8_t)k_ra8_gwdcc_dt_fsingle))) {
      return k_ra8_ok;
    }
#else
    if (state->tx_chain[0].dt != (uint8_t)k_ra8_gwdcc_dt_fsingle) {
      return k_ra8_ok;
    }
#endif
  }
  ra8_log_error(s_tag, "default_send: TX completion timeout");
  return k_ra8_err_hw_timeout;
}

ra8_err_t
ra8_eth_gwca_default_send(ra8_eth_gwca_default_state_t* state, const uint8_t* frame, uint32_t len)
{
  RA8_CHECK_NULL_PTR(state, s_tag, "default_send: state null");
  RA8_CHECK_NULL_PTR(frame, s_tag, "default_send: frame null");
  if (len == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (len > state->tx_slot_bytes) {
    return k_ra8_err_invalid_arg;
  }
  /* Re-arm if the GWCA idle-disabled the queue, then fill slot 0. */
  internal_tx_ext_rearm(state->tx_chain, state->tx_depth, state->tx_queue_index);
  enum : uint32_t {
    k_ds_low_mask   = 0xFFU, 
    k_ds_high_shift = 8U,    
    k_ds_high_mask  = 0xFU,  
  };
  ra8_gwca_ext_descriptor_t* const d = &state->tx_chain[0];
  (void)memcpy(state->tx_pool, frame, (size_t)len);
  d->ds_l        = (uint8_t)(len & k_ds_low_mask);
  d->ds_h        = (uint8_t)((len >> k_ds_high_shift) & k_ds_high_mask);
  d->info1_lo    = (uint32_t)k_ra8_gwca_info1_tx_fmt_direct;
  d->info1_hi    = internal_tx_info1_hi(state->mac_port);
  d->dt          = (uint8_t)k_ra8_gwdcc_dt_fsingle;
  state->tx_tail = 0U;
  /* DSB: the descriptor + frame buffer are Normal (SRAM) writes; the
   * GWCA kick below is a Device write. Armv8-M does not order them
   * without an explicit barrier (host no-op via the ra8_hw_intrinsics seam). */
  ra8_hw_dsb();
  const ra8_err_t reload_err = ra8_eth_gwca_reload_queue(state->tx_queue_index);
  if (reload_err != k_ra8_ok) {
    return reload_err;
  }
  const ra8_err_t kick_err = ra8_eth_gwca_kick_tx(state->tx_queue_index);
  if (kick_err != k_ra8_ok) {
    return kick_err;
  }
  /* Block until the GWCA writes slot 0 back (FSINGLE -> FEMPTY) or the spin
   * budget is exhausted; extracted so this send stays under the complexity cap. */
  return internal_wait_tx0_done(state);
}

ra8_err_t ra8_eth_gwca_default_recv(ra8_eth_gwca_default_state_t* state,
                                    uint8_t*                      out_frame,
                                    uint32_t                      out_capacity,
                                    uint32_t*                     out_len)
{
  RA8_CHECK_NULL_PTR(state, s_tag, "default_recv: state null");
  const ra8_err_t err = ra8_eth_gwca_rx_frame(state->rx_chain,
                                              state->rx_depth,
                                              &state->rx_head,
                                              out_frame,
                                              out_capacity,
                                              state->rx_slot_bytes,
                                              out_len);
  if (err == k_ra8_err_no_data) {
    internal_rearm_queue_if_disabled(state->rx_chain,
                                     state->rx_depth,
                                     state->rx_queue_index,
                                     &state->rx_head);
  }
  return err;
}

ra8_err_t ra8_eth_gwca_rx_frame(ra8_gwca_basic_descriptor_t* chain,
                                uint32_t                     ring_depth,
                                uint32_t*                    head_idx,
                                uint8_t*                     out_frame,
                                uint32_t                     out_capacity,
                                uint32_t                     slot_bytes,
                                uint32_t*                    out_len)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "rx_frame: chain null");
  RA8_CHECK_NULL_PTR(head_idx, s_tag, "rx_frame: head_idx null");
  RA8_CHECK_NULL_PTR(out_frame, s_tag, "rx_frame: out_frame null");
  RA8_CHECK_NULL_PTR(out_len, s_tag, "rx_frame: out_len null");
  if (out_capacity == 0U) {
    return k_ra8_err_invalid_arg;
  }
  uint32_t        slot = 0U;
  const ra8_err_t err  = ra8_eth_gwca_find_slot(chain,
                                                ring_depth,
                                                k_ra8_gwdcc_dt_fsingle,
                                                *head_idx % (ring_depth - 1U),
                                                &slot);
  if (err != k_ra8_ok) {
    return err;
  }
  const ra8_err_t drain_err =
    internal_drain_rx_slot(&chain[slot], out_frame, out_capacity, slot_bytes, out_len);
  if (drain_err != k_ra8_ok) {
    return drain_err;
  }
  *head_idx = (slot + 1U) % (ring_depth - 1U);
  return k_ra8_ok;
}