ra8_eth_gwca_queue.c

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#include <stdint.h>
#include <string.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_eth_gwca.h"
#include "ra8_eth_gwca_internal.h"
#include "ra8_ether_regs.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
 
static const char* s_tag = "ETHGWC";

RA8_INTERNAL
static uint32_t internal_compose_gwdcc(const ra8_eth_gwca_queue_cfg_t* cfg)
{
  /* GWDCC value: DQT + DCP[18:16] + SL + EDE. SM[1:0] stays 00b
   * (Normal mode -- full descriptor write-back). ETS stays 0, BALR
   * stays 0 (default AXI burst), OSID 0. EDE = 1 when the queue uses
   * 16-byte extended descriptors (the TX path). */
  uint32_t value = 0U;
  if (cfg->is_tx) {
    value |= (uint32_t)k_ra8_gwdcc_dqt;
  }
  if (cfg->stop_on_last) {
    value |= (uint32_t)k_ra8_gwdcc_sl;
  }
  if (cfg->extended) {
    value |= (uint32_t)k_ra8_gwdcc_ede;
  }
  value |= (((uint32_t)cfg->priority << k_ra8_gwdcc_dcp_shift) & k_ra8_gwdcc_dcp_mask);
  return value;
}
 
void priv_ra8_eth_gwca_set_linkfix_entry(ra8_gwca_basic_descriptor_t* entry, const void* chain_head)
{
  enum : uintptr_t {
    k_ra8_linkfix_ptr_upper_shift = 32U,           
    k_ra8_linkfix_ptr_upper_mask  = 0xFFULL,       
    k_ra8_linkfix_ptr_lower_mask  = 0xFFFFFFFFULL, 
  };
  const uintptr_t head_addr = (uintptr_t)chain_head;
  entry->dt                 = (uint8_t)k_ra8_gwdcc_dt_linkfix;
  entry->ptr_h =
    (uint8_t)((uint64_t)head_addr >> k_ra8_linkfix_ptr_upper_shift) & k_ra8_linkfix_ptr_upper_mask;
  entry->ptr_l = (uint32_t)head_addr & k_ra8_linkfix_ptr_lower_mask;
}

ra8_err_t ra8_eth_gwca_configure_queue(ra8_gwca_basic_descriptor_t*    linkfix_table,
                                       uint32_t                        queue_index,
                                       const ra8_eth_gwca_queue_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(linkfix_table, s_tag, "configure_queue: table null");
  RA8_CHECK_NULL_PTR(cfg, s_tag, "configure_queue: cfg null");
  RA8_CHECK_NULL_PTR(cfg->chain_head, s_tag, "configure_queue: chain_head null");
  enum : uint8_t {
    k_ra8_gwdcc_dcp_max = 7U, 
  };
  if (cfg->priority > k_ra8_gwdcc_dcp_max) {
    return k_ra8_err_invalid_arg;
  }
  volatile uint32_t* const gwdcc = ra8_gwca_gwdcc(queue_index);
  if (gwdcc == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  *gwdcc = internal_compose_gwdcc(cfg);
  priv_ra8_eth_gwca_set_linkfix_entry(&linkfix_table[queue_index], cfg->chain_head);
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_reload_queue(uint32_t queue_index)
{
  volatile uint32_t* const gwdcc = ra8_gwca_gwdcc(queue_index);
  if (gwdcc == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 34.3 "GWDCCi" p 1811: BALR self-clears once the GWCA has
   * reset the AXI address RAM current_address pointer. */
  *gwdcc |= (uint32_t)k_ra8_gwdcc_balr;
  const ra8_err_t err =
    ra8_hw_wait_flag_clear32(gwdcc, (uint32_t)k_ra8_gwdcc_balr, (uint32_t)k_ra8_eth_gwca_balr_spin);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "reload_queue: GWDCC BALR never cleared");
  }
  return err;
}

ra8_err_t
ra8_eth_gwca_init_ring(ra8_gwca_basic_descriptor_t* chain, uint32_t ring_depth, uint32_t slot_bytes)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "init_ring: chain null");
  enum : uint32_t {
    k_ra8_gwca_ring_min_depth = 2U,    
    k_ra8_gwca_ring_max_bytes = 2048U, 
  };
  if (ring_depth < k_ra8_gwca_ring_min_depth || slot_bytes > k_ra8_gwca_ring_max_bytes) {
    return k_ra8_err_invalid_arg;
  }
 
  /* FEMPTY data slots: ds carries the buffer size, dt = FEMPTY. */
  enum : uint32_t {
    k_ra8_ds_byte_mask  = 0xFFU, 
    k_ra8_ds_high_shift = 8U,    
    k_ra8_ds_high_mask  = 0xFU,  
  };
  for (uint32_t i = 0U; i < (ring_depth - 1U); ++i) {
    (void)memset(&chain[i], 0, sizeof(ra8_gwca_basic_descriptor_t));
    chain[i].dt   = (uint8_t)k_ra8_gwdcc_dt_fempty;
    chain[i].ds_l = (uint8_t)(slot_bytes & k_ra8_ds_byte_mask);
    chain[i].ds_h = (uint8_t)((slot_bytes >> k_ra8_ds_high_shift) & k_ra8_ds_high_mask);
    /* ptr_l left at 0 -- caller fills in the per-slot buffer address. */
  }
 
  /* Last entry: LINK back to chain[0] so the chip wraps. */
  priv_ra8_eth_gwca_set_linkfix_entry(&chain[ring_depth - 1U], &chain[0]);
  /* Override dt: priv_ra8_eth_gwca_set_linkfix_entry writes LINKFIX, but for
   * mid-chain wrap we want LINK (interchangeable per HUM Ch
   * 34.5.1.3.2; LINK is the standard chain-continuation type). */
  chain[ring_depth - 1U].dt = (uint8_t)k_ra8_gwdcc_dt_link;
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_set_descriptor_buffer(ra8_gwca_basic_descriptor_t* desc, void* buffer)
{
  RA8_CHECK_NULL_PTR(desc, s_tag, "set_descriptor_buffer: desc null");
  enum : uintptr_t {
    k_ra8_buf_ptr_upper_shift = 32U,           
    k_ra8_buf_ptr_upper_mask  = 0xFFULL,       
    k_ra8_buf_ptr_lower_mask  = 0xFFFFFFFFULL, 
  };
  const uintptr_t addr = (uintptr_t)buffer;
  desc->ptr_h = (uint8_t)((uint64_t)addr >> k_ra8_buf_ptr_upper_shift) & k_ra8_buf_ptr_upper_mask;
  desc->ptr_l = (uint32_t)addr & k_ra8_buf_ptr_lower_mask;
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_attach_buffers(ra8_gwca_basic_descriptor_t* chain,
                                      uint32_t                     ring_depth,
                                      uint32_t                     slot_bytes,
                                      uint8_t*                     pool)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "attach_buffers: chain null");
  RA8_CHECK_NULL_PTR(pool, s_tag, "attach_buffers: pool null");
  if (ring_depth < 2U || slot_bytes == 0U) {
    return k_ra8_err_invalid_arg;
  }
  for (uint32_t i = 0U; i < (ring_depth - 1U); ++i) {
    const size_t    slot_offset = (size_t)i * (size_t)slot_bytes;
    const ra8_err_t err         = ra8_eth_gwca_set_descriptor_buffer(&chain[i], &pool[slot_offset]);
    if (err != k_ra8_ok) {
      return err;
    }
  }
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_kick_tx(uint32_t queue_index)
{
  enum : uint32_t {
    k_ra8_gwca_max_tx_queues  = 64U, 
    k_ra8_gwca_queues_per_reg = 32U, 
  };
  if (queue_index >= k_ra8_gwca_max_tx_queues) {
    return k_ra8_err_invalid_arg;
  }
  const uintptr_t          offset = (queue_index < k_ra8_gwca_queues_per_reg)
                                      ? (uintptr_t)k_ra8_gwca_off_gwtrc0
                                      : (uintptr_t)k_ra8_gwca_off_gwtrc1;
  volatile uint32_t* const gwtrc  = (volatile uint32_t*)(k_ra8_gwca0_base_addr + offset);
  const uint32_t           bit    = 1U << (queue_index % k_ra8_gwca_queues_per_reg);
  *gwtrc                          = *gwtrc | bit;
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_find_slot(const ra8_gwca_basic_descriptor_t* chain,
                                 uint32_t                           ring_depth,
                                 ra8_gwdcc_dt_t                     match_dt,
                                 uint32_t                           start_idx,
                                 uint32_t*                          out_index)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "find_slot: chain null");
  RA8_CHECK_NULL_PTR(out_index, s_tag, "find_slot: out_index null");
  if (ring_depth < 2U) {
    return k_ra8_err_invalid_arg;
  }
  const uint32_t data_slot_count = ring_depth - 1U;
  if (start_idx >= data_slot_count) {
    return k_ra8_err_invalid_arg;
  }
  /* Walk from start_idx forward, wrapping once if needed. */
  for (uint32_t i = 0U; i < data_slot_count; ++i) {
    const uint32_t slot = (start_idx + i) % data_slot_count;
    if (chain[slot].dt == (uint8_t)match_dt) {
      *out_index = slot;
      return k_ra8_ok;
    }
  }
  return k_ra8_err_no_data;
}
 
uint8_t* priv_ra8_eth_gwca_decode_ptr(const ra8_gwca_basic_descriptor_t* desc)
{
  if (desc == nullptr) {
    return nullptr;
  }
  /* PTR is 40 bits across ptr_h (high 8) + ptr_l (low 32). On a
   * 32-bit target uintptr_t is 32 bits, so shifting by 32 is UB --
   * promote to uint64_t for the recompose, then back to uintptr_t.
   * On 32-bit chips ptr_h is always zero so the upper byte is
   * harmlessly truncated when we cast back. */
  enum : uint64_t {
    k_ra8_ptr_upper_shift = 32ULL,         
    k_ra8_ptr_low_mask    = 0xFFFFFFFFULL, 
  };
  const uint64_t addr64 =
    ((uint64_t)desc->ptr_h << k_ra8_ptr_upper_shift) | ((uint64_t)desc->ptr_l & k_ra8_ptr_low_mask);
  return (uint8_t*)(uintptr_t)addr64;
}

ra8_err_t ra8_eth_gwca_tx_frame(ra8_gwca_basic_descriptor_t* chain,
                                uint32_t                     ring_depth,
                                uint32_t*                    tail_idx,
                                const uint8_t*               frame,
                                uint32_t                     frame_len,
                                uint32_t                     slot_bytes)
{
  RA8_CHECK_NULL_PTR(chain, s_tag, "tx_frame: chain null");
  RA8_CHECK_NULL_PTR(tail_idx, s_tag, "tx_frame: tail_idx null");
  RA8_CHECK_NULL_PTR(frame, s_tag, "tx_frame: frame null");
  if (frame_len == 0U || frame_len > slot_bytes) {
    return k_ra8_err_invalid_arg;
  }
  uint32_t        slot = 0U;
  const ra8_err_t err  = ra8_eth_gwca_find_slot(chain,
                                                ring_depth,
                                                k_ra8_gwdcc_dt_fempty,
                                                *tail_idx % (ring_depth - 1U),
                                                &slot);
  if (err != k_ra8_ok) {
    return err;
  }
  uint8_t* const buf = priv_ra8_eth_gwca_decode_ptr(&chain[slot]);
  if (buf == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  (void)memcpy(buf, frame, (size_t)frame_len);
  enum : uint32_t {
    k_ra8_ds_low_byte_mask = 0xFFU, 
    k_ra8_ds_high_shift    = 8U,    
    k_ra8_ds_high_nibble   = 0xFU,  
  };
  chain[slot].ds_l = (uint8_t)(frame_len & k_ra8_ds_low_byte_mask);
  chain[slot].ds_h = (uint8_t)((frame_len >> k_ra8_ds_high_shift) & k_ra8_ds_high_nibble);
  chain[slot].dt   = (uint8_t)k_ra8_gwdcc_dt_fsingle;
  *tail_idx        = (slot + 1U) % (ring_depth - 1U);
  return k_ra8_ok;
}