ra8_eth_gwca.c

Go to the documentation of this file.

 
#include "ra8_eth_gwca.h"
 
#include <stdint.h>
#include <string.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_eth_gwca_internal.h"
#include "ra8_ether_regs.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
 
static const char* s_tag = "ETHGWC";
 
static ra8_eth_gwca_event_fn_t s_gwca_fn;
static void*                   s_gwca_ctx;

typedef enum : uint32_t {
  k_ra8_mfwd_off_fwpc10 = 0x104UL, 
  k_ra8_mfwd_off_fwpc11 = 0x114UL, 
  k_ra8_mfwd_off_fwpc12 = 0x124UL, 
  k_ra8_mfwd_fwpc_dde   = 0x1UL,   
} ra8_eth_gwca_init_layout_t;
 
ra8_err_t ra8_eth_gwca_init(void)
{
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C" p 446 */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_eswm);
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "gwca_init: mstp enable");
 
  volatile r_gwca_regs_t* reg = ra8_gwca();
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  reg->GWCA_CTRL = 0U;
  reg->GWCA_STS  = 0U;
  reg->GWCA_IE   = 0U;
  reg->GWCA_ICLR = 0U;
 
  /* Enable extended descriptor format on each agent before any GWCA
   * mode transition. Without this the AXI init handshake (GWARIRM.ARR)
   * never asserts. Mirrors FSP r_layer3_switch open path. */
  /* HUM Ch 30 "Ethernet Message Forwarding Engine (MFWD)" p 1321 */
  volatile uint32_t* const fwpc10 =
    (volatile uint32_t*)(k_ra8_mfwd_base_addr + (uintptr_t)k_ra8_mfwd_off_fwpc10);
  volatile uint32_t* const fwpc11 =
    (volatile uint32_t*)(k_ra8_mfwd_base_addr + (uintptr_t)k_ra8_mfwd_off_fwpc11);
  volatile uint32_t* const fwpc12 =
    (volatile uint32_t*)(k_ra8_mfwd_base_addr + (uintptr_t)k_ra8_mfwd_off_fwpc12);
  *fwpc10 = (*fwpc10 & ~(uint32_t)k_ra8_mfwd_fwpc_dde) | (uint32_t)k_ra8_mfwd_fwpc_dde;
  *fwpc11 = (*fwpc11 & ~(uint32_t)k_ra8_mfwd_fwpc_dde) | (uint32_t)k_ra8_mfwd_fwpc_dde;
  *fwpc12 = (*fwpc12 & ~(uint32_t)k_ra8_mfwd_fwpc_dde) | (uint32_t)k_ra8_mfwd_fwpc_dde;
 
  ra8_log_info(s_tag, "gwca_init");
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_gwca_deinit(void)
{
  volatile r_gwca_regs_t* reg = ra8_gwca();
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  reg->GWCA_CTRL = 0U;
  reg->GWCA_IE   = 0U;
  s_gwca_fn      = nullptr;
  s_gwca_ctx     = nullptr;
  return ra8_mstp_disable(k_ra8_mstp_eswm);
}
 
ra8_err_t ra8_eth_gwca_get_status(uint32_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "out_mask must not be nullptr");
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  *out_mask = ra8_gwca()->GWCA_STS;
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_gwca_clear_status(uint32_t mask)
{
  volatile r_gwca_regs_t* reg = ra8_gwca();
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  reg->GWCA_ICLR = mask;
  reg->GWCA_STS  = reg->GWCA_STS & ~mask;
  return k_ra8_ok;
}
 
ra8_err_t ra8_eth_gwca_attach_handler(ra8_eth_gwca_event_fn_t fn, void* ctx)
{
  s_gwca_fn  = fn;
  s_gwca_ctx = ctx;
  return k_ra8_ok;
}
 
RA8_ISR_SAFE
void ra8_eth_gwca_dispatch(void)
{
  volatile r_gwca_regs_t* reg = ra8_gwca();
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  const uint32_t                mask = reg->GWCA_STS;
  const ra8_eth_gwca_event_fn_t fn   = s_gwca_fn;
  void* const                   ctx  = s_gwca_ctx;
  reg->GWCA_ICLR                     = mask;
  reg->GWCA_STS                      = 0U;
  if (fn != nullptr) {
    fn(ctx, mask);
  }
}
 
ra8_err_t ra8_eth_gwca_enter_stop(void)
{
  /* HUM Ch 34 "Ethernet CPU Agent (GWCA)" p 1787 */
  ra8_gwca()->GWCA_CTRL = 0U;
  return ra8_mstp_disable(k_ra8_mstp_eswm);
}
 
ra8_err_t ra8_eth_gwca_exit_stop(void)
{
  return ra8_mstp_enable(k_ra8_mstp_eswm);
}

volatile uint32_t g_ra8_eth_gwca_open_step;

volatile uint32_t g_ra8_eth_gwca_pre_step;

volatile uint32_t g_ra8_eth_gwca_bring_up_step;
 
/* GWMC.OPC field at bits [1:0], GWMS.OPS field at bits [1:0]. The
 * full register layout matches FSP R_GWCA0_Type from the cloned
 * Renesas FSP source. */

ra8_err_t ra8_eth_gwca_set_operation_mode(ra8_gwmc_opc_t mode)
{
  if ((uint32_t)mode > (uint32_t)k_ra8_gwmc_opc_mask) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 34.3.1 "GWMC : Mode Configuration Register" p 1792 */
  volatile uint32_t* const gwmc =
    (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwmc);
 
  const uint32_t opc = (uint32_t)mode & (uint32_t)k_ra8_gwmc_opc_mask;
  const uint32_t cur = *gwmc & ~(uint32_t)k_ra8_gwmc_opc_mask;
  *gwmc              = cur | opc;
 
  /* HUM Ch 34.3.2 "GWMS : Mode Status Register" p 1792 */
  volatile const uint32_t* const gwms =
    (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwms);
  /* GWMS.OPS converges to a specific 2-bit value (opc), not a single-mask
   * set/clear, so the ra8_hw_wait_flag_* helpers do not fit -- run the real
   * poll inline and route the host unit-test build through the ra8_fake_mmio
   * seam so the poll/timeout legs execute rather than short-circuit (T1-01). */
  for (uint32_t i = 0U; i < k_ra8_eth_gwca_mode_spin; ++i) {
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    if (ra8_fake_mmio_wait_eval(gwms, i, ((*gwms & (uint32_t)k_ra8_gwmc_opc_mask) == opc))) {
      return k_ra8_ok;
    }
#else
    if ((*gwms & (uint32_t)k_ra8_gwmc_opc_mask) == opc) {
      return k_ra8_ok;
    }
#endif
  }
  ra8_log_error(s_tag, "set_operation_mode: GWMS.OPS never converged");
  return k_ra8_err_hw_timeout;
}

ra8_err_t ra8_eth_gwca_axi_init(void)
{
  /* HUM Ch 34.3.x "GWARIRM" -- the AXI Manager (vendor name uses
   * the older M-word) Initialization Request register. ARIOG bit is
   * the request, ARR bit is the response. Sequence per FSP
   * r_layer3_switch_initialize_gwca: set ARIOG=1, poll ARR until 1. */
  enum : uint32_t {
    k_ra8_gwarirm_ariog = 1UL << 0, 
    k_ra8_gwarirm_arr   = 1UL << 1, 
  };
  volatile uint32_t* const gwarirm =
    (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwarirm);
  *gwarirm = k_ra8_gwarirm_ariog;
 
  /* Wait for GWARIRM.ARR to set. The ra8_hw_wait_flag_set32 loop runs on every
   * build -- including the host unit test, where it is consulted by the
   * ra8_fake_mmio seam -- so the poll/timeout legs execute rather than compile
   * out behind an RA8_OFF_TARGET short-circuit (T1-01). */
  const ra8_err_t err = ra8_hw_wait_flag_set32(gwarirm,
                                               (uint32_t)k_ra8_gwarirm_arr,
                                               (uint32_t)k_ra8_eth_gwca_mode_spin);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "axi_init: GWARIRM.ARR never asserted");
  }
  return err;
}

ra8_err_t ra8_eth_gwca_install_linkfix(ra8_gwca_basic_descriptor_t* linkfix_table,
                                       uint32_t                     entry_count)
{
  RA8_CHECK_NULL_PTR(linkfix_table, s_tag, "install_linkfix: table must not be null");
  enum : uint32_t {
    k_ra8_gwca_linkfix_max_entries = 32U 
  };
  if (entry_count == 0U || entry_count > k_ra8_gwca_linkfix_max_entries) {
    ra8_log_error(s_tag, "install_linkfix: entry_count out of range");
    return k_ra8_err_invalid_arg;
  }
 
  /* Initialize every entry to LEMPTY (queue disabled). The chip
   * walks the LINKFIX table at queue-activation time, so any entry
   * not explicitly populated with a real chain head must look
   * disabled instead of pointing at random memory. */
  (void)memset(linkfix_table, 0, (size_t)entry_count * sizeof(ra8_gwca_basic_descriptor_t));
  for (uint32_t i = 0U; i < entry_count; ++i) {
    linkfix_table[i].dt = (uint8_t)k_ra8_gwdcc_dt_lempty;
  }
 
  /* HUM Ch 34.3.7.2 / 34.3.7.3 GWDCBAC0/1: split the table's
   * 40-bit address into PTR[39:32] (GWDCBAC0.DCBAU) and PTR[31:0]
   * (GWDCBAC1.DCBAL). On this 32-bit MCU the upper byte is always
   * zero, but the bit-field exists for the device family that uses
   * 40-bit addresses. */
  const uintptr_t addr = (uintptr_t)linkfix_table;
  enum : uintptr_t {
    k_ra8_linkfix_upper_shift = 32U,           
    k_ra8_linkfix_upper_mask  = 0xFFULL,       
    k_ra8_linkfix_lower_mask  = 0xFFFFFFFFULL, 
  };
  const uint32_t upper =
    (uint32_t)((uint64_t)addr >> k_ra8_linkfix_upper_shift) & k_ra8_linkfix_upper_mask;
  const uint32_t           lower = (uint32_t)addr & k_ra8_linkfix_lower_mask;
  volatile uint32_t* const gwdcbac0 =
    (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwdcbac0);
  volatile uint32_t* const gwdcbac1 =
    (volatile uint32_t*)(k_ra8_gwca0_base_addr + (uintptr_t)k_ra8_gwca_off_gwdcbac1);
  *gwdcbac0 = upper;
  *gwdcbac1 = lower;
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_bring_up_to_config(ra8_gwca_basic_descriptor_t* linkfix_table,
                                             uint32_t                     entry_count)
{
  ra8_err_t err = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_1;
    return err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_1;
  err                          = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_config);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_2;
    (void)ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
    return err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_2;
  err                          = ra8_eth_gwca_axi_init();
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_3;
    (void)ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
    return err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_3;
  err                          = ra8_eth_gwca_install_linkfix(linkfix_table, entry_count);
  if (err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_4;
    (void)ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
    return err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_4;
  return k_ra8_ok;
}

ra8_err_t ra8_eth_gwca_bring_up(ra8_gwca_basic_descriptor_t* linkfix_table, uint32_t entry_count)
{
  g_ra8_eth_gwca_bring_up_step = 0U;
  const ra8_err_t phase1_err   = internal_bring_up_to_config(linkfix_table, entry_count);
  if (phase1_err != k_ra8_ok) {
    return phase1_err;
  }
  const ra8_err_t dis_err = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_disable);
  if (dis_err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_5;
    return dis_err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_5;
  const ra8_err_t op_err       = ra8_eth_gwca_set_operation_mode(k_ra8_gwmc_opc_operation);
  if (op_err != k_ra8_ok) {
    g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_fail_6;
    return op_err;
  }
  g_ra8_eth_gwca_bring_up_step = (uint32_t)k_ra8_eth_gwca_step_ok_6;
  return k_ra8_ok;
}