73typedef enum : uint32_t {
96typedef enum : uint64_t {
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
ra8_err_t ra8_eth_gptp_timer_disable(ra8_gptp_timer_idx_t timer)
Stop one timer unit (PTPTMDC.TDq).
ra8_eth_gptp_sec_limit_t
Upper bound of the GPTP seconds field.
@ k_ra8_gptp_sec_max
Largest 48-bit seconds value.
ra8_err_t ra8_eth_gptp_timer_is_enabled(ra8_gptp_timer_idx_t timer, bool *out_enabled)
Report whether one timer unit is enabled.
ra8_err_t ra8_eth_gptp_get_increment(ra8_gptp_timer_idx_t timer, uint32_t *out_tiv)
Read one timer unit's increment register PTPTIVCt.
ra8_err_t ra8_eth_gptp_ip_version(uint32_t *out_version)
Read the read-only PTPIPV IP-version word.
ra8_err_t ra8_eth_gptp_tiv_from_hz(uint32_t clk_hz, uint32_t *out_tiv)
Derive PTPTIVCt.TIV from a clk frequency.
ra8_err_t ra8_eth_gptp_timer_enable(ra8_gptp_timer_idx_t timer)
Start one timer unit (PTPTMEC.TEq).
ra8_err_t ra8_eth_gptp_enter_stop(void)
Stop both timers and assert the ESWM module-stop gate.
ra8_err_t ra8_eth_gptp_get_time(ra8_gptp_timer_idx_t timer, uint64_t *out_sec, uint32_t *out_nsec)
Read one timer unit's 78-bit GPTP time.
ra8_err_t ra8_eth_gptp_set_offset(ra8_gptp_timer_idx_t timer, uint64_t sec, uint32_t nsec)
Load one timer unit's additive 78-bit offset.
ra8_eth_gptp_limit_t
Field limits taken from the HUM register descriptions.
@ k_ra8_gptp_ns_per_sec
Nanoseconds in one second.
@ k_ra8_gptp_nsec_max
Largest legal PTPTOVCtL.TOVL.
ra8_err_t ra8_eth_gptp_get_avtp_ns(ra8_gptp_timer_idx_t timer, uint64_t *out_ns)
Read one timer unit's 64-bit AVTP nanosecond counter.
ra8_err_t ra8_eth_gptp_set_increment(ra8_gptp_timer_idx_t timer, uint32_t tiv)
Write one timer unit's increment register PTPTIVCt.
ra8_err_t ra8_eth_gptp_deinit(void)
Stop both timers, clear their configuration and gate the block off.
ra8_err_t ra8_eth_gptp_exit_stop(void)
Release the ESWM module-stop gate again.
ra8_err_t ra8_eth_gptp_init(const ra8_eth_gptp_cfg_t *cfg)
Power up the GPTP block and programme both timers' increment.
Ethernet controller base addresses for the Renesas RA8D2.
ra8_gptp_timer_idx_t
GPTP timer instance index (HUM Table 35.3 lists t = 0, 1).
Static configuration for ra8_eth_gptp_init.
uint32_t clk_hz
ESWCLK frequency in Hz feeding the GPTP counter.