ra8_board_ek_ra8d2_comms.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_board_ek_ra8d2_internal.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_mipi_dsi.h"
#include "ra8_mipi_phy.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_sci.h"
#include "ra8_time_constants.h"

ra8_err_t ra8_board_clocks_init(ra8_board_clock_rates_t* out_rates)
{
  if (out_rates == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  const ra8_err_t err = ra8_cgc_init();
  if (err != k_ra8_ok) {
    return err;
  }
  *out_rates = (ra8_board_clock_rates_t){
    .cpuclk0_hz = (uint32_t)k_ra8_cpuclk0_hz,
    .pclka_hz   = (uint32_t)k_ra8_pclka_hz,
  };
  return k_ra8_ok;
}
 
/* =============================================================================
 * 10. MIPI-DSI panel bring-up (J32 -- Renesas RTKMIPILCDB00000BE mezzanine)
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_board_mipi_panel_h_active       = 480U, 
  k_ra8_board_mipi_panel_v_active       = 854U, 
  k_ra8_board_mipi_panel_line_rate_mbps = 480U, 
} ra8_board_mipi_panel_geometry_t;

static const ra8_mipi_dsi_config_t s_mipi_panel_cfg = {
  .lane_count             = k_ra8_mipi_dsi_lanes_2,
  .clock_mode             = k_ra8_mipi_dsi_clock_non_continuous,
  .max_return_packet_size = 16U,
  .ulps_wakeup_period     = 0U,
  .ecc_check_enable       = true,
  .eotp_enable            = true,
  .scramble_enable        = false,
  .tearing_detect_enable  = true,
  .crc_check_vc_mask      = 0x01U, /* VC0 only -- the only VC J32 wires up. */
  .timing                 = {},    /* TODO(panel-datasheet).                */
  .timeouts               = {},    /* TODO(panel-datasheet).                */
};

static const ra8_mipi_phy_timing_t s_mipi_phy_timing_placeholder = {
  .tinit = 1U,
};

static const ra8_mipi_phy_config_t s_mipi_phy_cfg = {
  .mode           = k_ra8_mipi_phy_mode_dsi_host,
  .pclka_mhz      = k_panel_pclka_mhz,
  .line_rate_mbps = (uint16_t)k_ra8_board_mipi_panel_line_rate_mbps,
  .lane_count     = k_ra8_mipi_phy_lane_count_2,
  .clk_mode       = k_ra8_mipi_phy_clk_noncontinuous,
  .eotp           = k_ra8_mipi_phy_eotp_enabled,
  .pll =
    {
      .idiv     = k_ra8_mipi_phy_idiv_1,
      .pmul     = k_ra8_mipi_phy_pmul_4,
      .nfmul    = k_ra8_mipi_phy_nfmul_0_00,
      .nmul_int = k_panel_pll_nmul, /* TODO(panel-datasheet). */
    },
  .escdiv   = 0U,
  .p_timing = &s_mipi_phy_timing_placeholder,
};
 
ra8_err_t ra8_board_mipi_dsi_init(void)
{
  /* Step 1: PHY first -- HUM Ch 64.3.1 startup procedure. The HAL warns
   * "The MIPI PHY (HUM Ch 64) must be brought up first" before the DSI
   * host can clock its LP/HS lanes. */
  ra8_err_t err = ra8_mipi_phy_init(&s_mipi_phy_cfg);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 2: DSI host link layer (HUM Ch 65). Programmes TXSETR / DSISETR
   * / guard-band timing / timeouts -- but does NOT start the HS clock
   * yet, so the application can splice in the panel-side reset pulse on
   * k_ra8_board_mipi_dsi_reset_n (P606) and backlight enable on
   * k_ra8_board_mipi_dsi_backlight (P514) between init and clock start. */
  err = ra8_mipi_dsi_init(&s_mipi_panel_cfg);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 3: kick the differential HS clock. After this returns the link
   * is HS-ready; callers can replay the panel DCS init stream via
   * ra8_mipi_dsi_send_command() and finally call ra8_mipi_dsi_video_start.
   *
   * TODO(panel-datasheet): the per-panel DCS command sequence (sleep-out,
   * pixel-format set, display-on, etc.) for the Focus E45RA-MW276-C is
   * not committed here -- the application currently owns it. */
  return ra8_mipi_dsi_hs_clock_start();
}
 
/* =============================================================================
 * 11. J-Link OB VCOM serial bridge (UM Table 13, page 24)
 * =============================================================================
 */

static bool s_uart_console_initialized = false;

typedef enum : uint32_t {
  k_ra8_board_uart_console_min_pclka_hz =
    16000000UL, 
} ra8_board_uart_console_clock_t;
 
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
{
  if (baud == 0U) {
    return k_ra8_err_invalid_arg;
  }
 
  /* SCI8's baud generator is fed by PCLKA on RA8D2 (chip HUM Ch 38.2
   * "SCI registers"). Hardcoding a constant here was the bug behind
   * every garbled UART symptom on apps that retune CGC: the BRR was
   * being computed for an assumed 60 MHz against a real 125 MHz clock,
   * so the line rate came out 2x too fast. Read PCLKA from CGC at
   * runtime instead so the BRR tracks whatever the application's CGC
   * tree settled on. */
  uint32_t  pclka_hz = 0U;
  ra8_err_t err      = ra8_cgc_get_clock_hz(k_ra8_clock_id_pclka, &pclka_hz);
  if (err != k_ra8_ok) {
    /* ra8_cgc_get_clock_hz with a valid clock-id and non-null out always returns k_ra8_ok. */
    return err; /* GCOVR_EXCL_LINE -- fixed PCLKA id and nonnull local satisfy get_clock_hz's only guards */
  }
  if (pclka_hz < (uint32_t)k_ra8_board_uart_console_min_pclka_hz) {
    return k_ra8_err_not_initialized;
  }
 
  /* Route PD02 -> TXD8, PD03 -> RXD8 (UM Table 13 p 24). PSEL value
   * k_ra8_psel_sci_async = 0x04 covers SCI async TXD/RXD per the chip
   * HUM Multiplexed Pin Function Selector. */
  err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_ra8_board_uart_console_pin_txd,
                                 k_ra8_psel_sci_async,
                                 "ra8_board.uart.console.txd");
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_ra8_board_uart_console_pin_rxd,
                                 k_ra8_psel_sci_async,
                                 "ra8_board.uart.console.rxd");
  if (err != k_ra8_ok) {
    return err;
  }
 
  const ra8_sci_cfg_t cfg = {
    .baud      = baud,
    .data_bits = k_ra8_sci_data_8,
    .parity    = k_ra8_sci_parity_none,
    .stop_bits = k_ra8_sci_stop_1,
    .pclk_hz   = pclka_hz,
  };
  err = ra8_sci_init((uint8_t)k_ra8_board_uart_console_sci_channel, &cfg);
  if (err != k_ra8_ok) {
    return err;
  }
  s_uart_console_initialized = true;
  return k_ra8_ok;
}
 
ra8_err_t ra8_board_uart_console_write(const uint8_t* data, size_t len)
{
  if (len == 0U) {
    return k_ra8_ok;
  }
  if (data == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_uart_console_initialized) {
    return k_ra8_err_not_initialized;
  }
  return ra8_sci_write_polling((uint8_t)k_ra8_board_uart_console_sci_channel, data, (uint32_t)len);
}
 
ra8_err_t ra8_board_uart_console_read(uint8_t* out, size_t cap, size_t* out_len)
{
  if (out_len == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  *out_len = 0U;
  if (cap == 0U) {
    return k_ra8_ok;
  }
  if (out == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_uart_console_initialized) {
    return k_ra8_err_not_initialized;
  }
 
  /* Polled non-blocking drain: pull bytes while RDRF stays set, stop
   * the moment ra8_sci_getc_polling reports nothing available. The cap
   * bounds the loop (NASA Rule 2). */
  for (size_t i = 0U; i < cap; ++i) {
    uint8_t         byte = 0U;
    const ra8_err_t err =
      ra8_sci_getc_polling((uint8_t)k_ra8_board_uart_console_sci_channel, &byte);
    if (err != k_ra8_ok) {
      /* No byte available yet -- treat as a non-blocking stop. */
      return k_ra8_ok;
    }
    out[i] = byte;
    *out_len += 1U;
  }
  return k_ra8_ok;
}

RA8_PRIV bool priv_ra8_board_uart_console_is_up(void)
{
  return s_uart_console_initialized;
}
 
ra8_err_t ra8_board_uart_console_flush(void)
{
  if (!s_uart_console_initialized) {
    return k_ra8_err_not_initialized;
  }
  /* HUM Ch 38.2.17 "CSR : Common Status Register", p 2225 -- defer to
   * ra8_sci_flush which spins on CSR.TEND for the SCI8 channel that
   * backs this console. Lets panic_halt() drain the failure log before
   * WFI gates the SCI clock. */
  return ra8_sci_flush((uint8_t)k_ra8_board_uart_console_sci_channel);
}