ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_mipi_phy_types.h
Go to the documentation of this file.
1
21
22#pragma once
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#include <stdint.h>
29
30#include "ra8_err.h"
31#include "ra8_mipi_phy_regs.h"
32
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208
233
245typedef struct {
249 uint32_t raw;
251
273
287typedef struct {
288 uint32_t tinit;
289 uint8_t tclkprep;
290 uint8_t tclksett;
291 uint8_t tclkmiss;
292 uint8_t thsprep;
293 uint8_t thssett;
294 uint8_t tclkzero;
295 uint8_t tclkpre;
296 uint8_t tclkpost;
297 uint8_t tclktrl;
298 uint8_t thszero;
299 uint8_t thstrl;
300 uint8_t thsexit;
301 uint8_t tlpx;
303
323
332typedef void (*ra8_mipi_phy_event_fn_t)(void* ctx, ra8_mipi_phy_event_t event, uint32_t sfr);
333
334#ifdef __cplusplus
335}
336#endif
Error Code Definitions for ra8-firmware.
MIPI D-PHY register layout for the RA8D2.
void(* ra8_mipi_phy_event_fn_t)(void *ctx, ra8_mipi_phy_event_t event, uint32_t sfr)
MIPI PHY status callback (LDO ready / PLL lock / PLL drop).
ra8_mipi_phy_state_t
Lifecycle position of the D-PHY block.
@ k_ra8_mipi_phy_state_error
LDO drop or PLL lost lock.
@ k_ra8_mipi_phy_state_run
DPHYEN=1, transmitting / receiving.
@ k_ra8_mipi_phy_state_off
MSTPCRC bit set, regs unreachable.
@ k_ra8_mipi_phy_state_ldo_up
PWRSEN=1, PWRSF=1, PLL stopped.
@ k_ra8_mipi_phy_state_idle
MSTPCRC clear, no LDO yet.
@ k_ra8_mipi_phy_state_pll_run
PLLSTP=0, PLLSF=1, DPHYEN=0.
ra8_mipi_phy_event_t
Event source codes pushed through ra8_mipi_phy_event_fn_t.
@ k_ra8_mipi_phy_event_pll_lost
DPHYSFR.PLLSF fell 1->0.
@ k_ra8_mipi_phy_event_ldo_ready
DPHYSFR.PWRSF rose 0->1.
@ k_ra8_mipi_phy_event_pll_locked
DPHYSFR.PLLSF rose 0->1.
@ k_ra8_mipi_phy_event_ldo_lost
DPHYSFR.PWRSF fell 1->0.
@ k_ra8_mipi_phy_event_status_chg
Catch-all status change.
ra8_mipi_phy_pll_idiv_t
DPHYPLFCR.IDIV[1:0] – input frequency divisor.
@ k_ra8_mipi_phy_idiv_2
IDIV = 1/2.
@ k_ra8_mipi_phy_idiv_1
IDIV = 1 (no division).
@ k_ra8_mipi_phy_idiv_3
IDIV = 1/3.
@ k_ra8_mipi_phy_idiv_4
IDIV = 1/4.
ra8_mipi_phy_lane_count_t
Number of D-PHY data lanes activated for a transfer.
@ k_ra8_mipi_phy_lane_count_1
1 data lane.
@ k_ra8_mipi_phy_lane_count_4
4 data lanes – rejected on RA8D2.
@ k_ra8_mipi_phy_lane_count_2
2 data lanes (silicon maximum).
@ k_ra8_mipi_phy_lane_count_3
3 data lanes – rejected on RA8D2.
ra8_mipi_phy_mode_t
D-PHY host vs device mode select (DPHYMDC.MASTEREN).
@ k_ra8_mipi_phy_mode_csi_device
Device mode used by MIPI CSI.
@ k_ra8_mipi_phy_mode_dsi_host
Host mode used by MIPI DSI.
ra8_mipi_phy_dual_mode_t
Arbitration policy when both DSI and CSI want the PHY.
@ k_ra8_mipi_phy_dual_csi_priority
CSI wins; DSI requests fail.
@ k_ra8_mipi_phy_dual_dsi_priority
DSI wins; CSI requests fail.
@ k_ra8_mipi_phy_dual_alternate
Time-share, switch on request.
@ k_ra8_mipi_phy_dual_off
Single-owner – no arbitration.
ra8_mipi_phy_pll_nfmul_t
DPHYPLFCR.NFMUL[1:0] – fractional multiplier (NF).
@ k_ra8_mipi_phy_nfmul_0_66
NF = 0.66.
@ k_ra8_mipi_phy_nfmul_0_00
NF = 0.00.
@ k_ra8_mipi_phy_nfmul_0_33
NF = 0.33.
@ k_ra8_mipi_phy_nfmul_0_50
NF = 0.50.
ra8_mipi_phy_clk_mode_t
HS clock-lane operating mode.
@ k_ra8_mipi_phy_clk_noncontinuous
Drop to LP-11 between bursts.
@ k_ra8_mipi_phy_clk_continuous
Keep HS clock running.
ra8_mipi_phy_pll_pmul_t
DPHYPLFCR.PMUL[1:0] – output frequency divisor.
@ k_ra8_mipi_phy_pmul_8
P = 1/8 (120.
@ k_ra8_mipi_phy_pmul_1
P = 1 (960.
@ k_ra8_mipi_phy_pmul_4
P = 1/4 (240.
@ k_ra8_mipi_phy_pmul_2
P = 1/2 (480.
ra8_mipi_phy_lane_id_t
Per-lane identifier passed to ra8_mipi_phy_set_lane_enable.
@ k_ra8_mipi_phy_lane_d3
Data lane 3 – not on RA8D2.
@ k_ra8_mipi_phy_lane_d1
Data lane 1.
@ k_ra8_mipi_phy_lane_d2
Data lane 2 – not on RA8D2.
@ k_ra8_mipi_phy_lane_d0
Data lane 0.
@ k_ra8_mipi_phy_lane_clk
Clock lane (always-on).
ra8_mipi_phy_eotp_t
End-of-Transmission Packet emission setting (DSI host only).
@ k_ra8_mipi_phy_eotp_disabled
Do not append EoTP.
@ k_ra8_mipi_phy_eotp_enabled
Append EoTP packet.
Top-level configuration for ra8_mipi_phy_init.
ra8_mipi_phy_clk_mode_t clk_mode
Continuous vs non-continuous HS clock.
const ra8_mipi_phy_timing_t * p_timing
Non-NULL timing block.
ra8_mipi_phy_pll_t pll
PLL coefficients.
uint16_t line_rate_mbps
Per-lane line rate (80..720).
ra8_mipi_phy_mode_t mode
Host (DSI) or device (CSI).
uint8_t escdiv
Escape clk divisor (0..31).
ra8_mipi_phy_lane_count_t lane_count
1 or 2 data lanes.
ra8_mipi_phy_eotp_t eotp
Append EoTP (DSI only).
uint8_t pclka_mhz
PCLKA frequency, MHz (40..125).
D-PHY PLL coefficients written into DPHYPLFCR.
ra8_mipi_phy_pll_pmul_t pmul
PMUL[1:0] output divisor.
ra8_mipi_phy_pll_nfmul_t nfmul
NFMUL[1:0] fractional N.
uint16_t nmul_int
NMUL[8:0] integer N (40..375).
ra8_mipi_phy_pll_idiv_t idiv
IDIV[1:0] input divisor.
Decoded DPHYSFR snapshot returned by ra8_mipi_phy_get_status_decoded.
bool phy_ready
(PWRSF & PLLSF) – driver fully armed.
bool pll_locked
PLLSF (bit 8) – PLL clock stable.
uint32_t raw
Verbatim DPHYSFR snapshot.
bool ldo_ready
PWRSF (bit 0) – LDO power-on stable.
D-PHY HS/LP transition timing values (DPHYTIM1..6).
uint8_t tclkprep
DPHYTIM2.TCLKPREP[7:0].
uint8_t thssett
DPHYTIM3.THSSETT[7:0].
uint8_t thszero
DPHYTIM5.THSZERO[7:0].
uint8_t tclkzero
DPHYTIM4.TCLKZERO[7:0].
uint8_t thstrl
DPHYTIM5.THSTRL[7:0].
uint8_t tclktrl
DPHYTIM4.TCLKTRL[7:0].
uint8_t tclkmiss
DPHYTIM2.TCLKMISS[7:0].
uint8_t tlpx
DPHYTIM6.TLPX[7:0].
uint8_t tclkpre
DPHYTIM4.TCLKPRE[7:0].
uint8_t tclkpost
DPHYTIM4.TCLKPOST[7:0].
uint8_t thsprep
DPHYTIM3.THSPREP[7:0].
uint8_t thsexit
DPHYTIM5.THSEXIT[7:0].
uint8_t tclksett
DPHYTIM2.TCLKSETT[7:0].
uint32_t tinit
DPHYTIM1.TINIT[18:0].