MIPI D-PHY driver – shared enums, structs, and callback typedef. More...

#include <stdint.h>
#include "ra8_err.h"
#include "ra8_mipi_phy_regs.h"

Include dependency graph for ra8_mipi_phy_types.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	ra8_mipi_phy_status_decoded_t
	Decoded DPHYSFR snapshot returned by ra8_mipi_phy_get_status_decoded. More...
struct	ra8_mipi_phy_pll_t
	D-PHY PLL coefficients written into DPHYPLFCR. More...
struct	ra8_mipi_phy_timing_t
	D-PHY HS/LP transition timing values (DPHYTIM1..6). More...
struct	ra8_mipi_phy_config_t
	Top-level configuration for ra8_mipi_phy_init. More...

Typedefs
typedef void(*	ra8_mipi_phy_event_fn_t) (void *ctx, ra8_mipi_phy_event_t event, uint32_t sfr)
	MIPI PHY status callback (LDO ready / PLL lock / PLL drop).

Enumerations
enum	ra8_mipi_phy_mode_t : uint8_t { k_ra8_mipi_phy_mode_csi_device = 0U , k_ra8_mipi_phy_mode_dsi_host = 1U }
	D-PHY host vs device mode select (DPHYMDC.MASTEREN). More...
enum	ra8_mipi_phy_lane_count_t : uint8_t { k_ra8_mipi_phy_lane_count_1 = 1U , k_ra8_mipi_phy_lane_count_2 = 2U , k_ra8_mipi_phy_lane_count_3 = 3U , k_ra8_mipi_phy_lane_count_4 = 4U }
	Number of D-PHY data lanes activated for a transfer. More...
enum	ra8_mipi_phy_lane_id_t : uint8_t { k_ra8_mipi_phy_lane_clk = 0U , k_ra8_mipi_phy_lane_d0 = 1U , k_ra8_mipi_phy_lane_d1 = 2U , k_ra8_mipi_phy_lane_d2 = 3U , k_ra8_mipi_phy_lane_d3 = 4U }
	Per-lane identifier passed to ra8_mipi_phy_set_lane_enable. More...
enum	ra8_mipi_phy_clk_mode_t : uint8_t { k_ra8_mipi_phy_clk_noncontinuous = 0U , k_ra8_mipi_phy_clk_continuous = 1U }
	HS clock-lane operating mode. More...
enum	ra8_mipi_phy_eotp_t : uint8_t { k_ra8_mipi_phy_eotp_disabled = 0U , k_ra8_mipi_phy_eotp_enabled = 1U }
	End-of-Transmission Packet emission setting (DSI host only). More...
enum	ra8_mipi_phy_pll_idiv_t : uint8_t { k_ra8_mipi_phy_idiv_1 = 0U , k_ra8_mipi_phy_idiv_2 = 1U , k_ra8_mipi_phy_idiv_3 = 2U , k_ra8_mipi_phy_idiv_4 = 3U }
	DPHYPLFCR.IDIV[1:0] – input frequency divisor. More...
enum	ra8_mipi_phy_pll_pmul_t : uint8_t { k_ra8_mipi_phy_pmul_1 = 0U , k_ra8_mipi_phy_pmul_2 = 1U , k_ra8_mipi_phy_pmul_4 = 2U , k_ra8_mipi_phy_pmul_8 = 3U }
	DPHYPLFCR.PMUL[1:0] – output frequency divisor. More...
enum	ra8_mipi_phy_pll_nfmul_t : uint8_t { k_ra8_mipi_phy_nfmul_0_00 = 0U , k_ra8_mipi_phy_nfmul_0_33 = 1U , k_ra8_mipi_phy_nfmul_0_66 = 2U , k_ra8_mipi_phy_nfmul_0_50 = 3U }
	DPHYPLFCR.NFMUL[1:0] – fractional multiplier (NF). More...
enum	ra8_mipi_phy_event_t : uint8_t { k_ra8_mipi_phy_event_ldo_ready = 0U , k_ra8_mipi_phy_event_ldo_lost = 1U , k_ra8_mipi_phy_event_pll_locked = 2U , k_ra8_mipi_phy_event_pll_lost = 3U , k_ra8_mipi_phy_event_status_chg = 4U }
	Event source codes pushed through ra8_mipi_phy_event_fn_t. More...
enum	ra8_mipi_phy_state_t : uint8_t { k_ra8_mipi_phy_state_off = 0U , k_ra8_mipi_phy_state_idle = 1U , k_ra8_mipi_phy_state_ldo_up = 2U , k_ra8_mipi_phy_state_pll_run = 3U , k_ra8_mipi_phy_state_run = 4U , k_ra8_mipi_phy_state_error = 5U }
	Lifecycle position of the D-PHY block. More...
enum	ra8_mipi_phy_dual_mode_t : uint8_t { k_ra8_mipi_phy_dual_off = 0U , k_ra8_mipi_phy_dual_alternate = 1U , k_ra8_mipi_phy_dual_dsi_priority = 2U , k_ra8_mipi_phy_dual_csi_priority = 3U }
	Arbitration policy when both DSI and CSI want the PHY. More...

Detailed Description

MIPI D-PHY driver – shared enums, structs, and callback typedef.

Tag: [Ring 3 / HAL] {World: NS}

Type definitions for the RA8D2 MIPI PHY block (HUM Ch 64, p 3822-3838). This sub-header carries every typed enum, register-mirror struct, and the status-callback typedef shared by the DSI and CSI clients of the PHY. The function prototypes that consume these types live in ra8_mipi_phy_api.h; both are re-exported by the thin umbrella ra8_mipi_phy.h.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file ra8_mipi_phy_types.h.

Typedef Documentation

◆ ra8_mipi_phy_event_fn_t

typedef void(* ra8_mipi_phy_event_fn_t) (void *ctx, ra8_mipi_phy_event_t event, uint32_t sfr)

MIPI PHY status callback (LDO ready / PLL lock / PLL drop).

Parameters

[in]	ctx	Caller context registered via ra8_mipi_phy_attach_handler.
[in]	event	Decoded event source from ra8_mipi_phy_event_t.
[in]	sfr	Snapshot of DPHYSFR at dispatch time.

Definition at line 332 of file ra8_mipi_phy_types.h.

Enumeration Type Documentation

◆ ra8_mipi_phy_clk_mode_t

enum ra8_mipi_phy_clk_mode_t : uint8_t

HS clock-lane operating mode.

D-PHY allows two clock-lane behaviours:

Continuous (k_ra8_mipi_phy_clk_continuous): HS clock is kept toggling between bursts. Lower latency on burst entry, higher dynamic power.
Non-continuous (k_ra8_mipi_phy_clk_noncontinuous): clock lane drops to LP-11 between bursts. Saves power; pays a TCLK-PRE handshake on each new burst.

The PHY block does not select this directly (DSI / CSI host drivers own the actual lane state machine), but the driver records the caller's choice so other modules can query it via ra8_mipi_phy_get_clock_mode.

Enumerator
k_ra8_mipi_phy_clk_noncontinuous	Drop to LP-11 between bursts.
k_ra8_mipi_phy_clk_continuous	Keep HS clock running.

Definition at line 109 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_dual_mode_t

enum ra8_mipi_phy_dual_mode_t : uint8_t

Arbitration policy when both DSI and CSI want the PHY.

The RA8D2 silicon hosts a single D-PHY shared between DSI host (Ch 65) and CSI device (Ch 66). MIPI-DSI and MIPI-CSI cannot be active simultaneously – DPHYMDC.MASTEREN is a single bit. To cover the brief's "dual-mode" requirement, the PHY driver tracks an arbitration policy that the higher-level stack can consult before it requests the PHY. alternate switches per request, dsi_priority and csi_priority lock to one client.

The driver does not implement queueing – it simply records the policy so the consumer can decide what to do when a conflict arises (typically: drop the lower-priority client, switch the PHY mode, then promote the higher-priority client).

Enumerator
k_ra8_mipi_phy_dual_off	Single-owner – no arbitration.
k_ra8_mipi_phy_dual_alternate	Time-share, switch on request.
k_ra8_mipi_phy_dual_dsi_priority	DSI wins; CSI requests fail.
k_ra8_mipi_phy_dual_csi_priority	CSI wins; DSI requests fail.

Definition at line 227 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_eotp_t

enum ra8_mipi_phy_eotp_t : uint8_t

End-of-Transmission Packet emission setting (DSI host only).

MIPI DSI 1.2 spec section 8.8.2 makes the EoTP packet optional. Some panels require it, others ignore it. The PHY driver does not generate the packet itself (that is a DSI-host responsibility), but tracks the setting so the DSI driver can read it back without duplicating state.

Enumerator
k_ra8_mipi_phy_eotp_disabled	Do not append EoTP.
k_ra8_mipi_phy_eotp_enabled	Append EoTP packet.

Definition at line 125 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_event_t

enum ra8_mipi_phy_event_t : uint8_t

Event source codes pushed through ra8_mipi_phy_event_fn_t.

The MIPI PHY itself does not raise NVIC vectors; DSI / CSI hosts forward their interrupts here and the dispatcher translates the raw DPHYSFR snapshot into one of these codes for higher-level consumers.

Enumerator
k_ra8_mipi_phy_event_ldo_ready	DPHYSFR.PWRSF rose 0->1.
k_ra8_mipi_phy_event_ldo_lost	DPHYSFR.PWRSF fell 1->0.
k_ra8_mipi_phy_event_pll_locked	DPHYSFR.PLLSF rose 0->1.
k_ra8_mipi_phy_event_pll_lost	DPHYSFR.PLLSF fell 1->0.
k_ra8_mipi_phy_event_status_chg	Catch-all status change.

Definition at line 182 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_lane_count_t

enum ra8_mipi_phy_lane_count_t : uint8_t

Number of D-PHY data lanes activated for a transfer.

HUM Ch 64.1 Table 64.1 p 3822: this part exposes "Up to 2 lanes". The DSI host (Ch 65) and CSI receiver (Ch 66) each own a separate lane-enable register; the PHY driver tracks the requested count here so callers can reason about it consistently. 1-lane and 2-lane configurations are the only legal silicon settings.

The 3-lane / 4-lane enumerators are accepted by the public API (the brief mandates "every lane configuration") but the driver returns k_ra8_err_not_supported because the silicon physically cannot drive more than 2 lanes – attempting 3/4 lanes on this MCU group is a misconfiguration that the HAL should refuse loudly rather than silently fall back.

Enumerator
k_ra8_mipi_phy_lane_count_1	1 data lane.
k_ra8_mipi_phy_lane_count_2	2 data lanes (silicon maximum).
k_ra8_mipi_phy_lane_count_3	3 data lanes – rejected on RA8D2.
k_ra8_mipi_phy_lane_count_4	4 data lanes – rejected on RA8D2.

Definition at line 64 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_lane_id_t

enum ra8_mipi_phy_lane_id_t : uint8_t

Per-lane identifier passed to ra8_mipi_phy_set_lane_enable.

Lane 0 / Lane 1 are the two data lanes. The clock lane is implicit and always enabled when DPHYOCR.DPHYEN = 1 (HUM Ch 64.2.7 p 3827); the public API still exposes a k_ra8_mipi_phy_lane_clk value for symmetry so callers can write transfer code that loops over every lane.

Enumerator
k_ra8_mipi_phy_lane_clk	Clock lane (always-on).
k_ra8_mipi_phy_lane_d0	Data lane 0.
k_ra8_mipi_phy_lane_d1	Data lane 1.
k_ra8_mipi_phy_lane_d2	Data lane 2 – not on RA8D2.
k_ra8_mipi_phy_lane_d3	Data lane 3 – not on RA8D2.

Definition at line 82 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_mode_t

enum ra8_mipi_phy_mode_t : uint8_t

D-PHY host vs device mode select (DPHYMDC.MASTEREN).

Mirrors HUM Ch 64.2.14 p 3836-3837 and the FSP boolean mipi_phy_cfg_t.dsi_mode: 0 = device (CSI), 1 = host (DSI).

Enumerator
k_ra8_mipi_phy_mode_csi_device	Device mode used by MIPI CSI.
k_ra8_mipi_phy_mode_dsi_host	Host mode used by MIPI DSI.

Definition at line 41 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_pll_idiv_t

enum ra8_mipi_phy_pll_idiv_t : uint8_t

DPHYPLFCR.IDIV[1:0] – input frequency divisor.

HUM Ch 64.2.2 p 3823: divides the MOSC input. The 8..24 MHz post-divisor band must be respected (HUM 64.2.2 note p 3824).

Enumerator
k_ra8_mipi_phy_idiv_1	IDIV = 1 (no division).
k_ra8_mipi_phy_idiv_2	IDIV = 1/2.
k_ra8_mipi_phy_idiv_3	IDIV = 1/3.
k_ra8_mipi_phy_idiv_4	IDIV = 1/4.

Definition at line 138 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_pll_nfmul_t

enum ra8_mipi_phy_pll_nfmul_t : uint8_t

DPHYPLFCR.NFMUL[1:0] – fractional multiplier (NF).

Enumerator
k_ra8_mipi_phy_nfmul_0_00	NF = 0.00.
k_ra8_mipi_phy_nfmul_0_33	NF = 0.33.
k_ra8_mipi_phy_nfmul_0_66	NF = 0.66.
k_ra8_mipi_phy_nfmul_0_50	NF = 0.50.

Definition at line 165 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_pll_pmul_t

enum ra8_mipi_phy_pll_pmul_t : uint8_t

DPHYPLFCR.PMUL[1:0] – output frequency divisor.

HUM Ch 64.2.2 p 3823. Each value maps to a different VCO band (HUM 64.2.2 note p 3824). The driver enforces the band mapping via ra8_mipi_phy_validate_pll_band.

Enumerator
k_ra8_mipi_phy_pmul_1	P = 1 (960. . 1440 MHz).
k_ra8_mipi_phy_pmul_2	P = 1/2 (480. . 1440 MHz).
k_ra8_mipi_phy_pmul_4	P = 1/4 (240. . 750 MHz).
k_ra8_mipi_phy_pmul_8	P = 1/8 (120. . 375 MHz).

Definition at line 154 of file ra8_mipi_phy_types.h.

◆ ra8_mipi_phy_state_t

enum ra8_mipi_phy_state_t : uint8_t

Lifecycle position of the D-PHY block.

Tracks the start-up procedure (HUM Ch 64.3.1 p 3837) one stage at a time so that callers can reason about where the driver is without having to re-read DPHYSFR. State transitions follow the

State: Machine in ra8_mipi_phy_init.

Enumerator
k_ra8_mipi_phy_state_off	MSTPCRC bit set, regs unreachable.
k_ra8_mipi_phy_state_idle	MSTPCRC clear, no LDO yet.
k_ra8_mipi_phy_state_ldo_up	PWRSEN=1, PWRSF=1, PLL stopped.
k_ra8_mipi_phy_state_pll_run	PLLSTP=0, PLLSF=1, DPHYEN=0.
k_ra8_mipi_phy_state_run	DPHYEN=1, transmitting / receiving.
k_ra8_mipi_phy_state_error	LDO drop or PLL lost lock.

Definition at line 200 of file ra8_mipi_phy_types.h.

Data Structures

Typedefs

Enumerations