|
| ra8_err_t | ra8_mipi_phy_set_lane_speed (const ra8_mipi_phy_pll_t *pll) |
| | Reprogram the PLL coefficients (DPHYPLFCR) at runtime.
|
| ra8_err_t | ra8_mipi_phy_switch_mode (ra8_mipi_phy_mode_t mode) |
| | Switch the PHY between DSI host and CSI device mode.
|
| ra8_err_t | ra8_mipi_phy_set_lane_count (ra8_mipi_phy_lane_count_t count) |
| | Configure the active lane count.
|
| ra8_mipi_phy_lane_count_t | ra8_mipi_phy_get_lane_count (void) |
| | Read back the lane count last configured.
|
| ra8_err_t | ra8_mipi_phy_set_lane_enable (ra8_mipi_phy_lane_id_t lane, bool enable) |
| | Enable or disable a single data lane.
|
| bool | ra8_mipi_phy_is_lane_enabled (ra8_mipi_phy_lane_id_t lane) |
| | Query whether the given lane is currently enabled.
|
| ra8_err_t | ra8_mipi_phy_set_clock_mode (ra8_mipi_phy_clk_mode_t mode) |
| | Set the HS clock-lane mode (continuous vs non-continuous).
|
| ra8_mipi_phy_clk_mode_t | ra8_mipi_phy_get_clock_mode (void) |
| | Query the HS clock-lane mode last configured.
|
| ra8_err_t | ra8_mipi_phy_set_eotp (ra8_mipi_phy_eotp_t eotp) |
| | Set the EoTP packet emission preference (DSI host only).
|
| ra8_mipi_phy_eotp_t | ra8_mipi_phy_get_eotp (void) |
| | Query the EoTP setting last configured.
|
| ra8_err_t | ra8_mipi_phy_set_pclka_freq (uint8_t mhz) |
| | Update DPHYREFCR.RFREQ at runtime.
|
| ra8_err_t | ra8_mipi_phy_set_escape_divisor (uint8_t escdiv) |
| | Update DPHYESCCR.ESCDIV at runtime.
|
| ra8_err_t | ra8_mipi_phy_select_timing (ra8_mipi_phy_mode_t mode, uint8_t pclka_mhz, uint16_t rate_mbps, ra8_mipi_phy_timing_t *out_timing) |
| | Look up an HUM Table 64.2 / 64.3 row and apply the timing.
|
| ra8_err_t | ra8_mipi_phy_validate_pll_band (const ra8_mipi_phy_pll_t *pll, uint8_t mosc_mhz) |
| | Validate a PLL coefficient block against HUM 64.2.2 p 3823-3824.
|
| ra8_err_t | ra8_mipi_phy_compute_pll_freq (const ra8_mipi_phy_pll_t *pll, uint8_t mosc_mhz, uint32_t *out_mhz) |
| | Compute approximate PLL output frequency for a coefficient block.
|
| ra8_err_t | ra8_mipi_phy_lookup_timing (ra8_mipi_phy_mode_t mode, uint8_t pclka_mhz, uint16_t rate_mbps, ra8_mipi_phy_timing_t *out_timing) |
| | Look up an HUM Table 64.2 / 64.3 row WITHOUT writing the regs.
|
| ra8_err_t | ra8_mipi_phy_get_status_decoded (ra8_mipi_phy_status_decoded_t *out) |
| | Read DPHYSFR and decode it into a ra8_mipi_phy_status_decoded_t.
|
| ra8_mipi_phy_state_t | ra8_mipi_phy_get_state (void) |
| | Read the cached lifecycle state.
|
| ra8_mipi_phy_mode_t | ra8_mipi_phy_get_active_mode (void) |
| | Read the most recently configured operating mode.
|
| ra8_err_t | ra8_mipi_phy_set_dual_mode (ra8_mipi_phy_dual_mode_t mode) |
| | Set the dual-mode arbitration policy.
|
| ra8_mipi_phy_dual_mode_t | ra8_mipi_phy_get_dual_mode (void) |
| | Read back the dual-mode arbitration policy last configured.
|
| bool | ra8_mipi_phy_dual_mode_can_acquire (ra8_mipi_phy_mode_t requestor) |
| | Test whether a (mode, policy) request is currently allowed.
|
| ra8_err_t | ra8_mipi_phy_set_pclka_freq_hz (uint32_t hz) |
| | Update DPHYREFCR.RFREQ from a PCLKA frequency in Hz.
|
| ra8_err_t | ra8_mipi_phy_compute_lane_rate_mbps (const ra8_mipi_phy_pll_t *pll, uint8_t mosc_mhz, uint32_t *out_mbps) |
| | Compute (mosc, pll) -> approximate per-lane line rate.
|
MIPI D-PHY driver – runtime operations prototypes.
- Tag
- [Ring 3 / HAL] {World: NS}
Runtime operation entry points for the RA8D2 MIPI PHY block (HUM Ch 64, p 3822-3838): lane-speed re-tune, mode switching, lane and clock configuration, EoTP, PCLKA / escape-divisor updates, timing lookup, PLL math helpers, status decode, and dual-mode arbitration. The enums, structs, and callback typedef these prototypes reference live in ra8_mipi_phy_types.h, which this header includes. The lifecycle / status / interrupt / power prototypes live in ra8_mipi_phy_api.h. All three are re-exported by the thin umbrella ra8_mipi_phy.h.
- Copyright
- Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT
- Since
- 0.1.0
Definition in file ra8_mipi_phy_ops.h.
Look up an HUM Table 64.2 / 64.3 row and apply the timing.
Tables 64.2 (DSI mode, p 3831-3834) and 64.3 (CSI mode, p 3835-3836) map (PCLKA, lane_rate_mbps) to a ready-made set of DPHYTIMx field values. This helper picks the closest row, fills in a ra8_mipi_phy_timing_t, and writes DPHYTIM1..6.
- Parameters
-
| [in] | mode | Active mode (DSI vs CSI uses different tables). |
| [in] | pclka_mhz | PCLKA frequency in MHz. |
| [in] | rate_mbps | Per-lane line rate in Mbps. |
| [out] | out_timing | Optional non-NULL pointer to receive the applied timing block (skip with NULL). |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- Module-stop is cleared.
- Postcondition
- DPHYTIM1..6 hold the looked-up values.
- Note
- Thread safety: not thread-safe.
- Since
- 0.1.0
Definition at line 900 of file ra8_mipi_phy_timing.c.
References internal_mipi_phy_lookup_timing(), k_ra8_err_invalid_arg, k_ra8_err_not_supported, k_ra8_mipi_phy_line_rate_max_mbps, k_ra8_mipi_phy_line_rate_min_mbps, k_ra8_mipi_phy_mode_csi_device, k_ra8_mipi_phy_mode_dsi_host, k_ra8_ok, priv_mipi_phy_write_timing(), s_csi_table, and s_dsi_table.
| ra8_err_t ra8_mipi_phy_set_escape_divisor |
( |
uint8_t | escdiv | ) |
|
|
nodiscard |
Update DPHYESCCR.ESCDIV at runtime.
HUM Ch 64.2.4 p 3825: ESCDIV[4:0] must be written while DPHYPLOCR.PLLSTP = 1. This helper enforces that by stopping the PLL, writing the divisor, and restarting the PLL.
- Parameters
-
| [in] | escdiv | New escape divisor (0..31). |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- ra8_mipi_phy_init ran successfully (host mode).
- Postcondition
- DPHYESCCR.ESCDIV equals escdiv on success.
- Note
- Thread safety: not thread-safe.
- Since
- 0.1.0
Definition at line 791 of file ra8_mipi_phy.c.
References internal_mipi_phy_wait_set(), k_ra8_err_invalid_arg, k_ra8_mipi_phy_esccr_escdiv_mask, k_ra8_mipi_phy_escdiv_max, k_ra8_mipi_phy_off_esccr, k_ra8_mipi_phy_off_plocr, k_ra8_mipi_phy_off_sfr, k_ra8_mipi_phy_plocr_pllstp, k_ra8_mipi_phy_sfr_pllsf, and ra8_mipi_phy_reg32().
Configure the active lane count.
The PHY has no lane-count register of its own (the DSI / CSI host drivers gate individual lanes), so this helper only validates the argument against the silicon limit and stores it for later inspection through ra8_mipi_phy_get_lane_count. The value is also used by ra8_mipi_phy_set_lane_enable to bound checks.
- Parameters
-
| [in] | count | Desired lane count. |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- – (no preconditions).
- Postcondition
- ra8_mipi_phy_get_lane_count returns count on success.
- Note
- Thread safety: not thread-safe.
- Since
- 0.1.0
Definition at line 673 of file ra8_mipi_phy.c.
References k_ra8_err_invalid_arg, k_ra8_err_not_supported, k_ra8_mipi_phy_lane_bit_d1, k_ra8_mipi_phy_lane_count_1, k_ra8_mipi_phy_lane_count_2, k_ra8_mipi_phy_lane_count_3, k_ra8_mipi_phy_lane_count_4, k_ra8_ok, s_lane_count, and s_lane_enable_mask.
Enable or disable a single data lane.
Mirrors the per-lane gate that the DSI / CSI host drivers expose. The PHY itself has no per-lane register, so this helper only validates the index and stashes the request – the higher-level driver consults ra8_mipi_phy_is_lane_enabled when configuring its own lane gate.
- Parameters
-
| [in] | lane | Lane identifier. |
| [in] | enable | true to enable, false to disable. |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- – (no preconditions).
- Postcondition
- ra8_mipi_phy_is_lane_enabled returns enable on success.
- Note
- Thread safety: not thread-safe.
- Since
- 0.1.0
Definition at line 698 of file ra8_mipi_phy.c.
References k_ra8_err_invalid_arg, k_ra8_err_not_supported, k_ra8_mipi_phy_lane_bit_clk, k_ra8_mipi_phy_lane_bit_d0, k_ra8_mipi_phy_lane_bit_d1, k_ra8_mipi_phy_lane_clk, k_ra8_mipi_phy_lane_count_1, k_ra8_mipi_phy_lane_d0, k_ra8_mipi_phy_lane_d1, k_ra8_mipi_phy_lane_d2, k_ra8_mipi_phy_lane_d3, k_ra8_ok, s_lane_count, and s_lane_enable_mask.
Reprogram the PLL coefficients (DPHYPLFCR) at runtime.
HUM Ch 64.2.2 p 3824: DPHYPLFCR may only be written while DPHYPLOCR.PLLSTP = 1. This helper sets PLLSTP, writes DPHYPLFCR from pll, clears PLLSTP, and spins until DPHYSFR.PLLSF re-asserts. The D-PHY enable bit (DPHYOCR.DPHYEN) is left as it was on entry; callers transmitting active video should disable the lane outputs first.
- Parameters
-
| [in] | pll | Non-NULL PLL coefficient block. |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- pll is non-NULL.
-
ra8_mipi_phy_init has already run successfully.
- Postcondition
- On success, the PLL output frequency reflects the new coefficients and DPHYSFR.PLLSF reads 1.
- Note
- Thread safety: not thread-safe.
- Since
- 0.1.0
Definition at line 639 of file ra8_mipi_phy.c.
References internal_mipi_phy_pack_plfcr(), internal_mipi_phy_validate_pll(), internal_mipi_phy_wait_set(), k_ra8_mipi_phy_off_plfcr, k_ra8_mipi_phy_off_plocr, k_ra8_mipi_phy_off_sfr, k_ra8_mipi_phy_plocr_pllstp, k_ra8_mipi_phy_sfr_pllsf, RA8_CHECK_NULL_PTR, ra8_mipi_phy_reg32(), RA8_RETURN_ON_ERROR, and s_tag.
Validate a PLL coefficient block against HUM 64.2.2 p 3823-3824.
Checks the integer N range (40..375), then verifies the resulting PLL output frequency lies within the band selected by PMUL[1:0] (P=1: 960..1440, P=1/2: 480..1440, P=1/4: 240..750, P=1/8: 120..375). The MOSC frequency is taken from the parameter mosc_mhz so the check works without consulting the live CGC state.
- Parameters
-
| [in] | pll | Non-NULL PLL coefficient block. |
| [in] | mosc_mhz | MOSC frequency, MHz (8..48). |
- Returns
- ra8_err_t error code.
- Return values
-
- Precondition
- pll is non-NULL.
-
mosc_mhz is between 8 and 48.
- Postcondition
- Hardware state is unchanged.
- Note
- Pure function – safe to call from any context.
- Since
- 0.1.0
Definition at line 808 of file ra8_mipi_phy.c.
References internal_mipi_phy_validate_pll(), k_ra8_err_invalid_arg, k_ra8_mipi_phy_mosc_max_mhz, k_ra8_mipi_phy_mosc_min_mhz, k_ra8_mipi_phy_pll_p1_max, k_ra8_mipi_phy_pll_p1_min, k_ra8_mipi_phy_pll_p2_max, k_ra8_mipi_phy_pll_p2_min, k_ra8_mipi_phy_pll_p4_max, k_ra8_mipi_phy_pll_p4_min, k_ra8_mipi_phy_pll_p8_max, k_ra8_mipi_phy_pll_p8_min, k_ra8_mipi_phy_pmul_1, k_ra8_mipi_phy_pmul_2, k_ra8_mipi_phy_pmul_4, k_ra8_mipi_phy_pmul_8, k_ra8_ok, ra8_mipi_phy_pll_t::pmul, priv_mipi_phy_compute_freq(), RA8_CHECK_NULL_PTR, RA8_RETURN_ON_ERROR, and s_tag.
1.16.1