ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_mipi_phy_timing.c
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1
32
33#include <stdint.h>
34
35#include "ra8_attributes.h"
36#include "ra8_err.h"
37#include "ra8_mipi_phy.h"
38#include "ra8_mipi_phy_internal.h"
39#include "ra8_mipi_phy_regs.h"
40
48
49/* =============================================================================
50 * HUM Tables 64.2 / 64.3 (DSI / CSI) timing rows -- p 3831-3836
51 * =============================================================================
52 */
53
68typedef struct {
69 uint8_t mode;
70 uint8_t pclka;
71 uint16_t rate_max;
72 ra8_mipi_phy_timing_t t;
73} mipi_phy_table_row_t;
74
88
98static const mipi_phy_table_row_t s_dsi_table[] = {
99 /* HUM Table 64.2 PCLKA 125 MHz, p 3831-3832 */
100 {1U,
101 125U,
102 100U,
103 {0x000124F9U,
104 0x08U,
105 0x00U,
106 0x00U,
107 0x0FU,
108 0x00U,
109 0x21U,
110 0x0DU,
111 0x58U,
112 0x0AU,
113 0x0FU,
114 0x16U,
115 0x0EU,
116 0x08U}},
117 {1U,
118 125U,
119 150U,
120 {0x000124F9U,
121 0x08U,
122 0x00U,
123 0x00U,
124 0x0DU,
125 0x00U,
126 0x21U,
127 0x0DU,
128 0x58U,
129 0x0AU,
130 0x0FU,
131 0x11U,
132 0x0EU,
133 0x08U}},
134 {1U,
135 125U,
136 250U,
137 {0x000124F9U,
138 0x08U,
139 0x00U,
140 0x00U,
141 0x0BU,
142 0x00U,
143 0x21U,
144 0x0DU,
145 0x3AU,
146 0x08U,
147 0x0FU,
148 0x0CU,
149 0x0EU,
150 0x08U}},
151 {1U,
152 125U,
153 400U,
154 {0x000124F9U,
155 0x08U,
156 0x00U,
157 0x00U,
158 0x0AU,
159 0x00U,
160 0x21U,
161 0x04U,
162 0x3AU,
163 0x08U,
164 0x0FU,
165 0x09U,
166 0x0EU,
167 0x08U}},
168 {1U,
169 125U,
170 600U,
171 {0x000124F9U,
172 0x08U,
173 0x00U,
174 0x00U,
175 0x09U,
176 0x00U,
177 0x21U,
178 0x04U,
179 0x23U,
180 0x06U,
181 0x0FU,
182 0x08U,
183 0x0EU,
184 0x08U}},
185 {1U,
186 125U,
187 720U,
188 {0x000124F9U,
189 0x08U,
190 0x00U,
191 0x00U,
192 0x08U,
193 0x00U,
194 0x21U,
195 0x04U,
196 0x23U,
197 0x05U,
198 0x0FU,
199 0x07U,
200 0x0EU,
201 0x08U}},
202
203 /* HUM Table 64.2 PCLKA 120 MHz, p 3832 */
204 {1U,
205 120U,
206 100U,
207 {0x00011941U,
208 0x08U,
209 0x00U,
210 0x00U,
211 0x0EU,
212 0x00U,
213 0x20U,
214 0x0DU,
215 0x58U,
216 0x0AU,
217 0x0FU,
218 0x15U,
219 0x0DU,
220 0x08U}},
221 {1U,
222 120U,
223 150U,
224 {0x00011941U,
225 0x08U,
226 0x00U,
227 0x00U,
228 0x0CU,
229 0x00U,
230 0x20U,
231 0x0DU,
232 0x58U,
233 0x0AU,
234 0x0FU,
235 0x10U,
236 0x0DU,
237 0x08U}},
238 {1U,
239 120U,
240 250U,
241 {0x00011941U,
242 0x08U,
243 0x00U,
244 0x00U,
245 0x0AU,
246 0x00U,
247 0x20U,
248 0x0DU,
249 0x3AU,
250 0x08U,
251 0x0FU,
252 0x0BU,
253 0x0DU,
254 0x08U}},
255 {1U,
256 120U,
257 400U,
258 {0x00011941U,
259 0x08U,
260 0x00U,
261 0x00U,
262 0x09U,
263 0x00U,
264 0x20U,
265 0x04U,
266 0x3AU,
267 0x07U,
268 0x0FU,
269 0x08U,
270 0x0DU,
271 0x08U}},
272 {1U,
273 120U,
274 600U,
275 {0x00011941U,
276 0x08U,
277 0x00U,
278 0x00U,
279 0x09U,
280 0x00U,
281 0x20U,
282 0x04U,
283 0x23U,
284 0x06U,
285 0x0FU,
286 0x07U,
287 0x0DU,
288 0x08U}},
289 {1U,
290 120U,
291 720U,
292 {0x00011941U,
293 0x08U,
294 0x00U,
295 0x00U,
296 0x08U,
297 0x00U,
298 0x20U,
299 0x04U,
300 0x23U,
301 0x05U,
302 0x0FU,
303 0x06U,
304 0x0DU,
305 0x08U}},
306
307 /* HUM Table 64.2 PCLKA 100 MHz, p 3833 */
308 {1U,
309 100U,
310 100U,
311 {0x0000EA61U,
312 0x06U,
313 0x00U,
314 0x00U,
315 0x0CU,
316 0x00U,
317 0x1CU,
318 0x0CU,
319 0x46U,
320 0x0AU,
321 0x0CU,
322 0x10U,
323 0x0CU,
324 0x08U}},
325 {1U,
326 100U,
327 150U,
328 {0x0000EA61U,
329 0x06U,
330 0x00U,
331 0x00U,
332 0x0AU,
333 0x00U,
334 0x1CU,
335 0x0CU,
336 0x46U,
337 0x07U,
338 0x0CU,
339 0x0BU,
340 0x0CU,
341 0x08U}},
342 {1U,
343 100U,
344 250U,
345 {0x0000EA61U,
346 0x06U,
347 0x00U,
348 0x00U,
349 0x08U,
350 0x00U,
351 0x1CU,
352 0x0CU,
353 0x32U,
354 0x06U,
355 0x0CU,
356 0x08U,
357 0x0CU,
358 0x08U}},
359 {1U,
360 100U,
361 400U,
362 {0x0000EA61U,
363 0x06U,
364 0x00U,
365 0x00U,
366 0x07U,
367 0x00U,
368 0x1CU,
369 0x04U,
370 0x22U,
371 0x04U,
372 0x0CU,
373 0x06U,
374 0x0CU,
375 0x08U}},
376 {1U,
377 100U,
378 600U,
379 {0x0000EA61U,
380 0x06U,
381 0x00U,
382 0x00U,
383 0x07U,
384 0x00U,
385 0x1CU,
386 0x04U,
387 0x22U,
388 0x04U,
389 0x0CU,
390 0x05U,
391 0x0CU,
392 0x08U}},
393 {1U,
394 100U,
395 720U,
396 {0x0000EA61U,
397 0x06U,
398 0x00U,
399 0x00U,
400 0x07U,
401 0x00U,
402 0x1CU,
403 0x04U,
404 0x22U,
405 0x03U,
406 0x0CU,
407 0x05U,
408 0x0CU,
409 0x08U}},
410
411 /* HUM Table 64.2 PCLKA 80 MHz, p 3833 */
412 {1U,
413 80U,
414 100U,
415 {0x0000BB81U,
416 0x05U,
417 0x00U,
418 0x00U,
419 0x09U,
420 0x00U,
421 0x17U,
422 0x0AU,
423 0x3AU,
424 0x07U,
425 0x0AU,
426 0x0CU,
427 0x0AU,
428 0x07U}},
429 {1U,
430 80U,
431 150U,
432 {0x0000BB81U,
433 0x05U,
434 0x00U,
435 0x00U,
436 0x08U,
437 0x00U,
438 0x17U,
439 0x0AU,
440 0x2EU,
441 0x05U,
442 0x0AU,
443 0x08U,
444 0x0AU,
445 0x07U}},
446 {1U,
447 80U,
448 250U,
449 {0x0000BB81U,
450 0x05U,
451 0x00U,
452 0x00U,
453 0x07U,
454 0x00U,
455 0x17U,
456 0x04U,
457 0x2EU,
458 0x04U,
459 0x0AU,
460 0x06U,
461 0x0AU,
462 0x07U}},
463 {1U,
464 80U,
465 400U,
466 {0x0000BB81U,
467 0x05U,
468 0x00U,
469 0x00U,
470 0x06U,
471 0x00U,
472 0x17U,
473 0x04U,
474 0x1CU,
475 0x03U,
476 0x0AU,
477 0x04U,
478 0x0AU,
479 0x07U}},
480 {1U,
481 80U,
482 600U,
483 {0x0000BB81U,
484 0x05U,
485 0x00U,
486 0x00U,
487 0x05U,
488 0x00U,
489 0x17U,
490 0x04U,
491 0x1CU,
492 0x02U,
493 0x0AU,
494 0x04U,
495 0x0AU,
496 0x07U}},
497 {1U,
498 80U,
499 720U,
500 {0x0000BB81U,
501 0x05U,
502 0x00U,
503 0x00U,
504 0x05U,
505 0x00U,
506 0x17U,
507 0x04U,
508 0x1CU,
509 0x02U,
510 0x0AU,
511 0x04U,
512 0x0AU,
513 0x07U}},
514
515 /* HUM Table 64.2 PCLKA 75 MHz, p 3834 */
516 {1U,
517 75U,
518 100U,
519 {0x0000AFC9U,
520 0x05U,
521 0x00U,
522 0x00U,
523 0x08U,
524 0x00U,
525 0x14U,
526 0x08U,
527 0x37U,
528 0x06U,
529 0x0AU,
530 0x0BU,
531 0x0AU,
532 0x07U}},
533 {1U,
534 75U,
535 150U,
536 {0x0000AFC9U,
537 0x05U,
538 0x00U,
539 0x00U,
540 0x07U,
541 0x00U,
542 0x14U,
543 0x08U,
544 0x2BU,
545 0x04U,
546 0x0AU,
547 0x08U,
548 0x0AU,
549 0x07U}},
550 {1U,
551 75U,
552 250U,
553 {0x0000AFC9U,
554 0x05U,
555 0x00U,
556 0x00U,
557 0x06U,
558 0x00U,
559 0x14U,
560 0x03U,
561 0x2BU,
562 0x03U,
563 0x0AU,
564 0x05U,
565 0x0AU,
566 0x07U}},
567 {1U,
568 75U,
569 400U,
570 {0x0000AFC9U,
571 0x05U,
572 0x00U,
573 0x00U,
574 0x05U,
575 0x00U,
576 0x14U,
577 0x03U,
578 0x19U,
579 0x02U,
580 0x0AU,
581 0x04U,
582 0x0AU,
583 0x07U}},
584 {1U,
585 75U,
586 600U,
587 {0x0000AFC9U,
588 0x05U,
589 0x00U,
590 0x00U,
591 0x05U,
592 0x00U,
593 0x14U,
594 0x03U,
595 0x19U,
596 0x02U,
597 0x0AU,
598 0x04U,
599 0x0AU,
600 0x07U}},
601 {1U,
602 75U,
603 720U,
604 {0x0000AFC9U,
605 0x05U,
606 0x00U,
607 0x00U,
608 0x05U,
609 0x00U,
610 0x14U,
611 0x03U,
612 0x19U,
613 0x01U,
614 0x0AU,
615 0x04U,
616 0x0AU,
617 0x07U}},
618
619 /* HUM Table 64.2 PCLKA 40 MHz, p 3834 */
620 {1U,
621 40U,
622 100U,
623 {0x00005DC1U,
624 0x02U,
625 0x00U,
626 0x00U,
627 0x04U,
628 0x00U,
629 0x0CU,
630 0x02U,
631 0x20U,
632 0x01U,
633 0x05U,
634 0x03U,
635 0x05U,
636 0x05U}},
637 {1U,
638 40U,
639 150U,
640 {0x00005DC1U,
641 0x02U,
642 0x00U,
643 0x00U,
644 0x03U,
645 0x00U,
646 0x0CU,
647 0x02U,
648 0x1AU,
649 0x01U,
650 0x05U,
651 0x02U,
652 0x05U,
653 0x05U}},
654 {1U,
655 40U,
656 250U,
657 {0x00005DC1U,
658 0x02U,
659 0x00U,
660 0x00U,
661 0x03U,
662 0x00U,
663 0x0CU,
664 0x00U,
665 0x1AU,
666 0x00U,
667 0x05U,
668 0x02U,
669 0x05U,
670 0x05U}},
671 {1U,
672 40U,
673 400U,
674 {0x00005DC1U,
675 0x02U,
676 0x00U,
677 0x00U,
678 0x02U,
679 0x00U,
680 0x0CU,
681 0x00U,
682 0x0CU,
683 0x00U,
684 0x05U,
685 0x02U,
686 0x05U,
687 0x05U}},
688 {1U,
689 40U,
690 600U,
691 {0x00005DC1U,
692 0x02U,
693 0x00U,
694 0x00U,
695 0x02U,
696 0x00U,
697 0x0CU,
698 0x00U,
699 0x0CU,
700 0x00U,
701 0x05U,
702 0x02U,
703 0x05U,
704 0x05U}},
705 {1U,
706 40U,
707 720U,
708 {0x00005DC1U,
709 0x02U,
710 0x00U,
711 0x00U,
712 0x02U,
713 0x00U,
714 0x0CU,
715 0x00U,
716 0x0CU,
717 0x00U,
718 0x05U,
719 0x02U,
720 0x05U,
721 0x05U}},
722};
723
734static const mipi_phy_table_row_t s_csi_table[] = {
735 /* HUM Table 64.3 PCLKA 125 MHz, p 3835 */
736 {0U, 125U, 90U, {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x12U, 0x12U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
737 {0U,
738 125U,
739 100U,
740 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x11U, 0x11U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
741 {0U,
742 125U,
743 130U,
744 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x10U, 0x10U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
745 {0U,
746 125U,
747 200U,
748 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x0FU, 0x0FU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
749 {0U,
750 125U,
751 300U,
752 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x0DU, 0x0EU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
753 {0U,
754 125U,
755 400U,
756 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x0CU, 0x0DU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
757 {0U,
758 125U,
759 700U,
760 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x0BU, 0x0CU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
761 {0U,
762 125U,
763 720U,
764 {0x000124F9U, 0x11U, 0x19U, 0x03U, 0x0AU, 0x0BU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
765
766 /* HUM Table 64.3 PCLKA 120 MHz, p 3835 */
767 {0U, 120U, 90U, {0x00011941U, 0x10U, 0x18U, 0x03U, 0x11U, 0x11U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
768 {0U,
769 120U,
770 100U,
771 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x10U, 0x10U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
772 {0U,
773 120U,
774 130U,
775 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x0FU, 0x0FU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
776 {0U,
777 120U,
778 200U,
779 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x0EU, 0x0EU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
780 {0U,
781 120U,
782 300U,
783 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x0CU, 0x0DU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
784 {0U,
785 120U,
786 400U,
787 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x0BU, 0x0CU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
788 {0U,
789 120U,
790 700U,
791 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x0AU, 0x0BU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
792 {0U,
793 120U,
794 720U,
795 {0x00011941U, 0x10U, 0x18U, 0x03U, 0x09U, 0x0AU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
796
797 /* HUM Table 64.3 PCLKA 100 MHz, p 3835 */
798 {0U, 100U, 90U, {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x0EU, 0x0EU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
799 {0U,
800 100U,
801 100U,
802 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x0DU, 0x0DU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
803 {0U,
804 100U,
805 130U,
806 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x0CU, 0x0CU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
807 {0U,
808 100U,
809 200U,
810 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x0BU, 0x0BU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
811 {0U,
812 100U,
813 300U,
814 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x0AU, 0x0AU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
815 {0U,
816 100U,
817 400U,
818 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x09U, 0x09U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
819 {0U,
820 100U,
821 700U,
822 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x08U, 0x08U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
823 {0U,
824 100U,
825 720U,
826 {0x0000EA61U, 0x0DU, 0x13U, 0x02U, 0x08U, 0x07U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
827
828 /* HUM Table 64.3 PCLKA 80 MHz, p 3835-3836 */
829 {0U, 80U, 90U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x0AU, 0x0AU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
830 {0U, 80U, 100U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x0AU, 0x0AU, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
831 {0U, 80U, 130U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x09U, 0x09U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
832 {0U, 80U, 200U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x08U, 0x08U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
833 {0U, 80U, 300U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x07U, 0x07U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
834 {0U, 80U, 400U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x07U, 0x07U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
835 {0U, 80U, 700U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x06U, 0x06U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
836 {0U, 80U, 720U, {0x0000BB81U, 0x0AU, 0x0FU, 0x01U, 0x06U, 0x05U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
837
838 /* HUM Table 64.3 PCLKA 75 MHz, p 3836 */
839 {0U, 75U, 90U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x09U, 0x09U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
840 {0U, 75U, 100U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x09U, 0x09U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
841 {0U, 75U, 130U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x08U, 0x08U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
842 {0U, 75U, 200U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x07U, 0x07U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
843 {0U, 75U, 300U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x06U, 0x06U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
844 {0U, 75U, 400U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x06U, 0x06U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
845 {0U, 75U, 700U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x06U, 0x05U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
846 {0U, 75U, 720U, {0x0000AFC9U, 0x0AU, 0x0EU, 0x01U, 0x06U, 0x05U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
847
848 /* HUM Table 64.3 PCLKA 50 MHz, p 3836 */
849 {0U, 50U, 90U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x05U, 0x05U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
850 {0U, 50U, 100U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x05U, 0x05U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
851 {0U, 50U, 130U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x04U, 0x04U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
852 {0U, 50U, 200U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x04U, 0x04U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
853 {0U, 50U, 300U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x03U, 0x03U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
854 {0U, 50U, 400U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x03U, 0x03U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
855 {0U, 50U, 700U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x03U, 0x03U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
856 {0U, 50U, 720U, {0x00007531U, 0x06U, 0x08U, 0x01U, 0x02U, 0x02U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}},
857};
858
864RA8_INTERNAL
865static const ra8_mipi_phy_timing_t* internal_mipi_phy_lookup_timing(const mipi_phy_table_row_t* tbl,
866 uint32_t n,
867 uint8_t pclka,
868 uint16_t rate_mbps,
869 uint8_t mode_flag)
870{
871 for (uint32_t i = 0U; i < n; ++i) {
872 // mcdc-deactivated: internal_mipi_phy_lookup_timing 3-condition row matcher; the static table carries one mode value per table, so tbl[i].mode == mode_flag is invariant across every row a given call scans -- that condition cannot be flipped independently while pclka and rate_max remain matchable.
873 if ((tbl[i].mode == mode_flag) && (tbl[i].pclka == pclka) && (tbl[i].rate_max >= rate_mbps)) {
874 return &tbl[i].t;
875 }
876 }
877 return nullptr;
878}
879
880uint32_t priv_mipi_phy_compute_freq(const ra8_mipi_phy_pll_t* pll, uint8_t mosc_mhz)
881{
882 /* HUM Ch 64.2.2 p 3823 -- f = fMAIN * I * (NF + N) * P. */
883 static const uint8_t local_idiv_div[] = {1U, 2U, 3U, 4U};
884 static const uint8_t local_pmul_div[] = {1U, 2U, 4U, 8U};
885 static const uint16_t local_nfmul_x100[] = {0U,
886 k_mipi_nf_x100_33,
887 k_mipi_nf_x100_66,
888 k_mipi_nf_x100_50}; /* hundredths */
889
890 const uint32_t idiv = (uint32_t)local_idiv_div[(uint8_t)pll->idiv & 0x3U];
891 const uint32_t pmul = (uint32_t)local_pmul_div[(uint8_t)pll->pmul & 0x3U];
892 const uint32_t nf_x100 = (uint32_t)local_nfmul_x100[(uint8_t)pll->nfmul & 0x3U];
893 const uint32_t n_x100 = ((uint32_t)pll->nmul_int * k_mipi_pll_percent_scale) + nf_x100;
894 /* f_mhz = mosc_mhz * (n_x100/100) / idiv / pmul */
895 const uint32_t numerator = (uint32_t)mosc_mhz * n_x100;
896 const uint32_t denom = idiv * pmul * k_mipi_pll_percent_scale;
897 return (denom == 0U) ? 0U : (numerator / denom);
898}
899
900ra8_err_t ra8_mipi_phy_select_timing(ra8_mipi_phy_mode_t mode,
901 uint8_t pclka_mhz,
902 uint16_t rate_mbps,
903 ra8_mipi_phy_timing_t* const out_timing)
904{
905 if ((mode != k_ra8_mipi_phy_mode_dsi_host) && (mode != k_ra8_mipi_phy_mode_csi_device)) {
906 return k_ra8_err_invalid_arg;
907 }
908 /* HUM Ch 64.1 "Overview" p 3822 */
909 if ((rate_mbps < k_ra8_mipi_phy_line_rate_min_mbps) ||
910 (rate_mbps > k_ra8_mipi_phy_line_rate_max_mbps)) {
911 return k_ra8_err_invalid_arg;
912 }
913
914 const ra8_mipi_phy_timing_t* row;
915 if (mode == k_ra8_mipi_phy_mode_dsi_host) {
916 /* HUM Table 64.2 "D-PHY timing setting DSI mode", p 3831-3834 */
917 row = internal_mipi_phy_lookup_timing(s_dsi_table,
918 sizeof(s_dsi_table) / sizeof(s_dsi_table[0]),
919 pclka_mhz,
920 rate_mbps,
921 1U);
922 } else {
923 /* HUM Table 64.3 "D-PHY timing setting CSI mode", p 3835-3836 */
924 row = internal_mipi_phy_lookup_timing(s_csi_table,
925 sizeof(s_csi_table) / sizeof(s_csi_table[0]),
926 pclka_mhz,
927 rate_mbps,
928 0U);
929 }
930 if (row == nullptr) {
931 return k_ra8_err_not_supported;
932 }
933 priv_mipi_phy_write_timing(row);
934 if (out_timing != nullptr) {
935 *out_timing = *row;
936 }
937 return k_ra8_ok;
938}
ra8_attributes.h
Annotation-attribute framework macros for ra8-firmware.
RA8_INTERNAL
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Definition ra8_attributes.h:190
ra8_err.h
Error Code Definitions for ra8-firmware.
k_ra8_err_not_supported
@ k_ra8_err_not_supported
Requested feature not compiled in, not wired, or not supported by this MCU variant.
Definition ra8_err.h:180
k_ra8_err_invalid_arg
@ k_ra8_err_invalid_arg
Invalid function argument.
Definition ra8_err.h:152
k_ra8_ok
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_t
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
priv_mipi_phy_write_timing
void priv_mipi_phy_write_timing(const ra8_mipi_phy_timing_t *t)
Implementation of priv_mipi_phy_write_timing() – packs DPHYTIM1..6.
Definition ra8_mipi_phy.c:248
ra8_mipi_phy.h
MIPI D-PHY driver – physical layer shared by DSI and CSI.
ra8_mipi_phy_internal.h
Module-private link seam shared between the MIPI D-PHY drivertranslation units.
ra8_mipi_phy_regs.h
MIPI D-PHY register layout for the RA8D2.
k_ra8_mipi_phy_line_rate_max_mbps
@ k_ra8_mipi_phy_line_rate_max_mbps
Upper line-rate limit.
Definition ra8_mipi_phy_regs.h:280
k_ra8_mipi_phy_line_rate_min_mbps
@ k_ra8_mipi_phy_line_rate_min_mbps
Lower line-rate limit.
Definition ra8_mipi_phy_regs.h:279
s_dsi_table
static const mipi_phy_table_row_t s_dsi_table[]
HUM Table 64.2 D-PHY timing setting DSI mode (p 3831-3834).
Definition ra8_mipi_phy_timing.c:98
mipi_pll_frac_t
mipi_pll_frac_t
PLL fixed-point (hundredths) scale and NF fractional table.
Definition ra8_mipi_phy_timing.c:42
k_mipi_nf_x100_50
@ k_mipi_nf_x100_50
NF = 0.50 (x100).
Definition ra8_mipi_phy_timing.c:46
k_mipi_pll_percent_scale
@ k_mipi_pll_percent_scale
Hundredths fixed-point scale.
Definition ra8_mipi_phy_timing.c:43
k_mipi_nf_x100_66
@ k_mipi_nf_x100_66
NF = 0.66 (x100).
Definition ra8_mipi_phy_timing.c:45
k_mipi_nf_x100_33
@ k_mipi_nf_x100_33
NF = 0.33 (x100).
Definition ra8_mipi_phy_timing.c:44
s_csi_table
static const mipi_phy_table_row_t s_csi_table[]
HUM Table 64.3 D-PHY timing setting CSI mode (p 3835-3836).
Definition ra8_mipi_phy_timing.c:734
ra8_mipi_phy_select_timing
ra8_err_t ra8_mipi_phy_select_timing(ra8_mipi_phy_mode_t mode, uint8_t pclka_mhz, uint16_t rate_mbps, ra8_mipi_phy_timing_t *const out_timing)
Look up an HUM Table 64.2 / 64.3 row and apply the timing.
Definition ra8_mipi_phy_timing.c:900
priv_mipi_phy_compute_freq
uint32_t priv_mipi_phy_compute_freq(const ra8_mipi_phy_pll_t *pll, uint8_t mosc_mhz)
Compute the PLL output frequency for a (mosc, pll) tuple.
Definition ra8_mipi_phy_timing.c:880
ra8_mipi_phy_table_szlim_t
ra8_mipi_phy_table_szlim_t
Static lookup-table cardinalities.
Definition ra8_mipi_phy_timing.c:79
k_ra8_mipi_phy_table_pclka_75
@ k_ra8_mipi_phy_table_pclka_75
PCLKA 75 MHz bucket.
Definition ra8_mipi_phy_timing.c:84
k_ra8_mipi_phy_table_pclka_50
@ k_ra8_mipi_phy_table_pclka_50
PCLKA 50 MHz bucket.
Definition ra8_mipi_phy_timing.c:85
k_ra8_mipi_phy_table_pclka_125
@ k_ra8_mipi_phy_table_pclka_125
PCLKA 125 MHz bucket.
Definition ra8_mipi_phy_timing.c:80
k_ra8_mipi_phy_table_pclka_120
@ k_ra8_mipi_phy_table_pclka_120
PCLKA 120 MHz bucket.
Definition ra8_mipi_phy_timing.c:81
k_ra8_mipi_phy_table_pclka_40
@ k_ra8_mipi_phy_table_pclka_40
PCLKA 40 MHz bucket.
Definition ra8_mipi_phy_timing.c:86
k_ra8_mipi_phy_table_pclka_80
@ k_ra8_mipi_phy_table_pclka_80
PCLKA 80 MHz bucket.
Definition ra8_mipi_phy_timing.c:83
k_ra8_mipi_phy_table_pclka_100
@ k_ra8_mipi_phy_table_pclka_100
PCLKA 100 MHz bucket.
Definition ra8_mipi_phy_timing.c:82
internal_mipi_phy_lookup_timing
static const ra8_mipi_phy_timing_t * internal_mipi_phy_lookup_timing(const mipi_phy_table_row_t *tbl, uint32_t n, uint8_t pclka, uint16_t rate_mbps, uint8_t mode_flag)
Lookup helper – linear scan picks the first row whose rate_max is >= the requested rate within a matc...
Definition ra8_mipi_phy_timing.c:865
ra8_mipi_phy_mode_t
ra8_mipi_phy_mode_t
D-PHY host vs device mode select (DPHYMDC.MASTEREN).
Definition ra8_mipi_phy_types.h:41
k_ra8_mipi_phy_mode_csi_device
@ k_ra8_mipi_phy_mode_csi_device
Device mode used by MIPI CSI.
Definition ra8_mipi_phy_types.h:42
k_ra8_mipi_phy_mode_dsi_host
@ k_ra8_mipi_phy_mode_dsi_host
Host mode used by MIPI DSI.
Definition ra8_mipi_phy_types.h:43
mipi_phy_table_row_t
One row of HUM Tables 64.2 / 64.3 with the rate ceiling.
Definition ra8_mipi_phy_timing.c:68
mipi_phy_table_row_t::t
ra8_mipi_phy_timing_t t
Timing values for the row.
Definition ra8_mipi_phy_timing.c:72
mipi_phy_table_row_t::pclka
uint8_t pclka
PCLKA in MHz.
Definition ra8_mipi_phy_timing.c:70
mipi_phy_table_row_t::mode
uint8_t mode
0 = CSI device, 1 = DSI host.
Definition ra8_mipi_phy_timing.c:69
mipi_phy_table_row_t::rate_max
uint16_t rate_max
Ceiling of the rate column.
Definition ra8_mipi_phy_timing.c:71
ra8_mipi_phy_pll_t
D-PHY PLL coefficients written into DPHYPLFCR.
Definition ra8_mipi_phy_types.h:267
ra8_mipi_phy_pll_t::pmul
ra8_mipi_phy_pll_pmul_t pmul
PMUL[1:0] output divisor.
Definition ra8_mipi_phy_types.h:269
ra8_mipi_phy_pll_t::nfmul
ra8_mipi_phy_pll_nfmul_t nfmul
NFMUL[1:0] fractional N.
Definition ra8_mipi_phy_types.h:270
ra8_mipi_phy_pll_t::nmul_int
uint16_t nmul_int
NMUL[8:0] integer N (40..375).
Definition ra8_mipi_phy_types.h:271
ra8_mipi_phy_pll_t::idiv
ra8_mipi_phy_pll_idiv_t idiv
IDIV[1:0] input divisor.
Definition ra8_mipi_phy_types.h:268
ra8_mipi_phy_timing_t
D-PHY HS/LP transition timing values (DPHYTIM1..6).
Definition ra8_mipi_phy_types.h:287