MIPI D-PHY register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_glcdc_regs.h"

Include dependency graph for ra8_mipi_phy_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_mipi_phy_block_off_t : uint16_t { k_ra8_mipi_phy_off_refcr = 0x000U , k_ra8_mipi_phy_off_plfcr = 0x004U , k_ra8_mipi_phy_off_plocr = 0x008U , k_ra8_mipi_phy_off_esccr = 0x00CU , k_ra8_mipi_phy_off_pwrcr = 0x010U , k_ra8_mipi_phy_off_sfr = 0x01CU , k_ra8_mipi_phy_off_ocr = 0x020U , k_ra8_mipi_phy_off_tim1 = 0x024U , k_ra8_mipi_phy_off_tim2 = 0x028U , k_ra8_mipi_phy_off_tim3 = 0x02CU , k_ra8_mipi_phy_off_tim4 = 0x030U , k_ra8_mipi_phy_off_tim5 = 0x034U , k_ra8_mipi_phy_off_tim6 = 0x038U , k_ra8_mipi_phy_off_mdc = 0x048U }
	32-bit register offsets inside the MIPI PHY window. More...
enum	ra8_mipi_phy_pwrcr_bit_t : uint32_t { k_ra8_mipi_phy_pwrcr_pwrsen = 0x1U }
	DPHYPWRCR bit positions / masks. More...
enum	ra8_mipi_phy_plocr_bit_t : uint32_t { k_ra8_mipi_phy_plocr_pllstp = 0x1U }
	DPHYPLOCR bit positions / masks. More...
enum	ra8_mipi_phy_ocr_bit_t : uint32_t { k_ra8_mipi_phy_ocr_dphyen = 0x1U }
	DPHYOCR bit positions / masks. More...
enum	ra8_mipi_phy_sfr_bit_t : uint32_t { k_ra8_mipi_phy_sfr_pwrsf = 0x001U , k_ra8_mipi_phy_sfr_pllsf = 0x100U , k_ra8_mipi_phy_sfr_ready_mask = 0x101U }
	DPHYSFR status flag positions / masks (read-only). More...
enum	ra8_mipi_phy_mdc_bit_t : uint32_t { k_ra8_mipi_phy_mdc_hosten = 0x1U }
	DPHYMDC bit positions / masks. More...
enum	ra8_mipi_phy_refcr_mask_t : uint32_t { k_ra8_mipi_phy_refcr_rfreq_mask = 0xFFU }
	DPHYREFCR field masks. More...
enum	ra8_mipi_phy_refcr_bias_t : uint8_t { k_ra8_mipi_phy_refcr_rfreq_bias = 1U }
	Software-side bias used when encoding DPHYREFCR.RFREQ. More...
enum	ra8_mipi_phy_esccr_mask_t : uint32_t { k_ra8_mipi_phy_esccr_escdiv_mask = 0x1FU }
	DPHYESCCR field masks. More...
enum	ra8_mipi_phy_tim1_mask_t : uint32_t { k_ra8_mipi_phy_tim1_tinit_mask = 0x0007FFFFUL }
	DPHYTIM1 field masks. More...
enum	ra8_mipi_phy_tim_byte_shift_t : uint8_t { k_ra8_mipi_phy_tim_shift_b0 = 0U , k_ra8_mipi_phy_tim_shift_b1 = 8U , k_ra8_mipi_phy_tim_shift_b2 = 16U , k_ra8_mipi_phy_tim_shift_b3 = 24U }
	Generic 8-bit byte-lane shifts used inside DPHYTIM2..5. More...
enum	ra8_mipi_phy_tim_byte_mask_t : uint32_t { k_ra8_mipi_phy_tim_byte_mask = 0xFFU }
	8-bit per-field mask applied before shifting in DPHYTIM2..5. More...
enum	ra8_mipi_phy_tim6_mask_t : uint32_t { k_ra8_mipi_phy_tim6_tlpx_mask = 0xFFU }
	DPHYTIM6 field masks. More...
enum	ra8_mipi_phy_pll_field_shift_t : uint8_t { k_ra8_mipi_phy_plfcr_shift_idiv = 0U , k_ra8_mipi_phy_plfcr_shift_nfmul = 8U , k_ra8_mipi_phy_plfcr_shift_pmul = 12U , k_ra8_mipi_phy_plfcr_shift_nmul = 16U }
	DPHYPLFCR field positions. More...
enum	ra8_mipi_phy_pll_field_mask_t : uint32_t { k_ra8_mipi_phy_plfcr_mask_idiv = 0x003U , k_ra8_mipi_phy_plfcr_mask_nfmul = 0x003U , k_ra8_mipi_phy_plfcr_mask_pmul = 0x003U , k_ra8_mipi_phy_plfcr_mask_nmul = 0x1FFU }
	DPHYPLFCR field width masks (pre-shift, applied to value). More...
enum	ra8_mipi_phy_lane_speed_limit_t : uint16_t { k_ra8_mipi_phy_line_rate_min_mbps = 80U , k_ra8_mipi_phy_line_rate_max_mbps = 720U }
	Per-lane line-rate guardrails (Mbps). More...
enum	ra8_mipi_phy_pll_band_t : uint16_t { k_ra8_mipi_phy_vco_min_mhz = 960U , k_ra8_mipi_phy_vco_max_mhz = 3000U , k_ra8_mipi_phy_pll_p1_min = 960U , k_ra8_mipi_phy_pll_p1_max = 1440U , k_ra8_mipi_phy_pll_p2_min = 480U , k_ra8_mipi_phy_pll_p2_max = 1440U , k_ra8_mipi_phy_pll_p4_min = 240U , k_ra8_mipi_phy_pll_p4_max = 750U , k_ra8_mipi_phy_pll_p8_min = 120U , k_ra8_mipi_phy_pll_p8_max = 375U }
	VCO frequency band guardrails (HUM Ch 64.1 Table 64.1 p 3822). More...
enum	ra8_mipi_phy_input_clk_t : uint8_t { k_ra8_mipi_phy_mosc_min_mhz = 8U , k_ra8_mipi_phy_mosc_max_mhz = 48U , k_ra8_mipi_phy_pll_in_min_mhz = 8U , k_ra8_mipi_phy_pll_in_max_mhz = 24U , k_ra8_mipi_phy_lp_clk_min_mhz = 2U , k_ra8_mipi_phy_lp_clk_max_mhz = 17U }
	Input clock guardrails to PLL (HUM Ch 64.1 Table 64.1 p 3822). More...

Functions
static volatile uint32_t *	ra8_mipi_phy_reg32 (ra8_mipi_phy_block_off_t offset)
	Pointer to a 32-bit MIPI PHY register at the given offset.

Detailed Description

MIPI D-PHY register layout for the RA8D2.

The MIPI PHY block at MMIO base 0x4034_6C00 is the physical layer shared by the MIPI DSI host (Ch 65) and the MIPI CSI receiver (Ch 66). It implements MIPI Alliance Specification v2.1 D-PHY with up to 2 lanes at a maximum line rate of 720 Mbps/lane (HUM Ch 64.1 "Overview" Table 64.1, p 3822).

The block exposes a small set of 32-bit registers (HUM Ch 64.2 "Register Description" notes "Access the following registers only in units of 32 bits.", p 3822):

Offset	Name	Purpose
0x000	DPHYREFCR	Reference clock setting (PCLKA MHz)
0x004	DPHYPLFCR	PLL frequency control (I/N/NF/P)
0x008	DPHYPLOCR	PLL operation control (PLLSTP)
0x00C	DPHYESCCR	Escape mode clock divisor (ESCDIV)
0x010	DPHYPWRCR	LDO power supply control (PWRSEN)
0x01C	DPHYSFR	Status flags (PWRSF, PLLSF) – RO
0x020	DPHYOCR	Operation control (DPHYEN)
0x024	DPHYTIM1	TINIT timing
0x028	DPHYTIM2	TCLK_PREP/SETT/MISS timing
0x02C	DPHYTIM3	THS_PREP/SETT timing
0x030	DPHYTIM4	TCLK_ZERO/PRE/POST/TRAIL timing
0x034	DPHYTIM5	THS_ZERO/TRAIL/EXIT timing
0x038	DPHYTIM6	TLPX timing
0x048	DPHYMDC	Host/device mode (DSI vs CSI)

Cross-checked against FSP R_MIPI_PHY register list in r_mipi_phy.c and the bit-field definitions in the FSP r_mipi_phy.h instance header.

Note: k_ra8_mipi_phy_base_addr is already declared in ra8_glcdc_regs.h as part of the ra8_display_addr_t enum that groups the GLCDC + MIPI + CEU bases. This header uses that constant rather than redefining it.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_mipi_phy_regs.h.

Enumeration Type Documentation

◆ ra8_mipi_phy_block_off_t

enum ra8_mipi_phy_block_off_t : uint16_t

32-bit register offsets inside the MIPI PHY window.

Names mirror the HUM register acronyms (DPHYxxx). Verified against HUM Ch 64.2 sections 64.2.1 .. 64.2.14, p 3822-3837.

Enumerator
k_ra8_mipi_phy_off_refcr	+0x000 DPHYREFCR – ref clock cfg.
k_ra8_mipi_phy_off_plfcr	+0x004 DPHYPLFCR – PLL freq ctrl.
k_ra8_mipi_phy_off_plocr	+0x008 DPHYPLOCR – PLL op ctrl.
k_ra8_mipi_phy_off_esccr	+0x00C DPHYESCCR – escape clk div.
k_ra8_mipi_phy_off_pwrcr	+0x010 DPHYPWRCR – LDO pwr supply.
k_ra8_mipi_phy_off_sfr	+0x01C DPHYSFR – status flags.
k_ra8_mipi_phy_off_ocr	+0x020 DPHYOCR – D-PHY enable.
k_ra8_mipi_phy_off_tim1	+0x024 DPHYTIM1 – TINIT.
k_ra8_mipi_phy_off_tim2	+0x028 DPHYTIM2 – TCLK PREP/SETT.
k_ra8_mipi_phy_off_tim3	+0x02C DPHYTIM3 – THS PREP/SETT.
k_ra8_mipi_phy_off_tim4	+0x030 DPHYTIM4 – TCLK ZERO/PRE.
k_ra8_mipi_phy_off_tim5	+0x034 DPHYTIM5 – THS ZERO/TRL.
k_ra8_mipi_phy_off_tim6	+0x038 DPHYTIM6 – TLPX.
k_ra8_mipi_phy_off_mdc	+0x048 DPHYMDC – host/device.

Definition at line 66 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_esccr_mask_t

enum ra8_mipi_phy_esccr_mask_t : uint32_t

DPHYESCCR field masks.

HUM Ch 64.2.4 "DPHYESCCR : D-PHY Escape Mode Clock Control Register" p 3825: ESCDIV[4:0] controls the LP-state clock divisor (1 .. 32). Must be set while the PLL is stopped.

Enumerator
k_ra8_mipi_phy_esccr_escdiv_mask	ESCDIV[4:0] field.

Definition at line 187 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_input_clk_t

enum ra8_mipi_phy_input_clk_t : uint8_t

Input clock guardrails to PLL (HUM Ch 64.1 Table 64.1 p 3822).

The MOSC reference must be 8..48 MHz, and after IDIV division the PLL input must land in 8..24 MHz.

Enumerator
k_ra8_mipi_phy_mosc_min_mhz	MOSC lower bound.
k_ra8_mipi_phy_mosc_max_mhz	MOSC upper bound.
k_ra8_mipi_phy_pll_in_min_mhz	Post-IDIV lower bound.
k_ra8_mipi_phy_pll_in_max_mhz	Post-IDIV upper bound.
k_ra8_mipi_phy_lp_clk_min_mhz	fLPX lower bound (HUM 64.2.4 p 3825).
k_ra8_mipi_phy_lp_clk_max_mhz	fLPX upper bound (HUM 64.2.4 p 3825).

Definition at line 321 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_lane_speed_limit_t

enum ra8_mipi_phy_lane_speed_limit_t : uint16_t

Per-lane line-rate guardrails (Mbps).

HUM Ch 64.1 Table 64.1 p 3822: D-PHY supports 80 Mbps to 720 Mbps per lane. The driver clamps the requested speed into this range before computing PLL coefficients.

Enumerator
k_ra8_mipi_phy_line_rate_min_mbps	Lower line-rate limit.
k_ra8_mipi_phy_line_rate_max_mbps	Upper line-rate limit.

Definition at line 278 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_mdc_bit_t

enum ra8_mipi_phy_mdc_bit_t : uint32_t

DPHYMDC bit positions / masks.

HUM Ch 64.2.14 "DPHYMDC : D-PHY Mode Control Register" p 3836:

bit 0 (MASTEREN): 0 = device (CSI-2), 1 = host (DSI).

Enumerator
k_ra8_mipi_phy_mdc_hosten	DPHYMDC.MASTEREN bit 0: host (DSI) mode.

Definition at line 145 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_ocr_bit_t

enum ra8_mipi_phy_ocr_bit_t : uint32_t

DPHYOCR bit positions / masks.

HUM Ch 64.2.7 "DPHYOCR : D-PHY Operation Control Register" p 3827: bit 0 = DPHYEN (0 = D-PHY off, 1 = D-PHY on).

Enumerator
k_ra8_mipi_phy_ocr_dphyen	Bit 0 mask: enable D-PHY.

Definition at line 115 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_pll_band_t

enum ra8_mipi_phy_pll_band_t : uint16_t

VCO frequency band guardrails (HUM Ch 64.1 Table 64.1 p 3822).

The PLL VCO must oscillate between 960 MHz and 3000 MHz. The post-divider band depends on PMUL[1:0]:

P = 1 : 960 .. 1440 MHz
P = 1/2 : 480 .. 1440 MHz
P = 1/4 : 240 .. 750 MHz
P = 1/8 : 120 .. 375 MHz

Used by the driver-side band validator to reject impossible combinations of NMUL_int / NFMUL / PMUL before they ever reach the silicon.

Enumerator
k_ra8_mipi_phy_vco_min_mhz	VCO lower bound (post NF+N).
k_ra8_mipi_phy_vco_max_mhz	VCO upper bound (post NF+N).
k_ra8_mipi_phy_pll_p1_min	P=1 floor.
k_ra8_mipi_phy_pll_p1_max	P=1 ceiling.
k_ra8_mipi_phy_pll_p2_min	P=1/2 floor.
k_ra8_mipi_phy_pll_p2_max	P=1/2 ceiling.
k_ra8_mipi_phy_pll_p4_min	P=1/4 floor.
k_ra8_mipi_phy_pll_p4_max	P=1/4 ceiling.
k_ra8_mipi_phy_pll_p8_min	P=1/8 floor.
k_ra8_mipi_phy_pll_p8_max	P=1/8 ceiling.

Definition at line 300 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_pll_field_mask_t

enum ra8_mipi_phy_pll_field_mask_t : uint32_t

DPHYPLFCR field width masks (pre-shift, applied to value).

Enumerator
k_ra8_mipi_phy_plfcr_mask_idiv	IDIV[1:0] mask.
k_ra8_mipi_phy_plfcr_mask_nfmul	NFMUL[1:0] mask.
k_ra8_mipi_phy_plfcr_mask_pmul	PMUL[1:0] mask.
k_ra8_mipi_phy_plfcr_mask_nmul	NMUL[8:0] mask.

Definition at line 262 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_pll_field_shift_t

enum ra8_mipi_phy_pll_field_shift_t : uint8_t

DPHYPLFCR field positions.

HUM Ch 64.2.2 "DPHYPLFCR : D-PHY PLL Frequency Control Register" p 3823:

IDIV [1:0] @ shift 0
NFMUL [1:0] @ shift 8
PMUL [1:0] @ shift 12
NMUL [8:0] @ shift 16

Enumerator
k_ra8_mipi_phy_plfcr_shift_idiv	IDIV[1:0] field shift.
k_ra8_mipi_phy_plfcr_shift_nfmul	NFMUL[1:0] field shift.
k_ra8_mipi_phy_plfcr_shift_pmul	PMUL[1:0] field shift.
k_ra8_mipi_phy_plfcr_shift_nmul	NMUL[8:0] field shift.

Definition at line 251 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_plocr_bit_t

enum ra8_mipi_phy_plocr_bit_t : uint32_t

DPHYPLOCR bit positions / masks.

HUM Ch 64.2.3 "DPHYPLOCR : D-PHY PLL Operation Control Register" p 3824: bit 0 = PLLSTP (0 = run PLL, 1 = stop PLL). Reset = 1.

Enumerator
k_ra8_mipi_phy_plocr_pllstp	Bit 0 mask: stop the PLL.

Definition at line 103 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_pwrcr_bit_t

enum ra8_mipi_phy_pwrcr_bit_t : uint32_t

DPHYPWRCR bit positions / masks.

HUM Ch 64.2.5 "DPHYPWRCR : D-PHY Power Supplying Control Register" p 3826: bit 0 = PWRSEN (0 = stop LDO, 1 = enable LDO).

Enumerator
k_ra8_mipi_phy_pwrcr_pwrsen	Bit 0 mask: enable D-PHY LDO.

Definition at line 91 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_refcr_bias_t

enum ra8_mipi_phy_refcr_bias_t : uint8_t

Software-side bias used when encoding DPHYREFCR.RFREQ.

HUM Ch 64.2.1 p 3822: hardware encoding subtracts one from the frequency in MHz before storing it in RFREQ[7:0]. Use this constant everywhere the driver converts pclka_mhz to a register value.

Enumerator
k_ra8_mipi_phy_refcr_rfreq_bias	RFREQ encodes (MHz - 1).

Definition at line 174 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_refcr_mask_t

enum ra8_mipi_phy_refcr_mask_t : uint32_t

DPHYREFCR field masks.

HUM Ch 64.2.1 "DPHYREFCR : D-PHY Reference Clock Setting Register" p 3822 documents the encoding as a strict RFREQ = pclka_mhz - 1 mapping: 0x27 = 40 MHz, 0x28 = 41 MHz, ..., 0x7C = 125 MHz. PCLKA must be >= 40 MHz to use MIPI DSI. Driver code MUST subtract one before writing – this matches FSP r_mipi_phy.c which writes (pclka_hz / 1MHz) - 1.

Enumerator
k_ra8_mipi_phy_refcr_rfreq_mask	RFREQ[7:0] field.

Definition at line 161 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_sfr_bit_t

enum ra8_mipi_phy_sfr_bit_t : uint32_t

DPHYSFR status flag positions / masks (read-only).

HUM Ch 64.2.6 "DPHYSFR : D-PHY Status Flag Register" p 3826:

bit 0 (PWRSF): D-PHY LDO power-on stable.
bit 8 (PLLSF): D-PHY PLL oscillation stable.

The full status mask combines both flags (used by status-get helpers that want to assert "PHY fully ready").

Enumerator
k_ra8_mipi_phy_sfr_pwrsf	Bit 0 mask: LDO stable.
k_ra8_mipi_phy_sfr_pllsf	Bit 8 mask: PLL clock stable.
k_ra8_mipi_phy_sfr_ready_mask	PWRSF \| PLLSF.

Definition at line 131 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_tim1_mask_t

enum ra8_mipi_phy_tim1_mask_t : uint32_t

DPHYTIM1 field masks.

HUM Ch 64.2.8 "DPHYTIM1 : D-PHY Timing Control Register 1" p 3827: TINIT[18:0] = (TINIT count) where T_INIT = (TINIT + 1) * PCLKA.

Enumerator
k_ra8_mipi_phy_tim1_tinit_mask	TINIT[18:0] field.

Definition at line 199 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_tim6_mask_t

enum ra8_mipi_phy_tim6_mask_t : uint32_t

DPHYTIM6 field masks.

HUM Ch 64.2.13 "DPHYTIM6 : D-PHY Timing Control Register 6" p 3830: TLPX[7:0] – only one byte-wide field, upper 24 bits are reserved.

Enumerator
k_ra8_mipi_phy_tim6_tlpx_mask	TLPX[7:0] field.

Definition at line 235 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_tim_byte_mask_t

enum ra8_mipi_phy_tim_byte_mask_t : uint32_t

8-bit per-field mask applied before shifting in DPHYTIM2..5.

Enumerator
k_ra8_mipi_phy_tim_byte_mask	Mask for each 8-bit lane.

Definition at line 222 of file ra8_mipi_phy_regs.h.

◆ ra8_mipi_phy_tim_byte_shift_t

enum ra8_mipi_phy_tim_byte_shift_t : uint8_t

Generic 8-bit byte-lane shifts used inside DPHYTIM2..5.

Many DPHYTIMx registers pack three / four 8-bit fields into the 32-bit word. These shifts replace the magic numbers 0/8/16/24.

Enumerator
k_ra8_mipi_phy_tim_shift_b0	Byte 0 (bits 7:0).
k_ra8_mipi_phy_tim_shift_b1	Byte 1 (bits 15:8).
k_ra8_mipi_phy_tim_shift_b2	Byte 2 (bits 23:16).
k_ra8_mipi_phy_tim_shift_b3	Byte 3 (bits 31:24).

Definition at line 211 of file ra8_mipi_phy_regs.h.

Function Documentation

◆ ra8_mipi_phy_reg32()

volatile uint32_t * ra8_mipi_phy_reg32 ( ra8_mipi_phy_block_off_t offset )

inlinestatic

Pointer to a 32-bit MIPI PHY register at the given offset.

Parameters

[in] offset Register offset from ra8_mipi_phy_block_off_t.

Returns: Volatile pointer to the 32-bit register.

Note: Per HUM Ch 64.2 p 3822, all MIPI PHY registers must be accessed in 32-bit units. Do not use byte / halfword writes.

Definition at line 340 of file ra8_mipi_phy_regs.h.

References k_ra8_mipi_phy_base_addr.

Referenced by internal_mipi_phy_cache_state(), internal_mipi_phy_init_host(), internal_mipi_phy_init_power_up(), priv_mipi_phy_write_timing(), ra8_mipi_phy_deinit(), ra8_mipi_phy_dispatch(), ra8_mipi_phy_get_status(), ra8_mipi_phy_init(), ra8_mipi_phy_is_ldo_stable(), ra8_mipi_phy_is_pll_locked(), ra8_mipi_phy_ldo_disable(), ra8_mipi_phy_ldo_enable(), ra8_mipi_phy_pll_start(), ra8_mipi_phy_pll_stop(), ra8_mipi_phy_reset(), ra8_mipi_phy_set_escape_divisor(), ra8_mipi_phy_set_lane_speed(), ra8_mipi_phy_set_pclka_freq(), ra8_mipi_phy_switch_mode(), and ra8_mipi_phy_wait_ready().

Enumerations

Functions