ra8_glcdc_regs.h File Reference

Graphics LCD Controller (GLCDC) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	ra8_glcdc_gam_t
	Per-channel gamma correction register block (HUM Ch 63 p 3789-3793). More...

Enumerations
enum	ra8_display_addr_t : uintptr_t {   k_ra8_glcdc_base_addr = 0x40342000UL ,   k_ra8_mipi_dsi_base_addr = 0x40346000UL ,   k_ra8_mipi_phy_base_addr = 0x40346C00UL ,   k_ra8_mipi_csi_base_addr = 0x40347000UL ,   k_ra8_ceu_base_addr = 0x40348000UL }
enum	ra8_glcdc_block_off_t : uint16_t {   k_ra8_glcdc_off_gr1_clut0 = 0x0000U ,   k_ra8_glcdc_off_gr1_clut1 = 0x0400U ,   k_ra8_glcdc_off_gr2_clut0 = 0x0800U ,   k_ra8_glcdc_off_gr2_clut1 = 0x0C00U ,   k_ra8_glcdc_off_bg_en = 0x1000U ,   k_ra8_glcdc_off_bg_per = 0x1004U ,   k_ra8_glcdc_off_bg_sync = 0x1008U ,   k_ra8_glcdc_off_bg_vsize = 0x100CU ,   k_ra8_glcdc_off_bg_hsize = 0x1010U ,   k_ra8_glcdc_off_bg_bgc = 0x1014U ,   k_ra8_glcdc_off_bg_mon = 0x1018U ,   k_ra8_glcdc_off_gr1_en = 0x1100U ,   k_ra8_glcdc_off_gr1_flmrd = 0x1104U ,   k_ra8_glcdc_off_gr1_flm1 = 0x1108U ,   k_ra8_glcdc_off_gr1_saddr = 0x110CU ,   k_ra8_glcdc_off_gr1_flm3 = 0x1110U ,   k_ra8_glcdc_off_gr1_line = 0x1118U ,   k_ra8_glcdc_off_gr1_fmt = 0x111CU ,   k_ra8_glcdc_off_gr1_ab1 = 0x1120U ,   k_ra8_glcdc_off_gr1_ab2 = 0x1124U ,   k_ra8_glcdc_off_gr1_size = 0x1128U ,   k_ra8_glcdc_off_gr1_ab4 = 0x112CU ,   k_ra8_glcdc_off_gr1_ab5 = 0x1130U ,   k_ra8_glcdc_off_gr1_ab6 = 0x1134U ,   k_ra8_glcdc_off_gr1_ab7 = 0x1138U ,   k_ra8_glcdc_off_gr1_ab8 = 0x113CU ,   k_ra8_glcdc_off_gr1_ab9 = 0x1140U ,   k_ra8_glcdc_off_gr1_base = 0x114CU ,   k_ra8_glcdc_off_gr1_clutint = 0x1150U ,   k_ra8_glcdc_off_gr1_mon = 0x1154U ,   k_ra8_glcdc_off_gr2_en = 0x1200U ,   k_ra8_glcdc_off_gr2_flmrd = 0x1204U ,   k_ra8_glcdc_off_gr2_flm1 = 0x1208U ,   k_ra8_glcdc_off_gr2_saddr = 0x120CU ,   k_ra8_glcdc_off_gr2_flm3 = 0x1210U ,   k_ra8_glcdc_off_gr2_line = 0x1218U ,   k_ra8_glcdc_off_gr2_fmt = 0x121CU ,   k_ra8_glcdc_off_gr2_ab1 = 0x1220U ,   k_ra8_glcdc_off_gr2_ab2 = 0x1224U ,   k_ra8_glcdc_off_gr2_size = 0x1228U ,   k_ra8_glcdc_off_gr2_ab4 = 0x122CU ,   k_ra8_glcdc_off_gr2_ab5 = 0x1230U ,   k_ra8_glcdc_off_gr2_ab6 = 0x1234U ,   k_ra8_glcdc_off_gr2_ab7 = 0x1238U ,   k_ra8_glcdc_off_gr2_ab8 = 0x123CU ,   k_ra8_glcdc_off_gr2_ab9 = 0x1240U ,   k_ra8_glcdc_off_gr2_base = 0x124CU ,   k_ra8_glcdc_off_gr2_clutint = 0x1250U ,   k_ra8_glcdc_off_gr2_mon = 0x1254U ,   k_ra8_glcdc_off_gam0 = 0x1300U ,   k_ra8_glcdc_off_gam1 = 0x1340U ,   k_ra8_glcdc_off_gam2 = 0x1380U ,   k_ra8_glcdc_off_out_vlatch = 0x13C0U ,   k_ra8_glcdc_off_out_set = 0x13C4U ,   k_ra8_glcdc_off_out_bright1 = 0x13C8U ,   k_ra8_glcdc_off_out_bright2 = 0x13CCU ,   k_ra8_glcdc_off_out_contrast = 0x13D0U ,   k_ra8_glcdc_off_panel_dtha = 0x13D4U ,   k_ra8_glcdc_off_out_gamsw = 0x13D8U ,   k_ra8_glcdc_off_out_clkphase = 0x13E4U ,   k_ra8_glcdc_off_tcon_tim = 0x1404U ,   k_ra8_glcdc_off_tcon_stva1 = 0x1408U ,   k_ra8_glcdc_off_tcon_stva2 = 0x140CU ,   k_ra8_glcdc_off_tcon_stvb1 = 0x1410U ,   k_ra8_glcdc_off_tcon_stvb2 = 0x1414U ,   k_ra8_glcdc_off_tcon_stha1 = 0x1418U ,   k_ra8_glcdc_off_tcon_stha2 = 0x141CU ,   k_ra8_glcdc_off_tcon_sthb1 = 0x1420U ,   k_ra8_glcdc_off_tcon_sthb2 = 0x1424U ,   k_ra8_glcdc_off_tcon_de = 0x1428U ,   k_ra8_glcdc_off_sys_cfg = 0x1440U ,   k_ra8_glcdc_off_sys_intr = 0x1444U ,   k_ra8_glcdc_off_sys_clr = 0x1448U ,   k_ra8_glcdc_off_sys_stat = 0x144CU ,   k_ra8_glcdc_off_panel_clk = 0x1450U }
	Absolute register offsets inside the GLCDC window. More...
enum	ra8_glcdc_pixel_fmt_t : uint8_t {   k_ra8_glcdc_fmt_argb8888 = 0x0U ,   k_ra8_glcdc_fmt_rgb888 = 0x1U ,   k_ra8_glcdc_fmt_rgb565 = 0x2U ,   k_ra8_glcdc_fmt_argb1555 = 0x3U ,   k_ra8_glcdc_fmt_argb4444 = 0x4U ,   k_ra8_glcdc_fmt_clut8 = 0x5U ,   k_ra8_glcdc_fmt_clut4 = 0x6U ,   k_ra8_glcdc_fmt_clut1 = 0x7U }
	Pixel format codes written to GRn_FLM6.FORMAT[30:28]. More...
enum	ra8_glcdc_gam_size_t : uint8_t { k_ra8_glcdc_gam_block_bytes = 64U }
	Byte size of one channel's GAM register block (LUT[8] + AREA[8]). More...
enum	ra8_glcdc_gam_field_t : uint32_t {   k_ra8_glcdc_gam_lut_gain_h_shift = 16U ,   k_ra8_glcdc_gam_lut_gain_l_mask = 0x000007FFUL ,   k_ra8_glcdc_gam_area_th_h_shift = 16U ,   k_ra8_glcdc_gam_area_th_l_mask = 0x000003FFUL }
	Shift and mask constants for the gamma LUT and AREA register fields. More...
enum	ra8_glcdc_gamsw_bits_t : uint32_t { k_ra8_glcdc_gamsw_gamon = 0x00000001UL }
	Bit mask for the output-stage gamma-switch register (GAMSW). More...
enum	ra8_glcdc_ek_timing_t : uint16_t {   k_ra8_glcdc_ek_h_active = 1024U ,   k_ra8_glcdc_ek_v_active = 600U ,   k_ra8_glcdc_ek_h_front = 160U ,   k_ra8_glcdc_ek_h_back = 140U ,   k_ra8_glcdc_ek_h_sync = 20U ,   k_ra8_glcdc_ek_v_front = 12U ,   k_ra8_glcdc_ek_v_back = 20U ,   k_ra8_glcdc_ek_v_sync = 3U }
enum	ra8_glcdc_ek_clk_t : uint32_t { k_ra8_glcdc_ek_pixel_clk_hz = 51200000UL }

Functions
static volatile uint32_t *	ra8_glcdc_reg32 (ra8_glcdc_block_off_t offset)
	Pointer to a 32-bit register inside the GLCDC block.
static volatile ra8_glcdc_gam_t *	ra8_glcdc_gam_regs (uint8_t channel_idx)
	Return a volatile pointer to a per-channel gamma register block.

Detailed Description

Graphics LCD Controller (GLCDC) register layout for the RA8D2.

GLCDC at 0x40342000 drives up to two RGB graphics layers with alpha blending, chroma key, dither, gamma correction, and parallel-RGB or MIPI-DSI output. The EK-RA8D2's 1024x600 7" parallel TFT connects here via the GLCDC expansion header. <h2>Block structure (verified against FSP R_GLCDC_Type in</h2> R7KA8D2KF_core0.h lines 6980-7045) <table class="markdownTable"> <tr class="markdownTableHead"> <th class="markdownTableHeadRight"> Offset

Block

Size

Purpose

0x0000

GR1_CLUT0[256]

0x0400

Graphics 1 CLUT plane 0

0x0400

GR1_CLUT1[256]

0x0400

Graphics 1 CLUT plane 1

0x0800

GR2_CLUT0[256]

0x0400

Graphics 2 CLUT plane 0

0x0C00

GR2_CLUT1[256]

0x0400

Graphics 2 CLUT plane 1

0x1000

BG

0x001C

Background timing + bgc

0x1100

GR[0]

0x0100

Graphics layer 0

0x1200

GR[1]

0x0100

Graphics layer 1

0x1300

GAM[0..2]

0x00C0

Gamma tables (3 channels)

0x13C0

OUT

0x0028

Output control

0x1400

TCON

0x002C

Timing controller

0x1440

SYSCNT

0x0014

System control / ints

The previous version of this header placed BG at offset 0x000, GR1 at 0x150, GR2 at 0x270, OUT at 0x390, SYSCNT at 0x420 – all of which landed inside GR1/GR2 CLUTs or reserved gaps. Every k_ra8_glcdc_off_* has been re-derived against FSP.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_glcdc_regs.h.

Enumeration Type Documentation

ra8_display_addr_t

enum ra8_display_addr_t : uintptr_t

Enumerator
k_ra8_glcdc_base_addr	RA8 GLCDC base address.
k_ra8_mipi_dsi_base_addr	RA8 mipi dsi base address.
k_ra8_mipi_phy_base_addr	RA8 mipi PHY base address.
k_ra8_mipi_csi_base_addr	RA8 mipi csi base address.
k_ra8_ceu_base_addr	RA8 CEU base address.

Definition at line 48 of file ra8_glcdc_regs.h.

ra8_glcdc_block_off_t

enum ra8_glcdc_block_off_t : uint16_t

Absolute register offsets inside the GLCDC window.

Names mirror FSP's R_GLCDC_Type field names so a reader can cross-reference directly. Offsets are verified byte-for-byte against FSP's sub-type structs (R_GLCDC_BG_Type, R_GLCDC_GR_Type, R_GLCDC_OUT_Type, R_GLCDC_TCON_Type, R_GLCDC_SYSCNT_Type).

Enumerator
k_ra8_glcdc_off_gr1_clut0	GR1_CLUT0[256] @ 0x0000.
k_ra8_glcdc_off_gr1_clut1	GR1_CLUT1[256] @ 0x0400.
k_ra8_glcdc_off_gr2_clut0	GR2_CLUT0[256] @ 0x0800.
k_ra8_glcdc_off_gr2_clut1	GR2_CLUT1[256] @ 0x0C00.
k_ra8_glcdc_off_bg_en	BG.EN: module enable.
k_ra8_glcdc_off_bg_per	BG.PERI: free-running period.
k_ra8_glcdc_off_bg_sync	BG.SYNC: sync position.
k_ra8_glcdc_off_bg_vsize	BG.VSIZE: vertical valid size.
k_ra8_glcdc_off_bg_hsize	BG.HSIZE: horizontal valid size.
k_ra8_glcdc_off_bg_bgc	BG.BGC: background colour.
k_ra8_glcdc_off_bg_mon	BG.MON: status monitor.
k_ra8_glcdc_off_gr1_en	GR[0].VEN: register update ctrl.
k_ra8_glcdc_off_gr1_flmrd	GR[0].FLMRD: frame buffer read en.
k_ra8_glcdc_off_gr1_flm1	GR[0].FLM1: burst mode.
k_ra8_glcdc_off_gr1_saddr	GR[0].FLM2.BASE: framebuffer addr.
k_ra8_glcdc_off_gr1_flm3	GR[0].FLM3: line offset bytes.
k_ra8_glcdc_off_gr1_line	GR[0].FLM5: datanum + lnnum.
k_ra8_glcdc_off_gr1_fmt	GR[0].FLM6.FORMAT: pixel format.
k_ra8_glcdc_off_gr1_ab1	GR[0].AB1: alpha blend ctrl 1.
k_ra8_glcdc_off_gr1_ab2	GR[0].AB2: graphics V size + pos.
k_ra8_glcdc_off_gr1_size	GR[0].AB3: graphics H size + pos.
k_ra8_glcdc_off_gr1_ab4	GR[0].AB4: alpha rect V size+pos.
k_ra8_glcdc_off_gr1_ab5	GR[0].AB5: alpha rect H size+pos.
k_ra8_glcdc_off_gr1_ab6	GR[0].AB6: fade rate / coef.
k_ra8_glcdc_off_gr1_ab7	GR[0].AB7: chroma-key on, def alf.
k_ra8_glcdc_off_gr1_ab8	GR[0].AB8: chroma-key key colour.
k_ra8_glcdc_off_gr1_ab9	GR[0].AB9: chroma-key replace col.
k_ra8_glcdc_off_gr1_base	GR[0].BASE: layer bg colour.
k_ra8_glcdc_off_gr1_clutint	GR[0].CLUTINT: CLUT swap + line.
k_ra8_glcdc_off_gr1_mon	GR[0].MON: status monitor.
k_ra8_glcdc_off_gr2_en	GR[1].VEN.
k_ra8_glcdc_off_gr2_flmrd	GR[1].FLMRD.
k_ra8_glcdc_off_gr2_flm1	GR[1].FLM1.
k_ra8_glcdc_off_gr2_saddr	GR[1].FLM2.BASE.
k_ra8_glcdc_off_gr2_flm3	GR[1].FLM3.
k_ra8_glcdc_off_gr2_line	GR[1].FLM5.
k_ra8_glcdc_off_gr2_fmt	GR[1].FLM6.FORMAT.
k_ra8_glcdc_off_gr2_ab1	GR[1].AB1.
k_ra8_glcdc_off_gr2_ab2	GR[1].AB2: graphics V size + pos.
k_ra8_glcdc_off_gr2_size	GR[1].AB3: graphics H size + pos.
k_ra8_glcdc_off_gr2_ab4	GR[1].AB4: alpha rect V size+pos.
k_ra8_glcdc_off_gr2_ab5	GR[1].AB5: alpha rect H size+pos.
k_ra8_glcdc_off_gr2_ab6	GR[1].AB6: fade rate / coef.
k_ra8_glcdc_off_gr2_ab7	GR[1].AB7: chroma-key on, def alf.
k_ra8_glcdc_off_gr2_ab8	GR[1].AB8: chroma-key key colour.
k_ra8_glcdc_off_gr2_ab9	GR[1].AB9: chroma-key replace col.
k_ra8_glcdc_off_gr2_base	GR[1].BASE.
k_ra8_glcdc_off_gr2_clutint	GR[1].CLUTINT.
k_ra8_glcdc_off_gr2_mon	GR[1].MON.
k_ra8_glcdc_off_gam0	GAM[0] block base (Red channel).
k_ra8_glcdc_off_gam1	GAM[1] block base (Green channel).
k_ra8_glcdc_off_gam2	GAM[2] block base (Blue channel).
k_ra8_glcdc_off_out_vlatch	OUT.VLATCH.
k_ra8_glcdc_off_out_set	OUT.SET: output interface.
k_ra8_glcdc_off_out_bright1	OUT.BRIGHT1.
k_ra8_glcdc_off_out_bright2	OUT.BRIGHT2.
k_ra8_glcdc_off_out_contrast	OUT.CONTRAST.
k_ra8_glcdc_off_panel_dtha	OUT.PDTHA: panel dither.
k_ra8_glcdc_off_out_gamsw	OUT.GAMSW: gamma enable switch.
k_ra8_glcdc_off_out_clkphase	OUT.CLKPHASE.
k_ra8_glcdc_off_tcon_tim	TCON.TIM: reference timing.
k_ra8_glcdc_off_tcon_stva1	TCON.STVA1.
k_ra8_glcdc_off_tcon_stva2	TCON.STVA2.
k_ra8_glcdc_off_tcon_stvb1	TCON.STVB1.
k_ra8_glcdc_off_tcon_stvb2	TCON.STVB2.
k_ra8_glcdc_off_tcon_stha1	TCON.STHA1.
k_ra8_glcdc_off_tcon_stha2	TCON.STHA2.
k_ra8_glcdc_off_tcon_sthb1	TCON.STHB1.
k_ra8_glcdc_off_tcon_sthb2	TCON.STHB2.
k_ra8_glcdc_off_tcon_de	TCON.DE.
k_ra8_glcdc_off_sys_cfg	SYSCNT.DTCTEN (state detection).
k_ra8_glcdc_off_sys_intr	SYSCNT.INTEN.
k_ra8_glcdc_off_sys_clr	SYSCNT.STCLR.
k_ra8_glcdc_off_sys_stat	SYSCNT.STMON.
k_ra8_glcdc_off_panel_clk	SYSCNT.PANEL_CLK.

Definition at line 66 of file ra8_glcdc_regs.h.

ra8_glcdc_ek_clk_t

enum ra8_glcdc_ek_clk_t : uint32_t

Enumerator
k_ra8_glcdc_ek_pixel_clk_hz	~51.2 MHz pixel clock.

Definition at line 304 of file ra8_glcdc_regs.h.

ra8_glcdc_ek_timing_t

enum ra8_glcdc_ek_timing_t : uint16_t

Enumerator
k_ra8_glcdc_ek_h_active	RA8 GLCDC ek h active.
k_ra8_glcdc_ek_v_active	RA8 GLCDC ek v active.
k_ra8_glcdc_ek_h_front	RA8 GLCDC ek h front.
k_ra8_glcdc_ek_h_back	RA8 GLCDC ek h back.
k_ra8_glcdc_ek_h_sync	RA8 GLCDC ek h sync.
k_ra8_glcdc_ek_v_front	RA8 GLCDC ek v front.
k_ra8_glcdc_ek_v_back	RA8 GLCDC ek v back.
k_ra8_glcdc_ek_v_sync	RA8 GLCDC ek v sync.

Definition at line 293 of file ra8_glcdc_regs.h.

ra8_glcdc_gam_field_t

enum ra8_glcdc_gam_field_t : uint32_t

Shift and mask constants for the gamma LUT and AREA register fields.

LUT register layout (HUM Ch 63 "GAMx_LUTn" p 3790): bits[26:16] = GAIN0 (11 bits, coefficient for even entry index) bits[10:0] = GAIN1 (11 bits, coefficient for odd entry index)

AREA register layout (HUM Ch 63 "GAMx_AREAn" p 3793): bits[25:16] = TH1 (10 bits, boundary for even threshold index) bits[9:0] = TH2 (10 bits, boundary for odd threshold index)

Enumerator
k_ra8_glcdc_gam_lut_gain_h_shift	LUT GAIN0 bit-shift.
k_ra8_glcdc_gam_lut_gain_l_mask	LUT GAIN1 11-bit mask.
k_ra8_glcdc_gam_area_th_h_shift	AREA TH1 bit-shift.
k_ra8_glcdc_gam_area_th_l_mask	AREA TH2 10-bit mask.

Definition at line 242 of file ra8_glcdc_regs.h.

ra8_glcdc_gam_size_t

enum ra8_glcdc_gam_size_t : uint8_t

Byte size of one channel's GAM register block (LUT[8] + AREA[8]).

Enumerator
k_ra8_glcdc_gam_block_bytes	sizeof(ra8_glcdc_gam_t).

Definition at line 222 of file ra8_glcdc_regs.h.

ra8_glcdc_gamsw_bits_t

enum ra8_glcdc_gamsw_bits_t : uint32_t

Bit mask for the output-stage gamma-switch register (GAMSW).

HUM Ch 63 "OUT_GAMSW Gamma Correction Block Switch Register" p 3789: bit 0 (GAMON) enables the gamma correction pipeline for all channels.

Enumerator
k_ra8_glcdc_gamsw_gamon	GAMSW.GAMON: global gamma enable.

Definition at line 257 of file ra8_glcdc_regs.h.

ra8_glcdc_pixel_fmt_t

enum ra8_glcdc_pixel_fmt_t : uint8_t

Pixel format codes written to GRn_FLM6.FORMAT[30:28].

Verified against HUM Ch 63 "GLCDC" Table 63.11 "Graphics data format" and FSP r_glcdc.h glcdc_gr_format_t.

Enumerator
k_ra8_glcdc_fmt_argb8888	32-bit ARGB.
k_ra8_glcdc_fmt_rgb888	24-bit RGB (packed).
k_ra8_glcdc_fmt_rgb565	16-bit RGB565.
k_ra8_glcdc_fmt_argb1555	16-bit ARGB1555.
k_ra8_glcdc_fmt_argb4444	16-bit ARGB4444.
k_ra8_glcdc_fmt_clut8	8-bit CLUT.
k_ra8_glcdc_fmt_clut4	4-bit CLUT.
k_ra8_glcdc_fmt_clut1	1-bit CLUT.

Definition at line 167 of file ra8_glcdc_regs.h.

Function Documentation

ra8_glcdc_gam_regs()

volatile ra8_glcdc_gam_t * ra8_glcdc_gam_regs ( uint8_t channel_idx )

inlinestatic

Return a volatile pointer to a per-channel gamma register block.

Computes the base address of GAM[0] (R), GAM[1] (G), or GAM[2] (B) from the offset table. The caller must validate channel_idx before calling; an out-of-range index produces a pointer into unmapped MMIO.

Parameters

[in]

channel_idx

0 = Red, 1 = Green, 2 = Blue.

Returns

Volatile pointer to the channel's ra8_glcdc_gam_t register block.

Definition at line 273 of file ra8_glcdc_regs.h.

References k_ra8_glcdc_base_addr, k_ra8_glcdc_off_gam0, k_ra8_glcdc_off_gam1, and k_ra8_glcdc_off_gam2.

Referenced by ra8_glcdc_set_gamma().

ra8_glcdc_reg32()

volatile uint32_t * ra8_glcdc_reg32 ( ra8_glcdc_block_off_t offset )

inlinestatic

Pointer to a 32-bit register inside the GLCDC block.

Parameters

[in]

offset

One of the k_ra8_glcdc_off_* values.

Returns

Volatile pointer to the register.

Definition at line 184 of file ra8_glcdc_regs.h.

References k_ra8_glcdc_base_addr.

Referenced by internal_clutint_reg(), internal_program_bg(), internal_program_gr1(), internal_program_gr2(), internal_program_out(), internal_program_tcon(), ra8_glcdc_clear_status(), ra8_glcdc_deinit(), ra8_glcdc_dispatch(), ra8_glcdc_enter_stop(), ra8_glcdc_gamma_enable(), ra8_glcdc_get_status(), ra8_glcdc_init(), ra8_glcdc_layer1_show(), ra8_glcdc_layer2_chroma_key_enable(), ra8_glcdc_layer2_show(), ra8_glcdc_set_background_color(), ra8_glcdc_set_blend(), ra8_glcdc_set_brightness(), ra8_glcdc_set_contrast(), ra8_glcdc_set_dithering(), ra8_glcdc_set_layer2(), and ra8_glcdc_start().