ra8_glcdc_gamma.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_glcdc.h"
#include "ra8_glcdc_regs.h"
#include "ra8_log.h"
 
static const char* s_tag = "GLCDC";
 
/* =============================================================================
 * Module-private constants
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_glcdc_gam_reg_count = 8U, 
  k_ra8_glcdc_gam_pair_step = 2U, 
} ra8_glcdc_gam_reg_count_t;
 
/* =============================================================================
 * Internal helpers (one per loop body to stay inside the 60-line limit)
 * =============================================================================
 */

RA8_INTERNAL
static void internal_write_lut(volatile ra8_glcdc_gam_t* gam, const uint16_t* gain)
{
  for (uint8_t i = 0U; i < (uint8_t)k_ra8_glcdc_gam_reg_count; i++) {
    const uint8_t  hi_idx = (uint8_t)(i * (uint8_t)k_ra8_glcdc_gam_pair_step);
    const uint8_t  lo_idx = (uint8_t)(hi_idx + 1U);
    const uint32_t packed = ((uint32_t)gain[hi_idx] << k_ra8_glcdc_gam_lut_gain_h_shift) |
                            ((uint32_t)gain[lo_idx] & (uint32_t)k_ra8_glcdc_gam_lut_gain_l_mask);
    /* HUM Ch 63 "GAMx_LUTn Gamma Correction LUT Register" p 3790 */
    gam->LUT[i] = packed;
  }
}

RA8_INTERNAL
static void internal_write_area(volatile ra8_glcdc_gam_t* gam, const uint16_t* threshold)
{
  for (uint8_t i = 0U; i < (uint8_t)k_ra8_glcdc_gam_reg_count; i++) {
    const uint8_t  hi_idx = (uint8_t)(i * (uint8_t)k_ra8_glcdc_gam_pair_step);
    const uint8_t  lo_idx = (uint8_t)(hi_idx + 1U);
    const uint32_t packed =
      ((uint32_t)threshold[hi_idx] << k_ra8_glcdc_gam_area_th_h_shift) |
      ((uint32_t)threshold[lo_idx] & (uint32_t)k_ra8_glcdc_gam_area_th_l_mask);
    /* HUM Ch 63 "GAMx_AREAn Gamma Correction Area Register" p 3793 */
    gam->AREA[i] = packed;
  }
}
 
/* =============================================================================
 * Public API
 * =============================================================================
 */
 
ra8_err_t ra8_glcdc_set_gamma(ra8_glcdc_color_channel_t channel,
                              const uint16_t*           gain,
                              const uint16_t*           threshold,
                              uint8_t                   count)
{
  RA8_CHECK_NULL_PTR(gain, s_tag, "gain must not be nullptr");
  RA8_CHECK_NULL_PTR(threshold, s_tag, "threshold must not be nullptr");
  if ((uint8_t)channel >= (uint8_t)k_ra8_glcdc_ch_count) {
    return k_ra8_err_invalid_arg;
  }
  if (count != (uint8_t)k_ra8_glcdc_gamma_lut_depth) {
    return k_ra8_err_invalid_arg;
  }
 
  volatile ra8_glcdc_gam_t* gam = ra8_glcdc_gam_regs((uint8_t)channel);
  RA8_CHECK_NULL_PTR(gam, s_tag, "gamma register block inaccessible");
 
  internal_write_lut(gam, gain);
  internal_write_area(gam, threshold);
 
  ra8_log_info_val(s_tag, "set_gamma channel", (uint32_t)channel);
  return k_ra8_ok;
}
 
ra8_err_t ra8_glcdc_gamma_enable(bool enable)
{
  volatile uint32_t* const reg = ra8_glcdc_reg32(k_ra8_glcdc_off_out_gamsw);
  RA8_CHECK_NULL_PTR(reg, s_tag, "GAMSW register inaccessible");
 
  /* HUM Ch 63 "OUT_GAMSW Gamma Correction Block Switch Register" p 3789 */
  if (enable) {
    *reg = (uint32_t)k_ra8_glcdc_gamsw_gamon;
  } else {
    *reg = 0U;
  }
 
  ra8_log_info_val(s_tag, "gamma_enable", enable ? 1UL : 0UL);
  return k_ra8_ok;
}