Graphics LCD Controller driver (two-layer with alpha blending). More...

#include <stdint.h>
#include "ra8_err.h"
#include "ra8_glcdc_regs.h"

Include dependency graph for ra8_glcdc.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	ra8_glcdc_timing_t
	Panel RGB timing the driver programs (accessory parameters). More...
struct	ra8_glcdc_config_t
	Minimal GLCDC configuration for a single-layer panel. More...
struct	ra8_glcdc_layer2_cfg_t
	Configuration for the background-image (Graphics 2) layer. More...

Typedefs
typedef void(*	ra8_glcdc_event_fn_t) (void *ctx, uint32_t status_mask)
	GLCDC event callback (VSYNC / line detect / underflow).

Enumerations
enum	ra8_glcdc_blend_mode_t : uint8_t { k_ra8_blend_overwrite = 0U , k_ra8_blend_normal = 1U , k_ra8_blend_alpha = 2U }
	Compositing mode between Graphics 1 and Graphics 2. More...
enum	ra8_glcdc_dither_mode_t : uint8_t { k_ra8_dither_off = 0U , k_ra8_dither_truncate = 1U , k_ra8_dither_2x2 = 2U }
	Output-stage dithering mode for 24bpp -> 18/16bpp panels. More...
enum	ra8_glcdc_color_channel_t : uint8_t { k_ra8_glcdc_ch_r = 0U , k_ra8_glcdc_ch_g = 1U , k_ra8_glcdc_ch_b = 2U , k_ra8_glcdc_ch_count = 3U }
	Selector for the three GLCDC gamma colour channels. More...
enum	ra8_glcdc_gamma_lut_const_t : uint8_t { k_ra8_glcdc_gamma_lut_depth = 16U }
	Piecewise-linear LUT depth constants for the GLCDC gamma correction. More...

Functions
ra8_err_t	ra8_glcdc_init (const ra8_glcdc_config_t *cfg)
	Initialise GLCDC with the EK-RA8D2 1024x600 timings and the supplied graphics layer 1 framebuffer.
ra8_err_t	ra8_glcdc_start (bool enable)
	Start or stop the panel output.
ra8_err_t	ra8_glcdc_deinit (void)
	Tear down GLCDC (stop + MSTP release).
ra8_err_t	ra8_glcdc_get_status (uint32_t *out_mask)
	Read GLCDC status register (VSYNC/HSYNC/underflow).
ra8_err_t	ra8_glcdc_clear_status (uint32_t mask)
	Clear GLCDC status flags.
ra8_err_t	ra8_glcdc_attach_handler (ra8_glcdc_event_fn_t fn, void *ctx)
	Attach a GLCDC event callback.
void	ra8_glcdc_dispatch (void)
	Dispatch a GLCDC event – snapshot + fire callback.
ra8_err_t	ra8_glcdc_enter_stop (void)
	Put GLCDC into MSTP-gated stop.
ra8_err_t	ra8_glcdc_exit_stop (void)
	Exit MSTP-gated stop.
ra8_err_t	ra8_glcdc_set_layer2 (const ra8_glcdc_layer2_cfg_t *cfg)
	Configure the Graphics 2 (background-image) layer.
ra8_err_t	ra8_glcdc_layer1_show (uintptr_t fb_addr)
	Make graphics layer 1 visible by pointing it at a framebuffer.
ra8_err_t	ra8_glcdc_layer2_show (uintptr_t fb_addr, uint16_t panel_x, uint16_t panel_y, uint16_t fb_w, uint16_t fb_h)
	Make graphics layer 2 visible at an arbitrary panel position.
ra8_err_t	ra8_glcdc_layer2_chroma_key_enable (uint32_t key_rgb888)
	Enable chroma-key transparency on graphics layer 2.
ra8_err_t	ra8_glcdc_set_blend (ra8_glcdc_blend_mode_t mode, uint8_t global_alpha)
	Set the layer-1-over-layer-2 blend mode and global alpha.
ra8_err_t	ra8_glcdc_set_background_color (uint32_t argb)
	Set the panel-wide background colour shown where neither layer covers a pixel.
ra8_err_t	ra8_glcdc_set_clut_double_buffered (uint8_t layer, const uint32_t *clut, uint32_t entries, bool swap_now)
	Update a CLUT plane double-buffered, optionally swapping on the next vsync.
ra8_err_t	ra8_glcdc_set_dithering (ra8_glcdc_dither_mode_t mode)
	Programme the output dithering mode (PDTHA.SEL).
ra8_err_t	ra8_glcdc_set_brightness (uint8_t r, uint8_t g, uint8_t b)
	Programme per-channel output brightness.
ra8_err_t	ra8_glcdc_set_contrast (uint8_t r, uint8_t g, uint8_t b)
	Programme per-channel output contrast gain.
ra8_err_t	ra8_glcdc_set_gamma (ra8_glcdc_color_channel_t channel, const uint16_t gain, const uint16_t threshold, uint8_t count)
	Programme the piecewise-linear gamma correction table for one channel.
ra8_err_t	ra8_glcdc_gamma_enable (bool enable)
	Enable or disable the GLCDC gamma correction pipeline.

Detailed Description

Graphics LCD Controller driver (two-layer with alpha blending).

Declares timing, layer, framebuffer, and lifecycle contracts for the RA8 graphics LCD controller.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_glcdc.h.

Typedef Documentation

◆ ra8_glcdc_event_fn_t

typedef void(* ra8_glcdc_event_fn_t) (void *ctx, uint32_t status_mask)

GLCDC event callback (VSYNC / line detect / underflow).

Definition at line 122 of file ra8_glcdc.h.

Enumeration Type Documentation

◆ ra8_glcdc_blend_mode_t

enum ra8_glcdc_blend_mode_t : uint8_t

Compositing mode between Graphics 1 and Graphics 2.

Enumerator
k_ra8_blend_overwrite	Layer 1 fully covers layer 2 (DISPSEL=01).
k_ra8_blend_normal	Layer 1 over layer 2, no alpha (DISPSEL=10).
k_ra8_blend_alpha	Per-pixel + global alpha blend (DISPSEL=10+AR).

Definition at line 89 of file ra8_glcdc.h.

◆ ra8_glcdc_color_channel_t

enum ra8_glcdc_color_channel_t : uint8_t

Selector for the three GLCDC gamma colour channels.

The GLCDC has three independent gamma correction blocks, one per colour channel. HUM Ch 63 "GLCDC" p 3789 maps the physical register blocks: GAM[0] -> Red (k_ra8_glcdc_ch_r) GAM[1] -> Green (k_ra8_glcdc_ch_g) GAM[2] -> Blue (k_ra8_glcdc_ch_b)

Invariant: Values are contiguous starting at 0; range is [0, k_ra8_glcdc_ch_count).

const uint16_t gains[16]      = { ... };
const uint16_t thresholds[16] = { ... };
ra8_glcdc_set_gamma(k_ra8_glcdc_ch_r, gains, thresholds, 16);

See also: ra8_glcdc_set_gamma()

Since: 0.1.0

Enumerator
k_ra8_glcdc_ch_r	Red channel -> GAM[0].
k_ra8_glcdc_ch_g	Green channel -> GAM[1].
k_ra8_glcdc_ch_b	Blue channel -> GAM[2].
k_ra8_glcdc_ch_count	Number of colour channels (sentinel).

Definition at line 451 of file ra8_glcdc.h.

◆ ra8_glcdc_dither_mode_t

enum ra8_glcdc_dither_mode_t : uint8_t

Output-stage dithering mode for 24bpp -> 18/16bpp panels.

Enumerator
k_ra8_dither_off	No dithering (PDTHA.SEL=0).
k_ra8_dither_truncate	Round/truncate (PDTHA.SEL=2).
k_ra8_dither_2x2	2x2 ordered dither (PDTHA.SEL=3).

Definition at line 99 of file ra8_glcdc.h.

◆ ra8_glcdc_gamma_lut_const_t

enum ra8_glcdc_gamma_lut_const_t : uint8_t

Piecewise-linear LUT depth constants for the GLCDC gamma correction.

The GLCDC gamma hardware provides 8 LUT registers per channel, each holding two 11-bit gain coefficients, giving 16 gain values total. The 8 AREA registers each hold two 10-bit boundary thresholds, giving 16 threshold values (HUM Ch 63 "GAMx_LUTn / GAMx_AREAn" p 3790-3793). Both the gain and threshold arrays passed to ra8_glcdc_set_gamma() must have exactly k_ra8_glcdc_gamma_lut_depth elements.

See also: ra8_glcdc_set_gamma()

Since: 0.1.0

Enumerator
k_ra8_glcdc_gamma_lut_depth	16 segments (8 LUT regs x 2 gains).

Definition at line 473 of file ra8_glcdc.h.

Function Documentation

◆ ra8_glcdc_attach_handler()

ra8_err_t ra8_glcdc_attach_handler	(	ra8_glcdc_event_fn_t	fn,
		void *	ctx )

nodiscard

Attach a GLCDC event callback.

Since: 0.1.0

Definition at line 842 of file ra8_glcdc.c.

References k_ra8_ok, s_glcdc_ctx, and s_glcdc_fn.

◆ ra8_glcdc_clear_status()

ra8_err_t ra8_glcdc_clear_status ( uint32_t mask )

nodiscard

Clear GLCDC status flags.

Since: 0.1.0

Definition at line 835 of file ra8_glcdc.c.

References k_ra8_glcdc_off_sys_stat, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_deinit()

ra8_err_t ra8_glcdc_deinit ( void )

nodiscard

Tear down GLCDC (stop + MSTP release).

Since: 0.1.0

Definition at line 818 of file ra8_glcdc.c.

References k_ra8_glcdc_off_bg_en, k_ra8_glcdc_off_gr1_en, k_ra8_glcdc_off_sys_cfg, k_ra8_mstp_glcdc, ra8_glcdc_reg32(), ra8_mstp_disable(), s_glcdc_ctx, and s_glcdc_fn.

Referenced by internal_lcd_deinit().

◆ ra8_glcdc_dispatch()

void ra8_glcdc_dispatch ( void )

Dispatch a GLCDC event – snapshot + fire callback.

Since: 0.1.0

See the matching header declaration for the full contract; this site adds no behaviour beyond what the public API documents.

Precondition: Driver state has been initialized by the matching *_init.; Caller has validated all pointer parameters.

Postcondition: Side effects are limited to those documented in the header.; No global state is modified on the error path.

Note: Thread safety: see the header declaration.

Definition at line 850 of file ra8_glcdc.c.

References k_ra8_glcdc_off_sys_stat, ra8_glcdc_reg32(), s_glcdc_ctx, and s_glcdc_fn.

◆ ra8_glcdc_enter_stop()

ra8_err_t ra8_glcdc_enter_stop ( void )

nodiscard

Put GLCDC into MSTP-gated stop.

Since: 0.1.0

Definition at line 862 of file ra8_glcdc.c.

References k_ra8_glcdc_off_sys_cfg, k_ra8_mstp_glcdc, ra8_glcdc_reg32(), and ra8_mstp_disable().

◆ ra8_glcdc_exit_stop()

ra8_err_t ra8_glcdc_exit_stop ( void )

nodiscard

Exit MSTP-gated stop.

Since: 0.1.0

Definition at line 868 of file ra8_glcdc.c.

References k_ra8_mstp_glcdc, and ra8_mstp_enable().

◆ ra8_glcdc_gamma_enable()

ra8_err_t ra8_glcdc_gamma_enable ( bool enable )

nodiscard

Enable or disable the GLCDC gamma correction pipeline.

Writes the GAMSW.GAMON bit (bit 0) in the output-control block, which gates the piecewise-linear correction circuit for all three colour channels. Call after programming all three channel tables with ra8_glcdc_set_gamma().

Parameters

[in] enable true to activate gamma correction; false to bypass it.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	GAMSW register updated.
k_ra8_err_null_ptr	GAMSW register address could not be resolved (should not occur in normal operation).

Precondition: GLCDC has been initialised via ra8_glcdc_init().; All three channel tables have been written via ra8_glcdc_set_gamma() when enabling.

Postcondition: OUT.GAMSW.GAMON == (enable ? 1 : 0).; The gamma pipeline state is visible on the next active pixel.

Note: Not thread-safe; caller must serialise access to GLCDC registers.

See also: ra8_glcdc_set_gamma() Programme individual channel tables.

Since: 0.1.0

HUM:: Ch 63 "OUT_GAMSW Gamma Correction Block Switch Register" p 3789.

Definition at line 155 of file ra8_glcdc_gamma.c.

References k_ra8_glcdc_gamsw_gamon, k_ra8_glcdc_off_out_gamsw, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_glcdc_reg32(), ra8_log_info_val, and s_tag.

◆ ra8_glcdc_get_status()

ra8_err_t ra8_glcdc_get_status ( uint32_t * out_mask )

nodiscard

Read GLCDC status register (VSYNC/HSYNC/underflow).

Since: 0.1.0

Definition at line 828 of file ra8_glcdc.c.

References k_ra8_glcdc_off_sys_stat, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_glcdc_reg32(), and s_tag.

Referenced by gh_glcdc_programmed().

◆ ra8_glcdc_init()

ra8_err_t ra8_glcdc_init ( const ra8_glcdc_config_t * cfg )

nodiscard

Initialise GLCDC with the EK-RA8D2 1024x600 timings and the supplied graphics layer 1 framebuffer.

Since: 0.1.0

< Panel clk clksel lcdclk.

< Panel clk clken.

< Panel clk dcdr div2.

Definition at line 662 of file ra8_glcdc.c.

References ra8_glcdc_config_t::format, ra8_glcdc_config_t::framebuffer_addr, ra8_glcdc_config_t::height_px, internal_graphics_power_on(), internal_panel_program(), k_ra8_glcdc_off_bg_en, k_ra8_glcdc_off_panel_clk, k_ra8_mstp_glcdc, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_glcdc_reg32(), ra8_log_info_val, ra8_mstp_enable(), RA8_RETURN_ON_ERROR, s_tag, ra8_glcdc_config_t::timing, and ra8_glcdc_config_t::width_px.

Referenced by internal_lcd_bringup_panel(), internal_lcd_bringup_panel(), and ra8_nsc_glcdc_init().

◆ ra8_glcdc_layer1_show()

ra8_err_t ra8_glcdc_layer1_show ( uintptr_t fb_addr )

nodiscard

Make graphics layer 1 visible by pointing it at a framebuffer.

Flips GR1 from the default hidden state (DISPSEL=transparent, FLMRD=0, alpha=0) into "show this framebuffer" mode:

GR1.FLM2.SADDR = fb_addr (framebuffer base)
GR1.AB7.ARCDEF = 0xFF (fully opaque)
GR1.AB1.DISPSEL = non_transparent (current layer drawn)
GR1.FLMRD.RENB = 1 (enable AXI fetch)
GR1.VEN = 1 (commit on next VS)

Width / height / format / position were already programmed by ra8_glcdc_init; the caller just provides the new framebuffer pointer. Caller is responsible for filling the framebuffer in cache-coherent fashion (writes to 0x60000000-0x9FFFFFFF SDRAM are non-cacheable by the Cortex-M85 default memory map).

Parameters

[in] fb_addr Base address of the layer-1 framebuffer (must match the format passed to ra8_glcdc_init; alignment is implementation defined, 64-byte AXI burst boundary is safe).

Returns: Error code.

Return values

k_ra8_ok	Layer 1 enabled.
k_ra8_err_invalid_state	GLCDC not in DISPLAYING state.

Precondition: ra8_glcdc_init and ra8_glcdc_start have been called.; fb_addr points to a valid framebuffer of the dimensions passed to ra8_glcdc_init.

Postcondition: GR1 fetches and composites pixels from fb_addr.; Layer-1 changes are visible from the next vertical sync.

Note: Single-threaded; not safe to call from IRQ.

Since: 0.1.0

Make graphics layer 1 visible by pointing it at a framebuffer.

See header for caller-facing contract. Writes SADDR, alpha=0xFF, DISPSEL=non_transparent, FLMRD=1, then asserts GR1.VEN so the chip commits the layer-1 visibility flip at the next VS.

Parameters

[in] fb_addr Framebuffer base address (see header for dims).

Returns: Always k_ra8_ok (writes can't fail at this point).

Return values

k_ra8_ok Layer 1 visible from next VS.

Precondition: ra8_glcdc_init and ra8_glcdc_start have run.; fb_addr is valid for the framebuffer size from init.

Postcondition: GR1 fetches and composites pixels from fb_addr.; GR1.VEN is asserted (auto-clears at next VS).

Note: Single-threaded; not safe to call from IRQ.

Since: 0.1.0

< Gr1 ven.

< AB1.DISPSEL = ON_LOWER (FSP's BLEND_ON_LOWER_LAYER).

Definition at line 234 of file ra8_glcdc_layer.c.

References k_glcdc_alpha_opaque, k_glcdc_shift_arcdef, k_ra8_glcdc_off_gr1_ab1, k_ra8_glcdc_off_gr1_ab7, k_ra8_glcdc_off_gr1_en, k_ra8_glcdc_off_gr1_flmrd, k_ra8_glcdc_off_gr1_saddr, k_ra8_ok, and ra8_glcdc_reg32().

Referenced by internal_lcd_bringup_panel().

◆ ra8_glcdc_layer2_chroma_key_enable()

ra8_err_t ra8_glcdc_layer2_chroma_key_enable ( uint32_t key_rgb888 )

nodiscard

Enable chroma-key transparency on graphics layer 2.

Pixels in GR2's framebuffer whose RGB888 expansion matches key_rgb888 are treated as fully transparent at composite time – the layer below (BG plane) shows through those pixels. All other pixels remain opaque. This lets a single RGB565 GR2 layer host multiple opaque shapes with the BG plane visible between them.

Caller-provided key is in 0xRRGGBB form (alpha is ignored). For an RGB565 framebuffer, paint matching pixels with the RGB565 word whose 5/6/5-to-8/8/8 expansion equals key_rgb888 (e.g. magenta: paint 0xF81F into the fb and pass 0xFF00FF here).

Parameters

[in] key_rgb888 Chroma-key match colour in 0x00RRGGBB form.

Returns: ra8_err_t

Return values

k_ra8_ok Chroma-key enabled; takes effect on next vsync.

Precondition: ra8_glcdc_layer2_show has been called.

Postcondition: GR2.AB7.CKON = 1, GR2.AB8 = key, GR2.AB9 = transparent.; GR2.VEN is asserted (auto-clears on next vsync).

Note: Single-threaded; not safe to call from IRQ.

Since: 0.1.0

Enable chroma-key transparency on graphics layer 2.

Programmes GR2.AB8 / AB9 with the match/replace colour pair so that every framebuffer pixel matching key_rgb888 composites with alpha=0 (i.e. the lower layer / BG plane shows through). Also asserts the AB1.ARCON bit because some RA parts gate the per-pixel alpha replacement behind ARCON; without it the compositor clamps alpha back to AB7.ARCDEF (0xFF) and the pixel stays opaque. See HUM Ch 63 for the AB7 / AB8 / AB9 layouts.

Parameters

[in] key_rgb888 Chroma-key match colour, 0x00RRGGBB. The function adds an explicit alpha=0xFF for the comparator and masks the supplied value to 24 bits, so callers may pass either 0x00RRGGBB or 0xFFRRGGBB.

Returns: ra8_err_t

Return values

k_ra8_ok Chroma-key enabled; effect lands at next vsync.

Precondition: ra8_glcdc_layer2_show has run (GR2 has a framebuffer and panel position).; Caller serialises GLCDC register access (single-threaded init context, or interrupts masked).

Postcondition: GR2.AB7.CKON=1, GR2.AB8 holds the match colour, GR2.AB9 holds (0, transparent).; GR2.VEN is asserted (auto-clears at next vsync).

Note: Not thread-safe; not ISR-safe.

Since: 0.1.0

< Gr2 ven.

Ab7 ckon.

Ab1 arcon.

Arcdef op.

< AB8 alpha-byte = opaque.

< 24-bit colour mask.

< AB9 = alpha-0 replace.

Definition at line 284 of file ra8_glcdc_layer.c.

References k_glcdc_alpha_opaque, k_glcdc_shift_arcdef, k_ra8_glcdc_off_gr2_ab1, k_ra8_glcdc_off_gr2_ab7, k_ra8_glcdc_off_gr2_ab8, k_ra8_glcdc_off_gr2_ab9, k_ra8_glcdc_off_gr2_en, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_layer2_show()

ra8_err_t ra8_glcdc_layer2_show	(	uintptr_t	fb_addr,
		uint16_t	panel_x,
		uint16_t	panel_y,
		uint16_t	fb_w,
		uint16_t	fb_h )

nodiscard

Make graphics layer 2 visible at an arbitrary panel position.

Sets GR2's framebuffer pointer / stride / dimensions / position registers and pulses VEN to commit on the next vsync. The framebuffer is interpreted as RGB565.

Parameters

[in]	fb_addr	Base address of the layer-2 framebuffer (RGB565).
[in]	panel_x	Horizontal position on the panel in GLCDC coords.
[in]	panel_y	Vertical position on the panel in GLCDC coords.
[in]	fb_w	Framebuffer width in pixels.
[in]	fb_h	Framebuffer height in pixels.

Returns: Error code.

Return values

k_ra8_ok Layer 2 enabled.

Precondition: ra8_glcdc_init and ra8_glcdc_start have been called.; fb_addr points to an fb_w * fb_h * 2-byte RGB565 framebuffer.

Postcondition: GR2 fetches and composites pixels from fb_addr at (panel_x, panel_y).; Layer-2 changes are visible from the next vertical sync.

Note: Single-threaded; not safe to call from IRQ.

Since: 0.1.0

Make graphics layer 2 visible at an arbitrary panel position.

Programmes GR2's framebuffer pointer, line stride, line count, panel position, alpha, DISPSEL, FLMRD, and asserts GR2.VEN to latch on the next vertical sync. The framebuffer format is hard-coded to RGB565; for other formats use the chroma-key helper after this call.

Parameters

[in]	fb_addr	Layer-2 framebuffer base (RGB565).
[in]	panel_x	Horizontal panel position (GLCDC coords).
[in]	panel_y	Vertical panel position (GLCDC coords).
[in]	fb_w	Framebuffer width in pixels.
[in]	fb_h	Framebuffer height in pixels.

Returns: ra8_err_t

Return values

k_ra8_ok Layer 2 visible from next vsync.

Precondition: ra8_glcdc_init and ra8_glcdc_start have been called.; fb_addr points to an fb_w * fb_h * 2-byte RGB565 framebuffer.

Postcondition: GR2 composites pixels from fb_addr at (panel_x, panel_y).; GR2.VEN is asserted (auto-clears at next vsync).

Note: Single-threaded; not safe to call from IRQ.

Since: 0.1.0

< Gr2 ven.

< AB1.DISPSEL = ON_LOWER (FSP's BLEND_ON_LOWER_LAYER).

Definition at line 340 of file ra8_glcdc_layer.c.

References k_glcdc_alpha_opaque, k_glcdc_axi_burst_bytes, k_glcdc_bpp_rgb565, k_glcdc_out_set_rgb565, k_glcdc_shift_arcdef, k_glcdc_shift_flm6_fmt, k_glcdc_shift_high, k_ra8_glcdc_off_gr2_ab1, k_ra8_glcdc_off_gr2_ab2, k_ra8_glcdc_off_gr2_ab4, k_ra8_glcdc_off_gr2_ab5, k_ra8_glcdc_off_gr2_ab7, k_ra8_glcdc_off_gr2_en, k_ra8_glcdc_off_gr2_flm3, k_ra8_glcdc_off_gr2_flmrd, k_ra8_glcdc_off_gr2_fmt, k_ra8_glcdc_off_gr2_line, k_ra8_glcdc_off_gr2_saddr, k_ra8_glcdc_off_gr2_size, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_set_background_color()

ra8_err_t ra8_glcdc_set_background_color ( uint32_t argb )

nodiscard

Set the panel-wide background colour shown where neither layer covers a pixel.

Writes argb to BG.BGC. The alpha byte is ignored by hardware but preserved in the register for symmetry with the layer-base colour registers.

Parameters

[in] argb 0xAARRGGBB packed colour.

Returns: ra8_err_t

Return values

k_ra8_ok Always.

Since: 0.1.0

< Bg en ven.

< > 1 frame at 1 GHz CPU.

Definition at line 186 of file ra8_glcdc_layer.c.

References k_ra8_glcdc_off_bg_bgc, k_ra8_glcdc_off_bg_en, k_ra8_ok, and ra8_glcdc_reg32().

Referenced by internal_lcd_bringup_panel(), internal_lcd_bringup_panel(), and main().

◆ ra8_glcdc_set_blend()

ra8_err_t ra8_glcdc_set_blend	(	ra8_glcdc_blend_mode_t	mode,
		uint8_t	global_alpha )

nodiscard

Set the layer-1-over-layer-2 blend mode and global alpha.

Writes layer-1 AB1.DISPSEL / AB1.ARCON and AB7.ARCDEF to select "overwrite", "normal" (top opaque over bottom), or "alpha" (top blended over bottom using per-pixel alpha multiplied by the global alpha argument).

Parameters

[in]	mode	Compositing mode.
[in]	global_alpha	0..255 constant alpha applied in k_ra8_blend_alpha mode (AB7.ARCDEF).

Returns: ra8_err_t

Return values

k_ra8_ok	Blend programmed successfully.
k_ra8_err_invalid_arg	mode was out of range.

Since: 0.1.0

Definition at line 146 of file ra8_glcdc_layer.c.

References k_ra8_blend_alpha, k_ra8_blend_normal, k_ra8_blend_overwrite, k_ra8_err_invalid_arg, k_ra8_glcdc_arcdef_shift, k_ra8_glcdc_arcon_mask, k_ra8_glcdc_dispsel_above, k_ra8_glcdc_dispsel_below, k_ra8_glcdc_off_gr1_ab1, k_ra8_glcdc_off_gr1_ab7, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_set_brightness()

ra8_err_t ra8_glcdc_set_brightness	(	uint8_t	r,
		uint8_t	g,
		uint8_t	b )

nodiscard

Programme per-channel output brightness.

Writes g to BRIGHT1.BRTG and packs b/r into BRIGHT2.BRTB/BRTR. The values are 8-bit offsets that are added to the 10-bit channel (the low bits of the 10-bit BRTx field are left as 0 – callers wanting the full range supply pre-scaled numbers in the 0..255 portion).

Parameters

[in]	r	Red brightness offset (0..255).
[in]	g	Green brightness offset (0..255).
[in]	b	Blue brightness offset (0..255).

Returns: ra8_err_t

Return values

k_ra8_ok Always.

Since: 0.1.0

Definition at line 791 of file ra8_glcdc.c.

References k_ra8_glcdc_off_out_bright1, k_ra8_glcdc_off_out_bright2, k_ra8_glcdc_word_shift, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_set_clut_double_buffered()

ra8_err_t ra8_glcdc_set_clut_double_buffered	(	uint8_t	layer,
		const uint32_t *	clut,
		uint32_t	entries,
		bool	swap_now )

nodiscard

Update a CLUT plane double-buffered, optionally swapping on the next vsync.

GLCDC keeps two CLUT planes per layer (CLUT0/CLUT1) selected by GR[layer].CLUTINT.SEL. This function writes entries 32-bit ARGB entries into the inactive plane, then either:

leaves SEL alone (swap_now == false): the new table sits ready for a future swap, mirroring FSP's R_GLCDC_ClutEdit "shadow" pattern, or
flips SEL (swap_now == true): the hardware will switch to the freshly-written table at the next vertical sync, mirroring FSP's R_GLCDC_ColorPaletteUpdate.

Parameters

[in]	layer	0 = Graphics 1, 1 = Graphics 2.
[in]	clut	Source array of ARGB8888 entries.
[in]	entries	Number of entries to copy (1..256).
[in]	swap_now	true to flip CLUTINT.SEL after the write.

Returns: ra8_err_t

Return values

k_ra8_ok	Programmed successfully.
k_ra8_err_null_ptr	clut was NULL.
k_ra8_err_invalid_arg	layer >= 2 or entries out of range.

Since: 0.1.0

Definition at line 411 of file ra8_glcdc_layer.c.

References internal_clut_plane(), internal_clutint_reg(), k_ra8_err_invalid_arg, k_ra8_glcdc_clut_entries, k_ra8_glcdc_clutsel_mask, k_ra8_glcdc_clutsel_shift, k_ra8_glcdc_layer_count, k_ra8_ok, RA8_CHECK_NULL_PTR, and s_tag.

◆ ra8_glcdc_set_contrast()

ra8_err_t ra8_glcdc_set_contrast	(	uint8_t	r,
		uint8_t	g,
		uint8_t	b )

nodiscard

Programme per-channel output contrast gain.

Writes the three 8-bit gains into CONTRAST.CONTG/CONTB/CONTR. 0x80 == x1.000 gain (FSP convention).

Parameters

[in]	r	Red contrast gain (0..255, 0x80 = 1.0).
[in]	g	Green contrast gain (0..255, 0x80 = 1.0).
[in]	b	Blue contrast gain (0..255, 0x80 = 1.0).

Returns: ra8_err_t

Return values

k_ra8_ok Always.

Since: 0.1.0

Definition at line 802 of file ra8_glcdc.c.

References k_ra8_glcdc_b_shift, k_ra8_glcdc_g_shift, k_ra8_glcdc_off_out_contrast, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_set_dithering()

ra8_err_t ra8_glcdc_set_dithering ( ra8_glcdc_dither_mode_t mode )

nodiscard

Programme the output dithering mode (PDTHA.SEL).

Selects the dithering algorithm applied when the 24bpp internal pipeline drives a narrower (18bpp / 16bpp) panel.

Parameters

[in] mode Dither mode.

Returns: ra8_err_t

Return values

k_ra8_ok	Dither register written.
k_ra8_err_invalid_arg	mode was out of range.

Since: 0.1.0

Definition at line 766 of file ra8_glcdc.c.

References k_ra8_dither_2x2, k_ra8_dither_off, k_ra8_dither_truncate, k_ra8_err_invalid_arg, k_ra8_glcdc_off_panel_dtha, k_ra8_glcdc_pdtha_shift, k_ra8_ok, and ra8_glcdc_reg32().

◆ ra8_glcdc_set_gamma()

ra8_err_t ra8_glcdc_set_gamma	(	ra8_glcdc_color_channel_t	channel,
		const uint16_t *	gain,
		const uint16_t *	threshold,
		uint8_t	count )

nodiscard

Programme the piecewise-linear gamma correction table for one channel.

Writes the 8 GAMx_LUTn gain-pair registers and the 8 GAMx_AREAn threshold-pair registers for the selected colour channel. Each LUT register packs two 11-bit gain coefficients (GAIN0 in bits[26:16], GAIN1 in bits[10:0]); each AREA register packs two 10-bit boundary values (TH1 in bits[25:16], TH2 in bits[9:0]). Call ra8_glcdc_gamma_enable(true) after programming all three channels to activate the correction pipeline.

Parameters

[in]	channel	Colour channel to program (R, G, or B).
[in]	gain	Array of k_ra8_glcdc_gamma_lut_depth 11-bit gain values (0..2047). gain[0] corresponds to GAIN0 of LUT[0].
[in]	threshold	Array of k_ra8_glcdc_gamma_lut_depth 10-bit boundary values (0..1023). threshold[0] corresponds to TH1 of AREA[0].
[in]	count	Must equal k_ra8_glcdc_gamma_lut_depth (16); enforced.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	LUT and AREA registers written.
k_ra8_err_null_ptr	gain or threshold is NULL.
k_ra8_err_invalid_arg	channel >= k_ra8_glcdc_ch_count, or count != k_ra8_glcdc_gamma_lut_depth.

Precondition: GLCDC has been initialised via ra8_glcdc_init().; gain and threshold point to arrays of at least count elements.

Postcondition: All 8 GAMx_LUTn registers hold the packed gain pairs.; All 8 GAMx_AREAn registers hold the packed threshold pairs.

Note: Not thread-safe; caller must serialise access to GLCDC registers.

See also: ra8_glcdc_gamma_enable() Activate or deactivate the pipeline.

Since: 0.1.0

HUM:: Ch 63 "GAMx_LUTn Gamma Correction LUT Register" p 3790. Ch 63 "GAMx_AREAn Gamma Correction Area Register" p 3793.

Definition at line 131 of file ra8_glcdc_gamma.c.

References internal_write_area(), internal_write_lut(), k_ra8_err_invalid_arg, k_ra8_glcdc_ch_count, k_ra8_glcdc_gamma_lut_depth, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_glcdc_gam_regs(), ra8_log_info_val, and s_tag.

◆ ra8_glcdc_set_layer2()

ra8_err_t ra8_glcdc_set_layer2 ( const ra8_glcdc_layer2_cfg_t * cfg )

nodiscard

Configure the Graphics 2 (background-image) layer.

Programmes the per-layer GR2 register block (FLM2/FLM3/FLM5/FLM6/ AB1..AB7) so the layer is read from cfg->framebuffer_addr, placed at (cfg->pos_x, cfg->pos_y) inside the panel viewport with size (cfg->width_px, cfg->height_px), and treated as the lower layer in the blender. The constant alpha is loaded into AB7.ARCDEF and gated by AB1.ARCON when the active blend mode is k_ra8_blend_alpha.

Parameters

[in] cfg Layer configuration. Must be non-NULL.

Returns: ra8_err_t

Return values

k_ra8_ok	Layer 2 programmed successfully.
k_ra8_err_null_ptr	cfg was NULL.

Precondition: GLCDC has been opened via ra8_glcdc_init.; cfg->framebuffer_addr is valid for the chosen pixel format.

Postcondition: GR2_FLM2 == cfg->framebuffer_addr.; GR2 layer is enabled for read (FLMRD.RENB = 1).

Note: Not thread-safe; caller serialises register access.

Since: 0.1.0

Definition at line 91 of file ra8_glcdc_layer.c.

References ra8_glcdc_layer2_cfg_t::alpha, ra8_glcdc_layer2_cfg_t::format, ra8_glcdc_layer2_cfg_t::framebuffer_addr, ra8_glcdc_layer2_cfg_t::height_px, k_ra8_glcdc_arcdef_shift, k_ra8_glcdc_dispsel_below, k_ra8_glcdc_off_gr2_ab1, k_ra8_glcdc_off_gr2_ab2, k_ra8_glcdc_off_gr2_ab4, k_ra8_glcdc_off_gr2_ab5, k_ra8_glcdc_off_gr2_ab7, k_ra8_glcdc_off_gr2_en, k_ra8_glcdc_off_gr2_flm3, k_ra8_glcdc_off_gr2_flmrd, k_ra8_glcdc_off_gr2_fmt, k_ra8_glcdc_off_gr2_line, k_ra8_glcdc_off_gr2_saddr, k_ra8_glcdc_off_gr2_size, k_ra8_glcdc_word_shift, k_ra8_ok, ra8_glcdc_layer2_cfg_t::line_stride_bytes, ra8_glcdc_layer2_cfg_t::pos_x, ra8_glcdc_layer2_cfg_t::pos_y, RA8_CHECK_NULL_PTR, ra8_glcdc_reg32(), ra8_log_info_val, s_tag, and ra8_glcdc_layer2_cfg_t::width_px.

◆ ra8_glcdc_start()

ra8_err_t ra8_glcdc_start ( bool enable )

nodiscard

Start or stop the panel output.

Since: 0.1.0

< Bit en.

< Bit ven.

< Bit swrst.

Definition at line 709 of file ra8_glcdc.c.

References k_ra8_glcdc_off_bg_en, k_ra8_glcdc_off_gr1_en, k_ra8_glcdc_off_gr2_en, k_ra8_glcdc_off_out_vlatch, k_ra8_glcdc_off_sys_cfg, k_ra8_ok, and ra8_glcdc_reg32().

Referenced by internal_lcd_bringup_panel(), and internal_lcd_bringup_panel().

Data Structures

Typedefs

Enumerations

Functions

Detailed Description

Typedef Documentation

◆ ra8_glcdc_event_fn_t

Enumeration Type Documentation

◆ ra8_glcdc_blend_mode_t

◆ ra8_glcdc_color_channel_t

◆ ra8_glcdc_dither_mode_t

◆ ra8_glcdc_gamma_lut_const_t

Function Documentation

◆ ra8_glcdc_attach_handler()

◆ ra8_glcdc_clear_status()

◆ ra8_glcdc_deinit()

◆ ra8_glcdc_dispatch()

◆ ra8_glcdc_enter_stop()

◆ ra8_glcdc_exit_stop()

◆ ra8_glcdc_gamma_enable()

◆ ra8_glcdc_get_status()

◆ ra8_glcdc_init()

◆ ra8_glcdc_layer1_show()

◆ ra8_glcdc_layer2_chroma_key_enable()

◆ ra8_glcdc_layer2_show()

◆ ra8_glcdc_set_background_color()

◆ ra8_glcdc_set_blend()

◆ ra8_glcdc_set_brightness()

◆ ra8_glcdc_set_clut_double_buffered()

◆ ra8_glcdc_set_contrast()

◆ ra8_glcdc_set_dithering()

◆ ra8_glcdc_set_gamma()

◆ ra8_glcdc_set_layer2()

◆ ra8_glcdc_start()