ra8_glcdc_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
 
typedef enum : uintptr_t {
  k_ra8_glcdc_base_addr    = 0x40342000UL, 
  k_ra8_mipi_dsi_base_addr = 0x40346000UL, 
  k_ra8_mipi_phy_base_addr = 0x40346C00UL, 
  k_ra8_mipi_csi_base_addr = 0x40347000UL, 
  k_ra8_ceu_base_addr      = 0x40348000UL, 
} ra8_display_addr_t;

typedef enum : uint16_t {
  /* ---- Graphics 1 CLUT planes ------------------------------------------ */
  k_ra8_glcdc_off_gr1_clut0 = 0x0000U, 
  k_ra8_glcdc_off_gr1_clut1 = 0x0400U, 
  k_ra8_glcdc_off_gr2_clut0 = 0x0800U, 
  k_ra8_glcdc_off_gr2_clut1 = 0x0C00U, 
 
  /* ---- Background block ------------------------------------------------ */
  k_ra8_glcdc_off_bg_en    = 0x1000U, 
  k_ra8_glcdc_off_bg_per   = 0x1004U, 
  k_ra8_glcdc_off_bg_sync  = 0x1008U, 
  k_ra8_glcdc_off_bg_vsize = 0x100CU, 
  k_ra8_glcdc_off_bg_hsize = 0x1010U, 
  k_ra8_glcdc_off_bg_bgc   = 0x1014U, 
  k_ra8_glcdc_off_bg_mon   = 0x1018U, 
 
  /* ---- Graphics layer 0 (GR[0]) ---------------------------------------- */
  k_ra8_glcdc_off_gr1_en      = 0x1100U, 
  k_ra8_glcdc_off_gr1_flmrd   = 0x1104U, 
  k_ra8_glcdc_off_gr1_flm1    = 0x1108U, 
  k_ra8_glcdc_off_gr1_saddr   = 0x110CU, 
  k_ra8_glcdc_off_gr1_flm3    = 0x1110U, 
  k_ra8_glcdc_off_gr1_line    = 0x1118U, 
  k_ra8_glcdc_off_gr1_fmt     = 0x111CU, 
  k_ra8_glcdc_off_gr1_ab1     = 0x1120U, 
  k_ra8_glcdc_off_gr1_ab2     = 0x1124U, 
  k_ra8_glcdc_off_gr1_size    = 0x1128U, 
  k_ra8_glcdc_off_gr1_ab4     = 0x112CU, 
  k_ra8_glcdc_off_gr1_ab5     = 0x1130U, 
  k_ra8_glcdc_off_gr1_ab6     = 0x1134U, 
  k_ra8_glcdc_off_gr1_ab7     = 0x1138U, 
  k_ra8_glcdc_off_gr1_ab8     = 0x113CU, 
  k_ra8_glcdc_off_gr1_ab9     = 0x1140U, 
  k_ra8_glcdc_off_gr1_base    = 0x114CU, 
  k_ra8_glcdc_off_gr1_clutint = 0x1150U, 
  k_ra8_glcdc_off_gr1_mon     = 0x1154U, 
 
  /* ---- Graphics layer 1 (GR[1]) ---------------------------------------- */
  k_ra8_glcdc_off_gr2_en      = 0x1200U, 
  k_ra8_glcdc_off_gr2_flmrd   = 0x1204U, 
  k_ra8_glcdc_off_gr2_flm1    = 0x1208U, 
  k_ra8_glcdc_off_gr2_saddr   = 0x120CU, 
  k_ra8_glcdc_off_gr2_flm3    = 0x1210U, 
  k_ra8_glcdc_off_gr2_line    = 0x1218U, 
  k_ra8_glcdc_off_gr2_fmt     = 0x121CU, 
  k_ra8_glcdc_off_gr2_ab1     = 0x1220U, 
  k_ra8_glcdc_off_gr2_ab2     = 0x1224U, 
  k_ra8_glcdc_off_gr2_size    = 0x1228U, 
  k_ra8_glcdc_off_gr2_ab4     = 0x122CU, 
  k_ra8_glcdc_off_gr2_ab5     = 0x1230U, 
  k_ra8_glcdc_off_gr2_ab6     = 0x1234U, 
  k_ra8_glcdc_off_gr2_ab7     = 0x1238U, 
  k_ra8_glcdc_off_gr2_ab8     = 0x123CU, 
  k_ra8_glcdc_off_gr2_ab9     = 0x1240U, 
  k_ra8_glcdc_off_gr2_base    = 0x124CU, 
  k_ra8_glcdc_off_gr2_clutint = 0x1250U, 
  k_ra8_glcdc_off_gr2_mon     = 0x1254U, 
 
  /* ---- Gamma correction (GAM[0..2]) ------------------------------------ */
  k_ra8_glcdc_off_gam0 = 0x1300U, 
  k_ra8_glcdc_off_gam1 = 0x1340U, 
  k_ra8_glcdc_off_gam2 = 0x1380U, 
 
  /* ---- Output control block (OUT) -------------------------------------- */
  k_ra8_glcdc_off_out_vlatch   = 0x13C0U, 
  k_ra8_glcdc_off_out_set      = 0x13C4U, 
  k_ra8_glcdc_off_out_bright1  = 0x13C8U, 
  k_ra8_glcdc_off_out_bright2  = 0x13CCU, 
  k_ra8_glcdc_off_out_contrast = 0x13D0U, 
  k_ra8_glcdc_off_panel_dtha   = 0x13D4U, 
  k_ra8_glcdc_off_out_gamsw    = 0x13D8U, 
  k_ra8_glcdc_off_out_clkphase = 0x13E4U, 
 
  /* ---- Timing control block (TCON) ------------------------------------- */
  k_ra8_glcdc_off_tcon_tim   = 0x1404U, 
  k_ra8_glcdc_off_tcon_stva1 = 0x1408U, 
  k_ra8_glcdc_off_tcon_stva2 = 0x140CU, 
  k_ra8_glcdc_off_tcon_stvb1 = 0x1410U, 
  k_ra8_glcdc_off_tcon_stvb2 = 0x1414U, 
  k_ra8_glcdc_off_tcon_stha1 = 0x1418U, 
  k_ra8_glcdc_off_tcon_stha2 = 0x141CU, 
  k_ra8_glcdc_off_tcon_sthb1 = 0x1420U, 
  k_ra8_glcdc_off_tcon_sthb2 = 0x1424U, 
  k_ra8_glcdc_off_tcon_de    = 0x1428U, 
 
  /* ---- System control block (SYSCNT) ----------------------------------- */
  k_ra8_glcdc_off_sys_cfg   = 0x1440U, 
  k_ra8_glcdc_off_sys_intr  = 0x1444U, 
  k_ra8_glcdc_off_sys_clr   = 0x1448U, 
  k_ra8_glcdc_off_sys_stat  = 0x144CU, 
  k_ra8_glcdc_off_panel_clk = 0x1450U, 
} ra8_glcdc_block_off_t;

typedef enum : uint8_t {
  k_ra8_glcdc_fmt_argb8888 = 0x0U, 
  k_ra8_glcdc_fmt_rgb888   = 0x1U, 
  k_ra8_glcdc_fmt_rgb565   = 0x2U, 
  k_ra8_glcdc_fmt_argb1555 = 0x3U, 
  k_ra8_glcdc_fmt_argb4444 = 0x4U, 
  k_ra8_glcdc_fmt_clut8    = 0x5U, 
  k_ra8_glcdc_fmt_clut4    = 0x6U, 
  k_ra8_glcdc_fmt_clut1    = 0x7U, 
} ra8_glcdc_pixel_fmt_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_glcdc_reg32(ra8_glcdc_block_off_t offset)
{
  return (volatile uint32_t*)(k_ra8_glcdc_base_addr + (uint16_t)offset);
}
 
/* =============================================================================
 * Gamma correction register block (HUM Ch 63 "GLCDC" p 3789-3793)
 * =============================================================================
 *
 * Each of the three color channels (R=GAM[0], G=GAM[1], B=GAM[2]) occupies
 * exactly 64 bytes starting at the k_ra8_glcdc_off_gamN base.  The block
 * contains:
 *   - LUT[8] at offset 0x00: eight 32-bit registers, each holding two 11-bit
 *     gain coefficients (GAIN0 in bits[26:16], GAIN1 in bits[10:0]).
 *   - AREA[8] at offset 0x20: eight 32-bit registers, each holding two 10-bit
 *     area/threshold values (TH1 in bits[25:16], TH2 in bits[9:0]).
 * The global gamma-enable switch (GAMSW.GAMON, bit 0) lives in the shared
 * OUT control block at k_ra8_glcdc_off_out_gamsw (0x13D8).
 */

typedef struct {
  volatile uint32_t LUT[8];  
  volatile uint32_t AREA[8]; 
} ra8_glcdc_gam_t;

typedef enum : uint8_t {
  k_ra8_glcdc_gam_block_bytes = 64U, 
} ra8_glcdc_gam_size_t;
 
static_assert(sizeof(ra8_glcdc_gam_t) == (uint32_t)k_ra8_glcdc_gam_block_bytes,
              "ra8_glcdc_gam_t must be 64 bytes");

typedef enum : uint32_t {
  k_ra8_glcdc_gam_lut_gain_h_shift = 16U,          
  k_ra8_glcdc_gam_lut_gain_l_mask  = 0x000007FFUL, 
  k_ra8_glcdc_gam_area_th_h_shift  = 16U,          
  k_ra8_glcdc_gam_area_th_l_mask   = 0x000003FFUL, 
} ra8_glcdc_gam_field_t;

typedef enum : uint32_t {
  k_ra8_glcdc_gamsw_gamon = 0x00000001UL, 
} ra8_glcdc_gamsw_bits_t;

RA8_HW_REGISTER_ACCESS
static inline volatile ra8_glcdc_gam_t* ra8_glcdc_gam_regs(uint8_t channel_idx)
{
  static const uint16_t local_gam_base[3] = {
    (uint16_t)k_ra8_glcdc_off_gam0,
    (uint16_t)k_ra8_glcdc_off_gam1,
    (uint16_t)k_ra8_glcdc_off_gam2,
  };
  return (volatile ra8_glcdc_gam_t*)(k_ra8_glcdc_base_addr + local_gam_base[channel_idx]);
}
 
/* =============================================================================
 * EK-RA8D2 panel timings (1024 x 600, 7-inch parallel TFT)
 * =============================================================================
 *
 * Values taken from the FSP `board_ra8d2_ek.c` panel descriptor and
 * the panel datasheet in `docs/reference/`. These are the nominal
 * values; a real driver should read the selected panel descriptor
 * at runtime.
 */
 
typedef enum : uint16_t {
  k_ra8_glcdc_ek_h_active = 1024U, 
  k_ra8_glcdc_ek_v_active = 600U,  
  k_ra8_glcdc_ek_h_front  = 160U,  
  k_ra8_glcdc_ek_h_back   = 140U,  
  k_ra8_glcdc_ek_h_sync   = 20U,   
  k_ra8_glcdc_ek_v_front  = 12U,   
  k_ra8_glcdc_ek_v_back   = 20U,   
  k_ra8_glcdc_ek_v_sync   = 3U,    
} ra8_glcdc_ek_timing_t;
 
typedef enum : uint32_t {
  k_ra8_glcdc_ek_pixel_clk_hz = 51200000UL, 
} ra8_glcdc_ek_clk_t;
 
#ifdef __cplusplus
}
#endif