ra8_mipi_phy_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_glcdc_regs.h" /* k_ra8_mipi_phy_base_addr */

typedef enum : uint16_t {
  k_ra8_mipi_phy_off_refcr = 0x000U, 
  k_ra8_mipi_phy_off_plfcr = 0x004U, 
  k_ra8_mipi_phy_off_plocr = 0x008U, 
  k_ra8_mipi_phy_off_esccr = 0x00CU, 
  k_ra8_mipi_phy_off_pwrcr = 0x010U, 
  k_ra8_mipi_phy_off_sfr   = 0x01CU, 
  k_ra8_mipi_phy_off_ocr   = 0x020U, 
  k_ra8_mipi_phy_off_tim1  = 0x024U, 
  k_ra8_mipi_phy_off_tim2  = 0x028U, 
  k_ra8_mipi_phy_off_tim3  = 0x02CU, 
  k_ra8_mipi_phy_off_tim4  = 0x030U, 
  k_ra8_mipi_phy_off_tim5  = 0x034U, 
  k_ra8_mipi_phy_off_tim6  = 0x038U, 
  k_ra8_mipi_phy_off_mdc   = 0x048U, 
} ra8_mipi_phy_block_off_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_pwrcr_pwrsen = 0x1U, 
} ra8_mipi_phy_pwrcr_bit_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_plocr_pllstp = 0x1U, 
} ra8_mipi_phy_plocr_bit_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_ocr_dphyen = 0x1U, 
} ra8_mipi_phy_ocr_bit_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_sfr_pwrsf      = 0x001U, 
  k_ra8_mipi_phy_sfr_pllsf      = 0x100U, 
  k_ra8_mipi_phy_sfr_ready_mask = 0x101U, 
} ra8_mipi_phy_sfr_bit_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_mdc_hosten = 0x1U, 
} ra8_mipi_phy_mdc_bit_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_refcr_rfreq_mask = 0xFFU, 
} ra8_mipi_phy_refcr_mask_t;

typedef enum : uint8_t {
  k_ra8_mipi_phy_refcr_rfreq_bias = 1U, 
} ra8_mipi_phy_refcr_bias_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_esccr_escdiv_mask = 0x1FU, 
} ra8_mipi_phy_esccr_mask_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_tim1_tinit_mask = 0x0007FFFFUL, 
} ra8_mipi_phy_tim1_mask_t;

typedef enum : uint8_t {
  k_ra8_mipi_phy_tim_shift_b0 = 0U,  
  k_ra8_mipi_phy_tim_shift_b1 = 8U,  
  k_ra8_mipi_phy_tim_shift_b2 = 16U, 
  k_ra8_mipi_phy_tim_shift_b3 = 24U, 
} ra8_mipi_phy_tim_byte_shift_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_tim_byte_mask = 0xFFU, 
} ra8_mipi_phy_tim_byte_mask_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_tim6_tlpx_mask = 0xFFU, 
} ra8_mipi_phy_tim6_mask_t;

typedef enum : uint8_t {
  k_ra8_mipi_phy_plfcr_shift_idiv  = 0U,  
  k_ra8_mipi_phy_plfcr_shift_nfmul = 8U,  
  k_ra8_mipi_phy_plfcr_shift_pmul  = 12U, 
  k_ra8_mipi_phy_plfcr_shift_nmul  = 16U, 
} ra8_mipi_phy_pll_field_shift_t;

typedef enum : uint32_t {
  k_ra8_mipi_phy_plfcr_mask_idiv  = 0x003U, 
  k_ra8_mipi_phy_plfcr_mask_nfmul = 0x003U, 
  k_ra8_mipi_phy_plfcr_mask_pmul  = 0x003U, 
  k_ra8_mipi_phy_plfcr_mask_nmul  = 0x1FFU, 
} ra8_mipi_phy_pll_field_mask_t;

typedef enum : uint16_t {
  k_ra8_mipi_phy_line_rate_min_mbps = 80U,  
  k_ra8_mipi_phy_line_rate_max_mbps = 720U, 
} ra8_mipi_phy_lane_speed_limit_t;

typedef enum : uint16_t {
  k_ra8_mipi_phy_vco_min_mhz = 960U,  
  k_ra8_mipi_phy_vco_max_mhz = 3000U, 
  k_ra8_mipi_phy_pll_p1_min  = 960U,  
  k_ra8_mipi_phy_pll_p1_max  = 1440U, 
  k_ra8_mipi_phy_pll_p2_min  = 480U,  
  k_ra8_mipi_phy_pll_p2_max  = 1440U, 
  k_ra8_mipi_phy_pll_p4_min  = 240U,  
  k_ra8_mipi_phy_pll_p4_max  = 750U,  
  k_ra8_mipi_phy_pll_p8_min  = 120U,  
  k_ra8_mipi_phy_pll_p8_max  = 375U,  
} ra8_mipi_phy_pll_band_t;

typedef enum : uint8_t {
  k_ra8_mipi_phy_mosc_min_mhz   = 8U,  
  k_ra8_mipi_phy_mosc_max_mhz   = 48U, 
  k_ra8_mipi_phy_pll_in_min_mhz = 8U,  
  k_ra8_mipi_phy_pll_in_max_mhz = 24U, 
  k_ra8_mipi_phy_lp_clk_min_mhz = 2U,  
  k_ra8_mipi_phy_lp_clk_max_mhz = 17U, 
} ra8_mipi_phy_input_clk_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_mipi_phy_reg32(ra8_mipi_phy_block_off_t offset)
{
  return (volatile uint32_t*)(k_ra8_mipi_phy_base_addr + (uintptr_t)offset);
}
 
#ifdef __cplusplus
}
#endif