ra8_mipi_dsi_types.h

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#pragma once
 
#include <stdint.h>
 
#include "ra8_err.h"
#include "ra8_mipi_dsi_regs.h"

typedef enum : uint8_t {
  k_ra8_mipi_dsi_lanes_1 = 1U, 
  k_ra8_mipi_dsi_lanes_2 = 2U, 
} ra8_mipi_dsi_lane_count_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_clock_non_continuous = 0U, 
  k_ra8_mipi_dsi_clock_continuous     = 1U, 
} ra8_mipi_dsi_clock_mode_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_vc0 = 0U, 
  k_ra8_mipi_dsi_vc1 = 1U, 
  k_ra8_mipi_dsi_vc2 = 2U, 
  k_ra8_mipi_dsi_vc3 = 3U, 
} ra8_mipi_dsi_vc_t;

typedef enum : uint8_t {
  /* Short packet writes */
  k_ra8_mipi_dsi_dt_v_sync_start        = 0x01U, 
  k_ra8_mipi_dsi_dt_v_sync_end          = 0x11U, 
  k_ra8_mipi_dsi_dt_h_sync_start        = 0x21U, 
  k_ra8_mipi_dsi_dt_h_sync_end          = 0x31U, 
  k_ra8_mipi_dsi_dt_none                = 0x00U, 
  k_ra8_mipi_dsi_dt_color_mode_off      = 0x02U, 
  k_ra8_mipi_dsi_dt_color_mode_on       = 0x12U, 
  k_ra8_mipi_dsi_dt_shutdown_peripheral = 0x22U, 
  k_ra8_mipi_dsi_dt_turn_on_peripheral  = 0x32U, 
  k_ra8_mipi_dsi_dt_compression_mode    = 0x07U, 
  k_ra8_mipi_dsi_dt_end_of_transmission = 0x08U, 
  k_ra8_mipi_dsi_dt_dcs_short_write_0   = 0x05U, 
  k_ra8_mipi_dsi_dt_dcs_short_write_1   = 0x15U, 
  k_ra8_mipi_dsi_dt_gen_short_write_0   = 0x03U, 
  k_ra8_mipi_dsi_dt_gen_short_write_1   = 0x13U, 
  k_ra8_mipi_dsi_dt_gen_short_write_2   = 0x23U, 
  k_ra8_mipi_dsi_dt_gen_read_0          = 0x04U, 
  k_ra8_mipi_dsi_dt_gen_read_1          = 0x14U, 
  k_ra8_mipi_dsi_dt_gen_read_2          = 0x24U, 
  k_ra8_mipi_dsi_dt_dcs_read            = 0x06U, 
  k_ra8_mipi_dsi_dt_execute_queue       = 0x16U, 
  k_ra8_mipi_dsi_dt_set_max_return_pkt  = 0x37U, 
  /* Long packet writes */
  k_ra8_mipi_dsi_dt_null_packet     = 0x09U, 
  k_ra8_mipi_dsi_dt_blanking_packet = 0x19U, 
  k_ra8_mipi_dsi_dt_gen_long_write  = 0x29U, 
  k_ra8_mipi_dsi_dt_dcs_long_write  = 0x39U, 
  /* Pixel stream long packets */
  k_ra8_mipi_dsi_dt_pixel_rgb565       = 0x0EU, 
  k_ra8_mipi_dsi_dt_pixel_rgb666       = 0x1EU, 
  k_ra8_mipi_dsi_dt_pixel_rgb666_loose = 0x2EU, 
  k_ra8_mipi_dsi_dt_pixel_rgb888       = 0x3EU, 
} ra8_mipi_dsi_dt_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_lane_none  = 0U,      
  k_ra8_mipi_dsi_lane_clock = 1U << 0, 
  k_ra8_mipi_dsi_lane_data  = 1U << 1, 
  k_ra8_mipi_dsi_lane_all   = (uint8_t)((1U << 0) | (1U << 1)),
} ra8_mipi_dsi_lane_sel_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_event_seq0    = 0U, 
  k_ra8_mipi_dsi_event_seq1    = 1U, 
  k_ra8_mipi_dsi_event_video   = 2U, 
  k_ra8_mipi_dsi_event_receive = 3U, 
  k_ra8_mipi_dsi_event_fatal   = 4U, 
  k_ra8_mipi_dsi_event_phy     = 5U, 
} ra8_mipi_dsi_event_t;

typedef struct {
  uint16_t clock_stop_time;       
  uint8_t  clock_beforehand_time; 
  uint8_t  clock_keep_time;       
  uint16_t go_lp_and_back;        
} ra8_mipi_dsi_timing_t;

typedef struct {
  uint32_t hs_tx_timeout;      
  uint32_t lp_rx_host_timeout; 
  uint32_t turnaround_timeout; 
  uint32_t bta_timeout;        
  uint32_t lp_rw_timeout;      
  uint32_t hs_rw_timeout;      
} ra8_mipi_dsi_timeouts_t;

typedef struct {
  ra8_mipi_dsi_dt_t pixel_format;             
  ra8_mipi_dsi_vc_t virtual_channel;          
  bool              sync_pulse;               
  bool              hsa_no_lp;                
  bool              hbp_no_lp;                
  bool              hfp_no_lp;                
  bool              vsync_active_high;        
  bool              hsync_active_high;        
  uint16_t          vertical_sync_lines;      
  uint16_t          vertical_active_lines;    
  uint16_t          vertical_back_porch;      
  uint16_t          vertical_front_porch;     
  uint16_t          horizontal_sync_lines;    
  uint16_t          horizontal_active_pixels; 
  uint16_t          horizontal_back_porch;    
  uint16_t          horizontal_front_porch;   
  uint16_t          video_mode_delay;         
} ra8_mipi_dsi_video_cfg_t;

typedef struct {
  ra8_mipi_dsi_dt_t  cmd_id;          
  ra8_mipi_dsi_vc_t  virtual_channel; 
  ra8_mipi_dsi_bta_t bta;             
  bool               low_power;       
  bool               ack_request;     
  bool               aux_operation;   
  uint8_t            action_code;     
  uint16_t           tx_len;          
  const uint8_t*     p_tx_buffer;     
  uint8_t*           p_rx_buffer;     
} ra8_mipi_dsi_command_t;

typedef struct {
  uint8_t           data[2];              
  ra8_mipi_dsi_dt_t cmd_id;               
  ra8_mipi_dsi_vc_t virtual_channel;      
  bool              long_packet;          
  bool              rx_success;           
  bool              rx_fatal_error;       
  bool              rx_fail;              
  bool              rx_packet_data_fail;  
  bool              rx_correctable_error; 
  bool              rx_ack_and_error;     
  bool              info_overwritten;     
} ra8_mipi_dsi_rx_result_t;

typedef struct {
  bool sequence_ch0_running; 
  bool sequence_ch1_running; 
  bool video_running;        
  bool hs_busy;              
  bool lp_busy;              
} ra8_mipi_dsi_link_status_t;

typedef struct {
  uint16_t          error_report;    
  ra8_mipi_dsi_vc_t virtual_channel; 
} ra8_mipi_dsi_ack_error_t;

typedef struct {
  ra8_mipi_dsi_lane_count_t lane_count;             
  ra8_mipi_dsi_clock_mode_t clock_mode;             
  uint16_t                  max_return_packet_size; 
  uint8_t                   ulps_wakeup_period;     
  bool                      ecc_check_enable;       
  bool                      eotp_enable;            
  bool                      scramble_enable;        
  bool                      tearing_detect_enable;  
  uint8_t                   crc_check_vc_mask;      
  ra8_mipi_dsi_timing_t     timing;                 
  ra8_mipi_dsi_timeouts_t   timeouts;               
} ra8_mipi_dsi_config_t;

typedef void (*ra8_mipi_dsi_event_fn_t)(void*                ctx,
                                        ra8_mipi_dsi_event_t event,
                                        uint32_t             status_mask);