ra8_mipi_dsi_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_mipi_dsi_base_addr_s  = 0x40346000UL, 
  k_ra8_mipi_dsi_base_addr_ns = 0x50346000UL, 
} ra8_mipi_dsi_addr_t;

typedef enum : uint16_t {
  k_ra8_mipi_dsi_window_bytes = 0x880U, 
  k_ra8_mipi_dsi_max_lanes    = 2U,     
  k_ra8_mipi_dsi_payload_max  = 16U,    
  k_ra8_mipi_dsi_rx_slots     = 4U,     
  k_ra8_mipi_dsi_descriptors  = 8U,     
  k_ra8_mipi_dsi_max_lp_bytes = 128U,   
  k_ra8_mipi_dsi_max_hs_bytes = 1024U,  
} ra8_mipi_dsi_size_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_busy_loop_max = 100000UL, 
} ra8_mipi_dsi_busy_loop_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rxrinfoow_sl0 = 1UL << 0, 
  k_ra8_mipi_dsi_rxrinfoow_sl1 = 1UL << 1, 
  k_ra8_mipi_dsi_rxrinfoow_sl2 = 1UL << 2, 
  k_ra8_mipi_dsi_rxrinfoow_sl3 = 1UL << 3, 
} ra8_mipi_dsi_rxrinfoowscr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_isr_sq0  = 1UL << 0,  
  k_ra8_mipi_dsi_isr_sq1  = 1UL << 4,  
  k_ra8_mipi_dsi_isr_vm   = 1UL << 8,  
  k_ra8_mipi_dsi_isr_rcv  = 1UL << 12, 
  k_ra8_mipi_dsi_isr_ferr = 1UL << 16, 
  k_ra8_mipi_dsi_isr_ppi  = 1UL << 20, 
} ra8_mipi_dsi_isr_mask_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_link_sq0run = 1UL << 0,  
  k_ra8_mipi_dsi_link_sq1run = 1UL << 4,  
  k_ra8_mipi_dsi_link_vrun   = 1UL << 8,  
  k_ra8_mipi_dsi_link_hsbusy = 1UL << 12, 
  k_ra8_mipi_dsi_link_lpbusy = 1UL << 13, 
} ra8_mipi_dsi_linksr_mask_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_txset_lane1 = 0UL << 0, 
  k_ra8_mipi_dsi_txset_lane2 = 1UL << 0, 
  k_ra8_mipi_dsi_txset_clen  = 1UL << 8, 
  k_ra8_mipi_dsi_txset_dlen  = 1UL << 9, 
} ra8_mipi_dsi_txset_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_hsclk_start      = 1UL << 0, 
  k_ra8_mipi_dsi_hsclk_continuous = 1UL << 1, 
} ra8_mipi_dsi_hsclk_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_ulpscr_clent  = 1UL << 24, 
  k_ra8_mipi_dsi_ulpscr_clexit = 1UL << 25, 
  k_ra8_mipi_dsi_ulpscr_dlent  = 1UL << 28, 
  k_ra8_mipi_dsi_ulpscr_dlexit = 1UL << 29, 
} ra8_mipi_dsi_ulpscr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rstcr_swrst  = 1UL << 0,  
  k_ra8_mipi_dsi_rstcr_ftxstp = 1UL << 16, 
} ra8_mipi_dsi_rstcr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rstsr_rsths     = 1UL << 0,  
  k_ra8_mipi_dsi_rstsr_rstlp     = 1UL << 1,  
  k_ra8_mipi_dsi_rstsr_rstapb    = 1UL << 2,  
  k_ra8_mipi_dsi_rstsr_rstaxi    = 1UL << 3,  
  k_ra8_mipi_dsi_rstsr_rstv      = 1UL << 4,  
  k_ra8_mipi_dsi_rstsr_dl0stp    = 1UL << 8,  
  k_ra8_mipi_dsi_rstsr_dl1stp    = 1UL << 9,  
  k_ra8_mipi_dsi_rstsr_dl0dir    = 1UL << 15, 
  k_ra8_mipi_dsi_rstsr_all_reset = (1UL << 0) | (1UL << 1) | (1UL << 2) | (1UL << 3) | (1UL << 4),
} ra8_mipi_dsi_rstsr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_dsisetr_eccen       = 1UL << 16, 
  k_ra8_mipi_dsi_dsisetr_vc0crcen    = 1UL << 20, 
  k_ra8_mipi_dsi_dsisetr_vc1crcen    = 1UL << 21, 
  k_ra8_mipi_dsi_dsisetr_vc2crcen    = 1UL << 22, 
  k_ra8_mipi_dsi_dsisetr_vc3crcen    = 1UL << 23, 
  k_ra8_mipi_dsi_dsisetr_scren       = 1UL << 29, 
  k_ra8_mipi_dsi_dsisetr_extemd      = 1UL << 30, 
  k_ra8_mipi_dsi_dsisetr_eotpen      = 1UL << 31, 
  k_ra8_mipi_dsi_dsisetr_mrpsz_mask  = 0xFFFFUL,  
  k_ra8_mipi_dsi_dsisetr_vc_crc_mask = (1UL << 20) | (1UL << 21) | (1UL << 22) | (1UL << 23),
} ra8_mipi_dsi_dsisetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rxsr_btarend  = 1UL << 0,  
  k_ra8_mipi_dsi_rxsr_lrxhto   = 1UL << 1,  
  k_ra8_mipi_dsi_rxsr_tato     = 1UL << 2,  
  k_ra8_mipi_dsi_rxsr_rxresp   = 1UL << 8,  
  k_ra8_mipi_dsi_rxsr_rxeotp   = 1UL << 10, 
  k_ra8_mipi_dsi_rxsr_rxte     = 1UL << 13, 
  k_ra8_mipi_dsi_rxsr_rxack    = 1UL << 14, 
  k_ra8_mipi_dsi_rxsr_extedet  = 1UL << 15, 
  k_ra8_mipi_dsi_rxsr_mlferr   = 1UL << 16, 
  k_ra8_mipi_dsi_rxsr_eccerrm  = 1UL << 17, 
  k_ra8_mipi_dsi_rxsr_unexerr  = 1UL << 18, 
  k_ra8_mipi_dsi_rxsr_wcerr    = 1UL << 20, 
  k_ra8_mipi_dsi_rxsr_crcerr   = 1UL << 21, 
  k_ra8_mipi_dsi_rxsr_iberr    = 1UL << 22, 
  k_ra8_mipi_dsi_rxsr_rxovferr = 1UL << 23, 
  k_ra8_mipi_dsi_rxsr_prtoerr  = 1UL << 24, 
  k_ra8_mipi_dsi_rxsr_noreserr = 1UL << 25, 
  k_ra8_mipi_dsi_rxsr_rsizeerr = 1UL << 26, 
  k_ra8_mipi_dsi_rxsr_eccerrs  = 1UL << 28, 
  k_ra8_mipi_dsi_rxsr_rxake    = 1UL << 30, 
  k_ra8_mipi_dsi_rxsr_clear_all =
    (1UL << 0) | (1UL << 1) | (1UL << 2) | (1UL << 8) | (1UL << 10) | (1UL << 13) | (1UL << 14) |
    (1UL << 15) | (1UL << 16) | (1UL << 17) | (1UL << 18) | (1UL << 20) | (1UL << 21) |
    (1UL << 22) | (1UL << 23) | (1UL << 24) | (1UL << 25) | (1UL << 26) | (1UL << 28) | (1UL << 30),
} ra8_mipi_dsi_rxsr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rxrssr_slt0vld = 1UL << 0, 
  k_ra8_mipi_dsi_rxrssr_slt1vld = 1UL << 1, 
  k_ra8_mipi_dsi_rxrssr_slt2vld = 1UL << 2, 
  k_ra8_mipi_dsi_rxrssr_slt3vld = 1UL << 3, 
} ra8_mipi_dsi_rxrssr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_rxrss_data0_mask = 0x000000FFUL, 
  k_ra8_mipi_dsi_rxrss_data1_mask = 0x0000FF00UL, 
  k_ra8_mipi_dsi_rxrss_dt_mask    = 0x003F0000UL, 
  k_ra8_mipi_dsi_rxrss_vc_mask    = 0x00C00000UL, 
  k_ra8_mipi_dsi_rxrss_fmt        = 1UL << 24,    
  k_ra8_mipi_dsi_rxrss_rxsuc      = 1UL << 25,    
  k_ra8_mipi_dsi_rxrss_rxferr     = 1UL << 26,    
  k_ra8_mipi_dsi_rxrss_rxfail     = 1UL << 27,    
  k_ra8_mipi_dsi_rxrss_rxpfail    = 1UL << 28,    
  k_ra8_mipi_dsi_rxrss_rxcerr     = 1UL << 29,    
  k_ra8_mipi_dsi_rxrss_rxake      = 1UL << 30,    
  k_ra8_mipi_dsi_rxrss_infoow     = 1UL << 31,    
} ra8_mipi_dsi_rxrss_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_akep_erep_mask = 0xFFFFUL,    
  k_ra8_mipi_dsi_akep_vc_mask   = 0xFUL << 16, 
} ra8_mipi_dsi_akep_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_ferrsr_htxto     = 1UL << 0,  
  k_ra8_mipi_dsi_ferrsr_lrxhto    = 1UL << 1,  
  k_ra8_mipi_dsi_ferrsr_tato      = 1UL << 2,  
  k_ra8_mipi_dsi_ferrsr_escent    = 1UL << 16, 
  k_ra8_mipi_dsi_ferrsr_syncesc   = 1UL << 17, 
  k_ra8_mipi_dsi_ferrsr_ctrl      = 1UL << 18, 
  k_ra8_mipi_dsi_ferrsr_clp0      = 1UL << 19, 
  k_ra8_mipi_dsi_ferrsr_clp1      = 1UL << 20, 
  k_ra8_mipi_dsi_ferrsr_clp0s     = 1UL << 27, 
  k_ra8_mipi_dsi_ferrsr_clp1s     = 1UL << 28, 
  k_ra8_mipi_dsi_ferrsr_clear_all = (1UL << 0) | (1UL << 1) | (1UL << 2) | (1UL << 16) |
                                    (1UL << 17) | (1UL << 18) | (1UL << 19) | (1UL << 20),
} ra8_mipi_dsi_ferrsr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_plsr_cluan     = 1UL << 0,  
  k_ra8_mipi_dsi_plsr_clstp     = 1UL << 1,  
  k_ra8_mipi_dsi_plsr_dl0rle    = 1UL << 2,  
  k_ra8_mipi_dsi_plsr_dl0rue    = 1UL << 3,  
  k_ra8_mipi_dsi_plsr_dl0uan    = 1UL << 4,  
  k_ra8_mipi_dsi_plsr_dl1uan    = 1UL << 5,  
  k_ra8_mipi_dsi_plsr_dl0stp    = 1UL << 8,  
  k_ra8_mipi_dsi_plsr_dl1stp    = 1UL << 9,  
  k_ra8_mipi_dsi_plsr_dl0rx2tx  = 1UL << 12, 
  k_ra8_mipi_dsi_plsr_dl0tx2rx  = 1UL << 13, 
  k_ra8_mipi_dsi_plsr_dl0dir    = 1UL << 15, 
  k_ra8_mipi_dsi_plsr_clulpent  = 1UL << 24, 
  k_ra8_mipi_dsi_plsr_clulpext  = 1UL << 25, 
  k_ra8_mipi_dsi_plsr_cllp2hs   = 1UL << 26, 
  k_ra8_mipi_dsi_plsr_clhs2lp   = 1UL << 27, 
  k_ra8_mipi_dsi_plsr_dlulpent  = 1UL << 28, 
  k_ra8_mipi_dsi_plsr_dlulpext  = 1UL << 29, 
  k_ra8_mipi_dsi_plsr_clear_all = (1UL << 12) | (1UL << 13) | (1UL << 24) | (1UL << 25) |
                                  (1UL << 26) | (1UL << 27) | (1UL << 28) | (1UL << 29),
} ra8_mipi_dsi_plsr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmset0_vstart  = 1UL << 0,  
  k_ra8_mipi_dsi_vmset0_vstop   = 1UL << 1,  
  k_ra8_mipi_dsi_vmset0_hsanolp = 1UL << 8,  
  k_ra8_mipi_dsi_vmset0_hbpnolp = 1UL << 9,  
  k_ra8_mipi_dsi_vmset0_hfpnolp = 1UL << 10, 
} ra8_mipi_dsi_vmset0_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmset1_dly_shift = 2U,       
  k_ra8_mipi_dsi_vmset1_dly_mask  = 0x3FFCUL, 
} ra8_mipi_dsi_vmset1_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmsr_running = 1UL << 0,  
  k_ra8_mipi_dsi_vmsr_virdy   = 1UL << 4,  
  k_ra8_mipi_dsi_vmsr_stop    = 1UL << 8,  
  k_ra8_mipi_dsi_vmsr_timerr  = 1UL << 20, 
  k_ra8_mipi_dsi_vmsr_vbufudf = 1UL << 22, 
  k_ra8_mipi_dsi_vmsr_vbufovf = 1UL << 23, 
  k_ra8_mipi_dsi_vmsr_clear_all =
    (1UL << 0) | (1UL << 4) | (1UL << 8) | (1UL << 20) | (1UL << 22) | (1UL << 23),
} ra8_mipi_dsi_vmsr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmpp_txesync  = 1UL << 15, 
  k_ra8_mipi_dsi_vmpp_dt_shift = 16U,       
  k_ra8_mipi_dsi_vmpp_dt_mask  = 0x3FUL << 16,
  k_ra8_mipi_dsi_vmpp_vc_shift = 22U, 
  k_ra8_mipi_dsi_vmpp_vc_mask  = 0x3UL << 22,
} ra8_mipi_dsi_vmppsetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmvs_vsa_mask   = 0x00000FFFUL,   
  k_ra8_mipi_dsi_vmvs_vspol      = 1UL << 15,      
  k_ra8_mipi_dsi_vmvs_vact_shift = 16U,            
  k_ra8_mipi_dsi_vmvs_vact_mask  = 0x7FFFUL << 16, 
} ra8_mipi_dsi_vmvssetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmvp_vbp_mask  = 0x00001FFFUL,   
  k_ra8_mipi_dsi_vmvp_vfp_shift = 16U,            
  k_ra8_mipi_dsi_vmvp_vfp_mask  = 0x1FFFUL << 16, 
} ra8_mipi_dsi_vmvpsetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmhs_hsa_mask   = 0x00000FFFUL,   
  k_ra8_mipi_dsi_vmhs_hspol      = 1UL << 15,      
  k_ra8_mipi_dsi_vmhs_hact_shift = 16U,            
  k_ra8_mipi_dsi_vmhs_hact_mask  = 0x7FFFUL << 16, 
} ra8_mipi_dsi_vmhssetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_vmhp_hbp_mask  = 0x00001FFFUL,   
  k_ra8_mipi_dsi_vmhp_hfp_shift = 16U,            
  k_ra8_mipi_dsi_vmhp_hfp_mask  = 0x1FFFUL << 16, 
} ra8_mipi_dsi_vmhpsetr_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_clstpt_clkstpt_shift = 2U,      
  k_ra8_mipi_dsi_clstpt_clkstpt_mask  = 0xFFCUL, 
  k_ra8_mipi_dsi_clstpt_clkbfht_shift = 16U,     
  k_ra8_mipi_dsi_clstpt_clkbfht_mask  = 0xFFUL << 16,
  k_ra8_mipi_dsi_clstpt_clkkpt_shift = 24U, 
  k_ra8_mipi_dsi_clstpt_clkkpt_mask  = 0xFFUL << 24,
} ra8_mipi_dsi_clstpt_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_lptrnst_golpbkt_mask = 0x3FFUL, 
} ra8_mipi_dsi_lptrnst_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_presptolp_lpwto_mask  = 0xFFFFUL, 
  k_ra8_mipi_dsi_presptolp_lprto_shift = 16U,      
  k_ra8_mipi_dsi_presptolp_lprto_mask  = 0xFFFFUL << 16,
} ra8_mipi_dsi_presptolp_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_presptohs_hswto_mask  = 0xFFFFUL, 
  k_ra8_mipi_dsi_presptohs_hsrto_shift = 16U,      
  k_ra8_mipi_dsi_presptohs_hsrto_mask  = 0xFFFFUL << 16,
} ra8_mipi_dsi_presptohs_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_sqch_start     = 1UL << 0,  
  k_ra8_mipi_dsi_sqch_chsel     = 1UL << 23, 
  k_ra8_mipi_dsi_sqch_running   = 1UL << 2,  
  k_ra8_mipi_dsi_sqch_aactfin   = 1UL << 4,  
  k_ra8_mipi_dsi_sqch_adesfin   = 1UL << 8,  
  k_ra8_mipi_dsi_sqch_dabort    = 1UL << 16, 
  k_ra8_mipi_dsi_sqch_sizeerr   = 1UL << 19, 
  k_ra8_mipi_dsi_sqch_txiberr   = 1UL << 24, 
  k_ra8_mipi_dsi_sqch_rxferr    = 1UL << 26, 
  k_ra8_mipi_dsi_sqch_rxfail    = 1UL << 27, 
  k_ra8_mipi_dsi_sqch_rxpfail   = 1UL << 28, 
  k_ra8_mipi_dsi_sqch_rxcorerr  = 1UL << 29, 
  k_ra8_mipi_dsi_sqch_rxake     = 1UL << 30, 
  k_ra8_mipi_dsi_sqch_clear_all = (1UL << 4) | (1UL << 8) | (1UL << 16) | (1UL << 19) |
                                  (1UL << 24) | (1UL << 26) | (1UL << 27) | (1UL << 28) |
                                  (1UL << 29) | (1UL << 30),
} ra8_mipi_dsi_sqch_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_dsc0a_shift_data0 = 0U,  
  k_ra8_mipi_dsi_dsc0a_shift_data1 = 8U,  
  k_ra8_mipi_dsi_dsc0a_shift_dt    = 16U, 
  k_ra8_mipi_dsi_dsc0a_shift_vc    = 22U, 
  k_ra8_mipi_dsi_dsc0a_shift_fmt   = 24U, 
  k_ra8_mipi_dsi_dsc0a_shift_spd   = 25U, 
  k_ra8_mipi_dsi_dsc0a_shift_bta   = 26U, 
  k_ra8_mipi_dsi_dsc0a_shift_nxact = 28U, 
} ra8_mipi_dsi_dsc0a_shift_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_dsc0b_dtsel_txppd = 0UL << 24, 
  k_ra8_mipi_dsi_dsc0b_dtsel_seqrm = 1UL << 24, 
} ra8_mipi_dsi_dsc0b_t;

typedef enum : uint32_t {
  k_ra8_mipi_dsi_dsc0c_finact        = 1UL << 0,     
  k_ra8_mipi_dsi_dsc0c_auxop         = 1UL << 22,    
  k_ra8_mipi_dsi_dsc0c_actcode_shift = 24U,          
  k_ra8_mipi_dsi_dsc0c_actcode_mask  = 0xFFUL << 24, 
} ra8_mipi_dsi_dsc0c_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_bta_none     = 0U, 
  k_ra8_mipi_dsi_bta_after    = 1U, 
  k_ra8_mipi_dsi_bta_read     = 2U, 
  k_ra8_mipi_dsi_bta_no_write = 3U, 
} ra8_mipi_dsi_bta_t;

typedef struct {
  volatile uint32_t A; 
  volatile uint32_t B; 
  volatile uint32_t C; 
  volatile uint32_t D; 
} r_mipi_dsi_descriptor_t;

typedef enum : uint8_t {
  k_ra8_mipi_dsi_rsv_words_isr_to_linksr    = 3U,  
  k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr = 59U, 
  k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd = 15U, 
  k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr    = 36U, 
  k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd   = 28U, 
  k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto  = 4U,  
  k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr   = 5U,  
  k_ra8_mipi_dsi_rsv_words_plier_to_vmset   = 53U, 
  k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0 = 98U, 
  k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr = 3U,  
  k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1 = 9U,  
  k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc = 89U, 
} ra8_mipi_dsi_reserved_words_t;

typedef enum : uint16_t {
  k_ra8_mipi_dsi_offset_akeplatir = 0x220U, 
  k_ra8_mipi_dsi_offset_vmppsetr  = 0x420U, 
  k_ra8_mipi_dsi_offset_sqch0dsc  = 0x780U, 
  k_ra8_mipi_dsi_offset_sqch1dsc  = 0x800U, 
} ra8_mipi_dsi_offset_t;

typedef struct {
  volatile uint32_t ISR;                                         
  volatile uint32_t _r0[k_ra8_mipi_dsi_rsv_words_isr_to_linksr]; 
  volatile uint32_t LINKSR;                                      
  volatile uint32_t
    _r1[k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr]; 
  volatile uint32_t TXSETR;                         
  volatile uint32_t HSCLKSETR;                      
  volatile uint32_t ULPSSETR;                       
  volatile uint32_t ULPSCR;                         
  volatile uint32_t RSTCR;                          
  volatile uint32_t RSTSR;                          
  volatile uint32_t _r2[2];                         
  volatile uint32_t DSISETR;                        
  volatile uint32_t
    _r3[k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd]; 
  volatile uint32_t TXPPD0R;                        
  volatile uint32_t TXPPD1R;                        
  volatile uint32_t TXPPD2R;                        
  volatile uint32_t TXPPD3R;                        
  volatile uint32_t
    _r4[k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr]; 
  volatile uint32_t RXSR;                        
  volatile uint32_t RXSCR;                       
  volatile uint32_t RXIER;                       
  volatile uint32_t _r5;                         
  volatile uint32_t PRESPTOBTASETR;              
  volatile uint32_t PRESPTOLPSETR;               
  volatile uint32_t PRESPTOHSSETR;               
  volatile uint32_t _r6;                         
  volatile uint32_t AKEPLATIR;                   
  volatile uint32_t AKEPACMSR;                   
  volatile uint32_t AKEPSCR;                     
  volatile uint32_t _r7;                         
  volatile uint32_t RXRSSR;                      
  volatile uint32_t RXRSSCR;                     
  volatile uint32_t RXRINFOOWSR;                 
  volatile uint32_t RXRINFOOWSCR;                
  volatile uint32_t RXRSS0R;                     
  volatile uint32_t RXRSS1R;                     
  volatile uint32_t RXRSS2R;                     
  volatile uint32_t RXRSS3R;                     
  volatile uint32_t
    _r8[k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd]; 
  volatile uint32_t RXPPD0R;                      
  volatile uint32_t RXPPD1R;                      
  volatile uint32_t RXPPD2R;                      
  volatile uint32_t RXPPD3R;                      
  volatile uint32_t
    _r9[k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto]; 
  volatile uint32_t HSTXTOSETR;                    
  volatile uint32_t LRXHTOSETR;                    
  volatile uint32_t TATOSETR;                      
  volatile uint32_t
    _r10[k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr]; 
  volatile uint32_t FERRSR;                        
  volatile uint32_t FERRSCR;                       
  volatile uint32_t FERRIER;                       
  volatile uint32_t _r11[2];                       
  volatile uint32_t CLSTPTSETR;                    
  volatile uint32_t LPTRNSTSETR;                   
  volatile uint32_t _r12;                          
  volatile uint32_t PLSR;                          
  volatile uint32_t PLSCR;                         
  volatile uint32_t PLIER;                         
  volatile uint32_t
    _r13[k_ra8_mipi_dsi_rsv_words_plier_to_vmset]; 
  volatile uint32_t VMSET0R;                       
  volatile uint32_t VMSET1R;                       
  volatile uint32_t _r14[2];                       
  volatile uint32_t VMSR;                          
  volatile uint32_t VMSCR;                         
  volatile uint32_t VMIER;                         
  volatile uint32_t _r15;                          
  volatile uint32_t VMPPSETR;                      
  volatile uint32_t _r16;                          
  volatile uint32_t VMVSSETR;                      
  volatile uint32_t VMVPSETR;                      
  volatile uint32_t VMHSSETR;                      
  volatile uint32_t VMHPSETR;                      
  volatile uint32_t
    _r17[k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0]; 
  volatile uint32_t SQCH0SET0R;                      
  volatile uint32_t
    _r18[k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]; 
  volatile uint32_t SQCH0SR;                         
  volatile uint32_t SQCH0SCR;                        
  volatile uint32_t SQCH0IER;                        
  volatile uint32_t
    _r19[k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1]; 
  volatile uint32_t SQCH1SET0R;                      
  volatile uint32_t
    _r20[k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]; 
  volatile uint32_t SQCH1SR;                         
  volatile uint32_t SQCH1SCR;                        
  volatile uint32_t SQCH1IER;                        
  volatile uint32_t
    _r21[k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc]; 
  r_mipi_dsi_descriptor_t SQCH0DSC[8];               
  r_mipi_dsi_descriptor_t SQCH1DSC[8];               
} r_mipi_dsi_regs_t;
 
static_assert(sizeof(r_mipi_dsi_descriptor_t) == 16U,
              "r_mipi_dsi_descriptor_t must be 4 x uint32 = 16 bytes");
static_assert(sizeof(r_mipi_dsi_regs_t) == (size_t)k_ra8_mipi_dsi_window_bytes,
              "r_mipi_dsi_regs_t size must match HUM Ch 65 register window");
static_assert(offsetof(r_mipi_dsi_regs_t, SQCH0DSC) == (size_t)k_ra8_mipi_dsi_offset_sqch0dsc,
              "SQCH0DSC must land at offset 0x780");
static_assert(offsetof(r_mipi_dsi_regs_t, SQCH1DSC) == (size_t)k_ra8_mipi_dsi_offset_sqch1dsc,
              "SQCH1DSC must land at offset 0x800");
static_assert(offsetof(r_mipi_dsi_regs_t, VMPPSETR) == (size_t)k_ra8_mipi_dsi_offset_vmppsetr,
              "VMPPSETR must land at offset 0x420");
static_assert(offsetof(r_mipi_dsi_regs_t, AKEPLATIR) == (size_t)k_ra8_mipi_dsi_offset_akeplatir,
              "AKEPLATIR must land at offset 0x220");

RA8_HW_REGISTER_ACCESS
static inline volatile r_mipi_dsi_regs_t* ra8_mipi_dsi(void)
{
  return (volatile r_mipi_dsi_regs_t*)k_ra8_mipi_dsi_base_addr_s;
}
 
#ifdef __cplusplus
}
#endif