ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_mipi_dsi_regs_t Struct Reference

MIPI DSI host register block (full layout). More...

#include <ra8_mipi_dsi_regs.h>

Collaboration diagram for r_mipi_dsi_regs_t:

Data Fields

volatile uint32_t ISR
 +0x000 IRQ status (RO).
volatile uint32_t _r0 [k_ra8_mipi_dsi_rsv_words_isr_to_linksr]
 +0x004..0x00C reserved.
volatile uint32_t LINKSR
 +0x010 Link status (RO).
volatile uint32_t _r1 [k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr]
 +0x014..0x0FC reserved.
volatile uint32_t TXSETR
 +0x100 Lane enable + count.
volatile uint32_t HSCLKSETR
 +0x104 HS clock control.
volatile uint32_t ULPSSETR
 +0x108 ULPS wakeup period.
volatile uint32_t ULPSCR
 +0x10C ULPS enter/exit pulses.
volatile uint32_t RSTCR
 +0x110 Software reset control.
volatile uint32_t RSTSR
 +0x114 Software reset status (RO).
volatile uint32_t _r2 [2]
 +0x118..0x11C reserved.
volatile uint32_t DSISETR
 +0x120 DSI link configuration.
volatile uint32_t _r3 [k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd]
 +0x124..0x15C reserved.
volatile uint32_t TXPPD0R
 +0x160 Tx packet payload data 0.
volatile uint32_t TXPPD1R
 +0x164 Tx packet payload data 1.
volatile uint32_t TXPPD2R
 +0x168 Tx packet payload data 2.
volatile uint32_t TXPPD3R
 +0x16C Tx packet payload data 3.
volatile uint32_t _r4 [k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr]
 +0x170..0x1FC reserved.
volatile uint32_t RXSR
 +0x200 Receive status (RO).
volatile uint32_t RXSCR
 +0x204 Receive status clear.
volatile uint32_t RXIER
 +0x208 Receive interrupt enable.
volatile uint32_t _r5
 +0x20C reserved.
volatile uint32_t PRESPTOBTASETR
 +0x210 Peripheral resp TO (BTA).
volatile uint32_t PRESPTOLPSETR
 +0x214 Peripheral resp TO (LP).
volatile uint32_t PRESPTOHSSETR
 +0x218 Peripheral resp TO (HS).
volatile uint32_t _r6
 +0x21C reserved.
volatile uint32_t AKEPLATIR
 +0x220 Ack/err report latest (RO).
volatile uint32_t AKEPACMSR
 +0x224 Ack/err accumulated (RO).
volatile uint32_t AKEPSCR
 +0x228 Ack/err clear.
volatile uint32_t _r7
 +0x22C reserved.
volatile uint32_t RXRSSR
 +0x230 Rx result save status.
volatile uint32_t RXRSSCR
 +0x234 Rx result save clear.
volatile uint32_t RXRINFOOWSR
 +0x238 Rx info-overwrite status.
volatile uint32_t RXRINFOOWSCR
 +0x23C Rx info-overwrite clear.
volatile uint32_t RXRSS0R
 +0x240 Rx result save slot 0.
volatile uint32_t RXRSS1R
 +0x244 Rx result save slot 1.
volatile uint32_t RXRSS2R
 +0x248 Rx result save slot 2.
volatile uint32_t RXRSS3R
 +0x24C Rx result save slot 3.
volatile uint32_t _r8 [k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd]
 +0x250..0x2BC reserved.
volatile uint32_t RXPPD0R
 +0x2C0 Rx packet payload data 0.
volatile uint32_t RXPPD1R
 +0x2C4 Rx packet payload data 1.
volatile uint32_t RXPPD2R
 +0x2C8 Rx packet payload data 2.
volatile uint32_t RXPPD3R
 +0x2CC Rx packet payload data 3.
volatile uint32_t _r9 [k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto]
 +0x2D0..0x2DC reserved.
volatile uint32_t HSTXTOSETR
 +0x2E0 HS Tx timeout count.
volatile uint32_t LRXHTOSETR
 +0x2E4 LP-RX host timeout.
volatile uint32_t TATOSETR
 +0x2E8 Turnaround ack timeout.
volatile uint32_t _r10 [k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr]
 +0x2EC..0x2FC reserved.
volatile uint32_t FERRSR
 +0x300 Fatal-error status (RO).
volatile uint32_t FERRSCR
 +0x304 Fatal-error status clear.
volatile uint32_t FERRIER
 +0x308 Fatal-error int enable.
volatile uint32_t _r11 [2]
 +0x30C..0x310 reserved.
volatile uint32_t CLSTPTSETR
 +0x314 Clock-lane stop time.
volatile uint32_t LPTRNSTSETR
 +0x318 LP transition time.
volatile uint32_t _r12
 +0x31C reserved.
volatile uint32_t PLSR
 +0x320 PHY (PPI) status (RO).
volatile uint32_t PLSCR
 +0x324 PHY status clear.
volatile uint32_t PLIER
 +0x328 PHY interrupt enable.
volatile uint32_t _r13 [k_ra8_mipi_dsi_rsv_words_plier_to_vmset]
 +0x32C..0x3FC reserved.
volatile uint32_t VMSET0R
 +0x400 Video-mode set 0.
volatile uint32_t VMSET1R
 +0x404 Video-mode set 1.
volatile uint32_t _r14 [2]
 +0x408..0x40C reserved.
volatile uint32_t VMSR
 +0x410 Video-mode status (RO).
volatile uint32_t VMSCR
 +0x414 Video-mode status clear.
volatile uint32_t VMIER
 +0x418 Video-mode int enable.
volatile uint32_t _r15
 +0x41C reserved.
volatile uint32_t VMPPSETR
 +0x420 Video pixel-packet set.
volatile uint32_t _r16
 +0x424 reserved.
volatile uint32_t VMVSSETR
 +0x428 Vertical sync timing.
volatile uint32_t VMVPSETR
 +0x42C Vertical porch timing.
volatile uint32_t VMHSSETR
 +0x430 Horizontal sync timing.
volatile uint32_t VMHPSETR
 +0x434 Horizontal porch timing.
volatile uint32_t _r17 [k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0]
 +0x438..0x5BC reserved.
volatile uint32_t SQCH0SET0R
 +0x5C0 Sequence ch 0 START bit.
volatile uint32_t _r18 [k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]
 +0x5C4..0x5CC reserved.
volatile uint32_t SQCH0SR
 +0x5D0 Sequence ch 0 status (RO).
volatile uint32_t SQCH0SCR
 +0x5D4 Sequence ch 0 clear.
volatile uint32_t SQCH0IER
 +0x5D8 Sequence ch 0 int enable.
volatile uint32_t _r19 [k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1]
 +0x5DC..0x5FC reserved.
volatile uint32_t SQCH1SET0R
 +0x600 Sequence ch 1 START bit.
volatile uint32_t _r20 [k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]
 +0x604..0x60C reserved.
volatile uint32_t SQCH1SR
 +0x610 Sequence ch 1 status (RO).
volatile uint32_t SQCH1SCR
 +0x614 Sequence ch 1 clear.
volatile uint32_t SQCH1IER
 +0x618 Sequence ch 1 int enable.
volatile uint32_t _r21 [k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc]
 +0x61C..0x77C reserved.
r_mipi_dsi_descriptor_t SQCH0DSC [8]
 +0x780..0x7FC ch0 desc 0..7.
r_mipi_dsi_descriptor_t SQCH1DSC [8]
 +0x800..0x87C ch1 desc 0..7.

Detailed Description

MIPI DSI host register block (full layout).

Every documented register in HUM Ch 65 has a named field. The intervening reserved arrays hold the exact byte count to keep the named offsets aligned with the FSP R_MIPI_DSI_Type layout. Total struct size matches the FSP Size = 2176 (0x880) declaration so a static_assert below catches any accidental drift.

Invariant
sizeof(r_mipi_dsi_regs_t) == k_ra8_mipi_dsi_window_bytes

Definition at line 778 of file ra8_mipi_dsi_regs.h.

Field Documentation

◆ _r0

volatile uint32_t r_mipi_dsi_regs_t::_r0[k_ra8_mipi_dsi_rsv_words_isr_to_linksr]

+0x004..0x00C reserved.

Definition at line 780 of file ra8_mipi_dsi_regs.h.

◆ _r1

volatile uint32_t r_mipi_dsi_regs_t::_r1[k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr]

+0x014..0x0FC reserved.

Definition at line 783 of file ra8_mipi_dsi_regs.h.

◆ _r10

volatile uint32_t r_mipi_dsi_regs_t::_r10[k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr]

+0x2EC..0x2FC reserved.

Definition at line 832 of file ra8_mipi_dsi_regs.h.

◆ _r11

volatile uint32_t r_mipi_dsi_regs_t::_r11[2]

+0x30C..0x310 reserved.

Definition at line 836 of file ra8_mipi_dsi_regs.h.

◆ _r12

volatile uint32_t r_mipi_dsi_regs_t::_r12

+0x31C reserved.

Definition at line 839 of file ra8_mipi_dsi_regs.h.

◆ _r13

volatile uint32_t r_mipi_dsi_regs_t::_r13[k_ra8_mipi_dsi_rsv_words_plier_to_vmset]

+0x32C..0x3FC reserved.

Definition at line 844 of file ra8_mipi_dsi_regs.h.

◆ _r14

volatile uint32_t r_mipi_dsi_regs_t::_r14[2]

+0x408..0x40C reserved.

Definition at line 847 of file ra8_mipi_dsi_regs.h.

◆ _r15

volatile uint32_t r_mipi_dsi_regs_t::_r15

+0x41C reserved.

Definition at line 851 of file ra8_mipi_dsi_regs.h.

◆ _r16

volatile uint32_t r_mipi_dsi_regs_t::_r16

+0x424 reserved.

Definition at line 853 of file ra8_mipi_dsi_regs.h.

◆ _r17

volatile uint32_t r_mipi_dsi_regs_t::_r17[k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0]

+0x438..0x5BC reserved.

Definition at line 859 of file ra8_mipi_dsi_regs.h.

◆ _r18

volatile uint32_t r_mipi_dsi_regs_t::_r18[k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]

+0x5C4..0x5CC reserved.

Definition at line 862 of file ra8_mipi_dsi_regs.h.

◆ _r19

volatile uint32_t r_mipi_dsi_regs_t::_r19[k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1]

+0x5DC..0x5FC reserved.

Definition at line 867 of file ra8_mipi_dsi_regs.h.

◆ _r2

volatile uint32_t r_mipi_dsi_regs_t::_r2[2]

+0x118..0x11C reserved.

Definition at line 790 of file ra8_mipi_dsi_regs.h.

◆ _r20

volatile uint32_t r_mipi_dsi_regs_t::_r20[k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr]

+0x604..0x60C reserved.

Definition at line 870 of file ra8_mipi_dsi_regs.h.

◆ _r21

volatile uint32_t r_mipi_dsi_regs_t::_r21[k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc]

+0x61C..0x77C reserved.

Definition at line 875 of file ra8_mipi_dsi_regs.h.

◆ _r3

volatile uint32_t r_mipi_dsi_regs_t::_r3[k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd]

+0x124..0x15C reserved.

Definition at line 793 of file ra8_mipi_dsi_regs.h.

◆ _r4

volatile uint32_t r_mipi_dsi_regs_t::_r4[k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr]

+0x170..0x1FC reserved.

Definition at line 799 of file ra8_mipi_dsi_regs.h.

◆ _r5

volatile uint32_t r_mipi_dsi_regs_t::_r5

+0x20C reserved.

Definition at line 803 of file ra8_mipi_dsi_regs.h.

◆ _r6

volatile uint32_t r_mipi_dsi_regs_t::_r6

+0x21C reserved.

Definition at line 807 of file ra8_mipi_dsi_regs.h.

◆ _r7

volatile uint32_t r_mipi_dsi_regs_t::_r7

+0x22C reserved.

Definition at line 811 of file ra8_mipi_dsi_regs.h.

◆ _r8

volatile uint32_t r_mipi_dsi_regs_t::_r8[k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd]

+0x250..0x2BC reserved.

Definition at line 821 of file ra8_mipi_dsi_regs.h.

◆ _r9

volatile uint32_t r_mipi_dsi_regs_t::_r9[k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto]

+0x2D0..0x2DC reserved.

Definition at line 827 of file ra8_mipi_dsi_regs.h.

◆ AKEPACMSR

volatile uint32_t r_mipi_dsi_regs_t::AKEPACMSR

+0x224 Ack/err accumulated (RO).

Definition at line 809 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_ack_error_get().

◆ AKEPLATIR

volatile uint32_t r_mipi_dsi_regs_t::AKEPLATIR

+0x220 Ack/err report latest (RO).

Definition at line 808 of file ra8_mipi_dsi_regs.h.

◆ AKEPSCR

volatile uint32_t r_mipi_dsi_regs_t::AKEPSCR

+0x228 Ack/err clear.

Definition at line 810 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_ack_error_get().

◆ CLSTPTSETR

volatile uint32_t r_mipi_dsi_regs_t::CLSTPTSETR

+0x314 Clock-lane stop time.

Definition at line 837 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link().

◆ DSISETR

volatile uint32_t r_mipi_dsi_regs_t::DSISETR

+0x120 DSI link configuration.

Definition at line 791 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link().

◆ FERRIER

volatile uint32_t r_mipi_dsi_regs_t::FERRIER

+0x308 Fatal-error int enable.

Definition at line 835 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ FERRSCR

volatile uint32_t r_mipi_dsi_regs_t::FERRSCR

+0x304 Fatal-error status clear.

Definition at line 834 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), and ra8_mipi_dsi_dispatch_fatal().

◆ FERRSR

volatile uint32_t r_mipi_dsi_regs_t::FERRSR

+0x300 Fatal-error status (RO).

Definition at line 833 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_fatal().

◆ HSCLKSETR

volatile uint32_t r_mipi_dsi_regs_t::HSCLKSETR

+0x104 HS clock control.

Definition at line 785 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_hs_clock_start(), and ra8_mipi_dsi_hs_clock_stop().

◆ HSTXTOSETR

volatile uint32_t r_mipi_dsi_regs_t::HSTXTOSETR

+0x2E0 HS Tx timeout count.

Definition at line 828 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ ISR

volatile uint32_t r_mipi_dsi_regs_t::ISR

+0x000 IRQ status (RO).

Definition at line 779 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch(), and ra8_mipi_dsi_get_status().

◆ LINKSR

volatile uint32_t r_mipi_dsi_regs_t::LINKSR

+0x010 Link status (RO).

Definition at line 781 of file ra8_mipi_dsi_regs.h.

Referenced by internal_check_link_state(), and ra8_mipi_dsi_link_status_get().

◆ LPTRNSTSETR

volatile uint32_t r_mipi_dsi_regs_t::LPTRNSTSETR

+0x318 LP transition time.

Definition at line 838 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link().

◆ LRXHTOSETR

volatile uint32_t r_mipi_dsi_regs_t::LRXHTOSETR

+0x2E4 LP-RX host timeout.

Definition at line 829 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ PLIER

volatile uint32_t r_mipi_dsi_regs_t::PLIER

+0x328 PHY interrupt enable.

Definition at line 842 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ PLSCR

volatile uint32_t r_mipi_dsi_regs_t::PLSCR

+0x324 PHY status clear.

Definition at line 841 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), and ra8_mipi_dsi_dispatch_phy().

◆ PLSR

volatile uint32_t r_mipi_dsi_regs_t::PLSR

+0x320 PHY (PPI) status (RO).

Definition at line 840 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_phy(), ra8_mipi_dsi_hs_clock_start(), and ra8_mipi_dsi_hs_clock_stop().

◆ PRESPTOBTASETR

volatile uint32_t r_mipi_dsi_regs_t::PRESPTOBTASETR

+0x210 Peripheral resp TO (BTA).

Definition at line 804 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ PRESPTOHSSETR

volatile uint32_t r_mipi_dsi_regs_t::PRESPTOHSSETR

+0x218 Peripheral resp TO (HS).

Definition at line 806 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ PRESPTOLPSETR

volatile uint32_t r_mipi_dsi_regs_t::PRESPTOLPSETR

+0x214 Peripheral resp TO (LP).

Definition at line 805 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ RSTCR

volatile uint32_t r_mipi_dsi_regs_t::RSTCR

+0x110 Software reset control.

Definition at line 788 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link(), ra8_mipi_dsi_deinit(), ra8_mipi_dsi_dispatch_video(), and ra8_mipi_dsi_soft_reset().

◆ RSTSR

volatile uint32_t r_mipi_dsi_regs_t::RSTSR

+0x114 Software reset status (RO).

Definition at line 789 of file ra8_mipi_dsi_regs.h.

◆ RXIER

volatile uint32_t r_mipi_dsi_regs_t::RXIER

+0x208 Receive interrupt enable.

Definition at line 802 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ RXPPD0R

volatile uint32_t r_mipi_dsi_regs_t::RXPPD0R

+0x2C0 Rx packet payload data 0.

Definition at line 822 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_payload_read().

◆ RXPPD1R

volatile uint32_t r_mipi_dsi_regs_t::RXPPD1R

+0x2C4 Rx packet payload data 1.

Definition at line 823 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_payload_read().

◆ RXPPD2R

volatile uint32_t r_mipi_dsi_regs_t::RXPPD2R

+0x2C8 Rx packet payload data 2.

Definition at line 824 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_payload_read().

◆ RXPPD3R

volatile uint32_t r_mipi_dsi_regs_t::RXPPD3R

+0x2CC Rx packet payload data 3.

Definition at line 825 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_payload_read().

◆ RXRINFOOWSCR

volatile uint32_t r_mipi_dsi_regs_t::RXRINFOOWSCR

+0x23C Rx info-overwrite clear.

Definition at line 815 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_receive(), and ra8_mipi_dsi_rx_result_get().

◆ RXRINFOOWSR

volatile uint32_t r_mipi_dsi_regs_t::RXRINFOOWSR

+0x238 Rx info-overwrite status.

Definition at line 814 of file ra8_mipi_dsi_regs.h.

◆ RXRSS0R

volatile uint32_t r_mipi_dsi_regs_t::RXRSS0R

+0x240 Rx result save slot 0.

Definition at line 816 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXRSS1R

volatile uint32_t r_mipi_dsi_regs_t::RXRSS1R

+0x244 Rx result save slot 1.

Definition at line 817 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXRSS2R

volatile uint32_t r_mipi_dsi_regs_t::RXRSS2R

+0x248 Rx result save slot 2.

Definition at line 818 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXRSS3R

volatile uint32_t r_mipi_dsi_regs_t::RXRSS3R

+0x24C Rx result save slot 3.

Definition at line 819 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXRSSCR

volatile uint32_t r_mipi_dsi_regs_t::RXRSSCR

+0x234 Rx result save clear.

Definition at line 813 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXRSSR

volatile uint32_t r_mipi_dsi_regs_t::RXRSSR

+0x230 Rx result save status.

Definition at line 812 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_rx_result_get().

◆ RXSCR

volatile uint32_t r_mipi_dsi_regs_t::RXSCR

+0x204 Receive status clear.

Definition at line 801 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), ra8_mipi_dsi_dispatch_receive(), and ra8_mipi_dsi_te_event_clear().

◆ RXSR

volatile uint32_t r_mipi_dsi_regs_t::RXSR

+0x200 Receive status (RO).

Definition at line 800 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_receive(), and ra8_mipi_dsi_te_event_pending().

◆ SQCH0DSC

r_mipi_dsi_descriptor_t r_mipi_dsi_regs_t::SQCH0DSC[8]

+0x780..0x7FC ch0 desc 0..7.

Definition at line 876 of file ra8_mipi_dsi_regs.h.

Referenced by internal_send_stage_and_pulse().

◆ SQCH0IER

volatile uint32_t r_mipi_dsi_regs_t::SQCH0IER

+0x5D8 Sequence ch 0 int enable.

Definition at line 865 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ SQCH0SCR

volatile uint32_t r_mipi_dsi_regs_t::SQCH0SCR

+0x5D4 Sequence ch 0 clear.

Definition at line 864 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), and ra8_mipi_dsi_dispatch_seq0().

◆ SQCH0SET0R

volatile uint32_t r_mipi_dsi_regs_t::SQCH0SET0R

+0x5C0 Sequence ch 0 START bit.

Definition at line 860 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_pulse_start().

◆ SQCH0SR

volatile uint32_t r_mipi_dsi_regs_t::SQCH0SR

+0x5D0 Sequence ch 0 status (RO).

Definition at line 863 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_seq0().

◆ SQCH1DSC

r_mipi_dsi_descriptor_t r_mipi_dsi_regs_t::SQCH1DSC[8]

+0x800..0x87C ch1 desc 0..7.

Definition at line 877 of file ra8_mipi_dsi_regs.h.

Referenced by internal_send_stage_and_pulse().

◆ SQCH1IER

volatile uint32_t r_mipi_dsi_regs_t::SQCH1IER

+0x618 Sequence ch 1 int enable.

Definition at line 873 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ SQCH1SCR

volatile uint32_t r_mipi_dsi_regs_t::SQCH1SCR

+0x614 Sequence ch 1 clear.

Definition at line 872 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), and ra8_mipi_dsi_dispatch_seq1().

◆ SQCH1SET0R

volatile uint32_t r_mipi_dsi_regs_t::SQCH1SET0R

+0x600 Sequence ch 1 START bit.

Definition at line 868 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_pulse_start().

◆ SQCH1SR

volatile uint32_t r_mipi_dsi_regs_t::SQCH1SR

+0x610 Sequence ch 1 status (RO).

Definition at line 871 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_seq1().

◆ TATOSETR

volatile uint32_t r_mipi_dsi_regs_t::TATOSETR

+0x2E8 Turnaround ack timeout.

Definition at line 830 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_timeouts().

◆ TXPPD0R

volatile uint32_t r_mipi_dsi_regs_t::TXPPD0R

+0x160 Tx packet payload data 0.

Definition at line 794 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_stage_payload().

◆ TXPPD1R

volatile uint32_t r_mipi_dsi_regs_t::TXPPD1R

+0x164 Tx packet payload data 1.

Definition at line 795 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_stage_payload().

◆ TXPPD2R

volatile uint32_t r_mipi_dsi_regs_t::TXPPD2R

+0x168 Tx packet payload data 2.

Definition at line 796 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_stage_payload().

◆ TXPPD3R

volatile uint32_t r_mipi_dsi_regs_t::TXPPD3R

+0x16C Tx packet payload data 3.

Definition at line 797 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_stage_payload().

◆ TXSETR

volatile uint32_t r_mipi_dsi_regs_t::TXSETR

+0x100 Lane enable + count.

Definition at line 784 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link().

◆ ULPSCR

volatile uint32_t r_mipi_dsi_regs_t::ULPSCR

+0x10C ULPS enter/exit pulses.

Definition at line 787 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_ulps_enter(), and ra8_mipi_dsi_ulps_exit().

◆ ULPSSETR

volatile uint32_t r_mipi_dsi_regs_t::ULPSSETR

+0x108 ULPS wakeup period.

Definition at line 786 of file ra8_mipi_dsi_regs.h.

Referenced by internal_program_link().

◆ VMHPSETR

volatile uint32_t r_mipi_dsi_regs_t::VMHPSETR

+0x434 Horizontal porch timing.

Definition at line 857 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

◆ VMHSSETR

volatile uint32_t r_mipi_dsi_regs_t::VMHSSETR

+0x430 Horizontal sync timing.

Definition at line 856 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

◆ VMIER

volatile uint32_t r_mipi_dsi_regs_t::VMIER

+0x418 Video-mode int enable.

Definition at line 850 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_irq_enable().

◆ VMPPSETR

volatile uint32_t r_mipi_dsi_regs_t::VMPPSETR

+0x420 Video pixel-packet set.

Definition at line 852 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

◆ VMSCR

volatile uint32_t r_mipi_dsi_regs_t::VMSCR

+0x414 Video-mode status clear.

Definition at line 849 of file ra8_mipi_dsi_regs.h.

Referenced by internal_ra8_mipi_dsi_clear_all_status(), ra8_mipi_dsi_clear_status(), ra8_mipi_dsi_dispatch_video(), and ra8_mipi_dsi_video_stop().

◆ VMSET0R

volatile uint32_t r_mipi_dsi_regs_t::VMSET0R

+0x400 Video-mode set 0.

Definition at line 845 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_start(), and ra8_mipi_dsi_video_stop().

◆ VMSET1R

volatile uint32_t r_mipi_dsi_regs_t::VMSET1R

+0x404 Video-mode set 1.

Definition at line 846 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

◆ VMSR

volatile uint32_t r_mipi_dsi_regs_t::VMSR

+0x410 Video-mode status (RO).

Definition at line 848 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_dispatch_video(), ra8_mipi_dsi_video_start(), and ra8_mipi_dsi_video_stop().

◆ VMVPSETR

volatile uint32_t r_mipi_dsi_regs_t::VMVPSETR

+0x42C Vertical porch timing.

Definition at line 855 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

◆ VMVSSETR

volatile uint32_t r_mipi_dsi_regs_t::VMVSSETR

+0x428 Vertical sync timing.

Definition at line 854 of file ra8_mipi_dsi_regs.h.

Referenced by ra8_mipi_dsi_video_configure().

The documentation for this struct was generated from the following file: