ra8_mipi_dsi.c

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#include "ra8_mipi_dsi.h"
 
#include <stddef.h>
#include <stdint.h>
#include <string.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_log.h"
#include "ra8_mipi_dsi_internal.h"
#include "ra8_mipi_dsi_regs.h"
#include "ra8_mstp.h"

static const char* s_tag = "MIPI_DSI";

ra8_mipi_dsi_event_fn_t s_mipi_dsi_event_fn;

void* s_mipi_dsi_event_ctx;

static bool s_continuous_clock;

static bool s_clock_lanes_in_ulps;

static bool s_data_lanes_in_ulps;

uint8_t* s_mipi_dsi_pending_rx_buffer;

uint16_t s_mipi_dsi_pending_rx_len;

static bool s_initialized;
 
/* =============================================================================
 * Internal helpers
 * =============================================================================
 */

RA8_INTERNAL static ra8_err_t internal_ra8_mipi_dsi_validate_cfg(const ra8_mipi_dsi_config_t* cfg)
{
  if ((cfg->lane_count != k_ra8_mipi_dsi_lanes_1) && (cfg->lane_count != k_ra8_mipi_dsi_lanes_2)) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL static void internal_ra8_mipi_dsi_clear_all_status(void)
{
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
  /* HUM Ch 65.2 "SQCH0SCR : Sequence Channel 0 Status Clear", p 3902 */
  reg->SQCH0SCR = k_ra8_mipi_dsi_sqch_clear_all;
  /* HUM Ch 65.2 "SQCH1SCR : Sequence Channel 1 Status Clear", p 3907 */
  reg->SQCH1SCR = k_ra8_mipi_dsi_sqch_clear_all;
  /* HUM Ch 65.2 "VMSCR : Video Mode Status Clear", p 3894 */
  reg->VMSCR = k_ra8_mipi_dsi_vmsr_clear_all;
  /* HUM Ch 65.2 "RXSCR : Receive Status Clear", p 3855 */
  reg->RXSCR = k_ra8_mipi_dsi_rxsr_clear_all;
  /* HUM Ch 65.2 "FERRSCR : Fatal Error Status Clear", p 3878 */
  reg->FERRSCR = k_ra8_mipi_dsi_ferrsr_clear_all;
  /* HUM Ch 65.2 "PLSCR : PHY Lane Status Clear", p 3887 */
  reg->PLSCR = k_ra8_mipi_dsi_plsr_clear_all;
}

RA8_INTERNAL static uint32_t internal_ra8_mipi_dsi_make_txsetr(const ra8_mipi_dsi_config_t* cfg)
{
  uint32_t v = k_ra8_mipi_dsi_txset_clen | k_ra8_mipi_dsi_txset_dlen;
  if (cfg->lane_count == k_ra8_mipi_dsi_lanes_2) {
    v |= k_ra8_mipi_dsi_txset_lane2;
  }
  return v;
}

RA8_INTERNAL static uint32_t internal_ra8_mipi_dsi_make_dsisetr(const ra8_mipi_dsi_config_t* cfg)
{
  uint32_t v = ((uint32_t)cfg->max_return_packet_size & k_ra8_mipi_dsi_dsisetr_mrpsz_mask);
  if (cfg->ecc_check_enable) {
    v |= k_ra8_mipi_dsi_dsisetr_eccen;
  }
  if (cfg->eotp_enable) {
    v |= k_ra8_mipi_dsi_dsisetr_eotpen;
  }
  if (cfg->scramble_enable) {
    v |= k_ra8_mipi_dsi_dsisetr_scren;
  }
  if (cfg->tearing_detect_enable) {
    v |= k_ra8_mipi_dsi_dsisetr_extemd;
  }
  v |= (((uint32_t)cfg->crc_check_vc_mask) << (uint32_t)k_dsisetr_vc_crc_shift) &
       k_ra8_mipi_dsi_dsisetr_vc_crc_mask;
  return v;
}

ra8_err_t
priv_ra8_mipi_dsi_internal_wait_eq(volatile const uint32_t* reg, uint32_t mask, uint32_t expect)
{
  for (uint32_t i = 0U; i < k_ra8_mipi_dsi_busy_loop_max; ++i) {
    if ((*reg & mask) == expect) {
      return k_ra8_ok;
    }
  }
  return k_ra8_err_hw_timeout;
}
 
/* =============================================================================
 * Public API -- lifecycle
 * =============================================================================
 */

RA8_INTERNAL static void internal_program_link(const ra8_mipi_dsi_config_t* cfg)
{
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
 
  /* HUM Ch 65.2 "RSTCR" p 3845 */ /* pulse SWRST. */
  reg->RSTCR = k_ra8_mipi_dsi_rstcr_swrst;
  reg->RSTCR = 0U;
 
  /* HUM Ch 65.2 "TXSETR" p 3842 */ /* / "ULPSSETR" p 3849 / "DSISETR" p 3855 */
  reg->TXSETR   = internal_ra8_mipi_dsi_make_txsetr(cfg);
  reg->ULPSSETR = (uint32_t)cfg->ulps_wakeup_period << (uint32_t)k_ulpssetr_wkup_shift;
  reg->DSISETR  = internal_ra8_mipi_dsi_make_dsisetr(cfg);
 
  /* HUM Ch 65.2 "CLSTPTSETR" p 3881 */
  reg->CLSTPTSETR =
    ((((uint32_t)cfg->timing.clock_stop_time) << k_ra8_mipi_dsi_clstpt_clkstpt_shift) &
     k_ra8_mipi_dsi_clstpt_clkstpt_mask) |
    ((((uint32_t)cfg->timing.clock_beforehand_time) << k_ra8_mipi_dsi_clstpt_clkbfht_shift) &
     k_ra8_mipi_dsi_clstpt_clkbfht_mask) |
    ((((uint32_t)cfg->timing.clock_keep_time) << k_ra8_mipi_dsi_clstpt_clkkpt_shift) &
     k_ra8_mipi_dsi_clstpt_clkkpt_mask);
 
  /* HUM Ch 65.2 "LPTRNSTSETR" p 3883 */
  reg->LPTRNSTSETR = ((uint32_t)cfg->timing.go_lp_and_back) & k_ra8_mipi_dsi_lptrnst_golpbkt_mask;
}

RA8_INTERNAL static void internal_program_timeouts(const ra8_mipi_dsi_config_t* cfg)
{
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
  reg->PRESPTOBTASETR             = cfg->timeouts.bta_timeout;
  reg->PRESPTOLPSETR              = cfg->timeouts.lp_rw_timeout;
  reg->PRESPTOHSSETR              = cfg->timeouts.hs_rw_timeout;
  reg->HSTXTOSETR                 = cfg->timeouts.hs_tx_timeout;
  reg->LRXHTOSETR                 = cfg->timeouts.lp_rx_host_timeout;
  reg->TATOSETR                   = cfg->timeouts.turnaround_timeout;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_init(const ra8_mipi_dsi_config_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "cfg must not be nullptr");
  const ra8_err_t cfg_err = internal_ra8_mipi_dsi_validate_cfg(cfg);
  RA8_RETURN_ON_ERROR(cfg_err, s_tag, "mipi_dsi_init: cfg invalid");
 
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446 */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_mipi_dsi);
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "mipi_dsi_init: mstp enable");
 
  internal_program_link(cfg);
  internal_program_timeouts(cfg);
  internal_ra8_mipi_dsi_clear_all_status();
 
  s_continuous_clock           = (cfg->clock_mode == k_ra8_mipi_dsi_clock_continuous);
  s_clock_lanes_in_ulps        = false;
  s_data_lanes_in_ulps         = false;
  s_mipi_dsi_event_fn          = nullptr;
  s_mipi_dsi_event_ctx         = nullptr;
  s_mipi_dsi_pending_rx_buffer = nullptr;
  s_mipi_dsi_pending_rx_len    = 0U;
  s_initialized                = true;
 
  ra8_log_info(s_tag, "mipi_dsi_init done");
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_deinit(void)
{
  /* Idempotent: a second deinit (or a deinit on a never-initialized
   * driver) must succeed without underflowing the MSTPC refcount.
   * HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446. */
  if (!s_initialized) {
    return k_ra8_ok;
  }
 
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
  /* HUM Ch 65.2 "RSTCR : Reset Control Register", p 3845 */
  reg->RSTCR = k_ra8_mipi_dsi_rstcr_swrst;
 
  s_mipi_dsi_event_fn          = nullptr;
  s_mipi_dsi_event_ctx         = nullptr;
  s_continuous_clock           = false;
  s_clock_lanes_in_ulps        = false;
  s_data_lanes_in_ulps         = false;
  s_mipi_dsi_pending_rx_buffer = nullptr;
  s_mipi_dsi_pending_rx_len    = 0U;
 
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446 */
  const ra8_err_t err = ra8_mstp_disable(k_ra8_mstp_mipi_dsi);
  if (err == k_ra8_ok) {
    s_initialized = false;
  }
  return err;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_enter_stop(void)
{
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446.
   * Releases the MSTPC reference taken in ``init``; the matching
   * ``exit_stop`` re-acquires it. */
  if (!s_initialized) {
    return k_ra8_err_invalid_state;
  }
  const ra8_err_t err = ra8_mstp_disable(k_ra8_mstp_mipi_dsi);
  if (err == k_ra8_ok) {
    s_initialized = false;
  }
  return err;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_exit_stop(void)
{
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 446.
   * Re-acquires the MSTPC reference released by ``enter_stop``. */
  if (s_initialized) {
    return k_ra8_err_invalid_state;
  }
  const ra8_err_t err = ra8_mstp_enable(k_ra8_mstp_mipi_dsi);
  if (err == k_ra8_ok) {
    s_initialized = true;
  }
  return err;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_soft_reset(void)
{
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
  /* HUM Ch 65.2 "RSTCR : Reset Control Register", p 3845 */
  reg->RSTCR = k_ra8_mipi_dsi_rstcr_swrst;
  /* HUM Ch 65.2 "RSTCR : Reset Control Register", p 3845 */
  reg->RSTCR = 0U;
  return k_ra8_ok;
}
 
/* =============================================================================
 * HS clock control
 * =============================================================================
 */
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_hs_clock_start(void)
{
  volatile r_mipi_dsi_regs_t* reg   = ra8_mipi_dsi();
  uint32_t                    hsclk = k_ra8_mipi_dsi_hsclk_start;
  if (s_continuous_clock) {
    hsclk |= k_ra8_mipi_dsi_hsclk_continuous;
  }
  /* HUM Ch 65.2 "HSCLKSETR : HS Clock Setting Register", p 3843 */
  reg->HSCLKSETR = hsclk;
  /* HUM Ch 65.2 "PLSR : PHY Lane Status Register", p 3884 */
  return priv_ra8_mipi_dsi_internal_wait_eq(&reg->PLSR,
                                            k_ra8_mipi_dsi_plsr_cllp2hs,
                                            k_ra8_mipi_dsi_plsr_cllp2hs);
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_hs_clock_stop(void)
{
  volatile r_mipi_dsi_regs_t* reg = ra8_mipi_dsi();
  /* HUM Ch 65.2 "HSCLKSETR : HS Clock Setting Register", p 3843 */
  reg->HSCLKSETR = 0U;
  /* HUM Ch 65.2 "PLSR : PHY Lane Status Register", p 3884 */
  return priv_ra8_mipi_dsi_internal_wait_eq(&reg->PLSR,
                                            k_ra8_mipi_dsi_plsr_clhs2lp,
                                            k_ra8_mipi_dsi_plsr_clhs2lp);
}
 
/* =============================================================================
 * ULPS
 * =============================================================================
 */
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_ulps_enter(uint8_t lanes)
{
  if (lanes == k_ra8_mipi_dsi_lane_none) {
    return k_ra8_err_invalid_arg;
  }
  /* Continuous clock mode forbids clock-lane ULPS -- HUM Ch 65 lists
   * this constraint and FSP enforces the same precondition. */
  if (((lanes & k_ra8_mipi_dsi_lane_clock) != 0U) && s_continuous_clock) {
    ra8_log_error(s_tag, "ulps_enter: clock lane + continuous mode rejected");
    return k_ra8_err_invalid_arg;
  }
  uint32_t ulpscr = 0U;
  if (((lanes & k_ra8_mipi_dsi_lane_data) != 0U) && !s_data_lanes_in_ulps) {
    ulpscr |= k_ra8_mipi_dsi_ulpscr_dlent;
    s_data_lanes_in_ulps = true;
  }
  if (((lanes & k_ra8_mipi_dsi_lane_clock) != 0U) && !s_clock_lanes_in_ulps) {
    ulpscr |= k_ra8_mipi_dsi_ulpscr_clent;
    s_clock_lanes_in_ulps = true;
  }
  /* HUM Ch 65.2 "ULPSCR : ULPS Control Register", p 3844 */
  ra8_mipi_dsi()->ULPSCR = ulpscr;
  return k_ra8_ok;
}
 
[[nodiscard]] ra8_err_t ra8_mipi_dsi_ulps_exit(uint8_t lanes)
{
  if (lanes == k_ra8_mipi_dsi_lane_none) {
    return k_ra8_err_invalid_arg;
  }
  uint32_t ulpscr = 0U;
  if (((lanes & k_ra8_mipi_dsi_lane_data) != 0U) && s_data_lanes_in_ulps) {
    ulpscr |= k_ra8_mipi_dsi_ulpscr_dlexit;
    s_data_lanes_in_ulps = false;
  }
  if (((lanes & k_ra8_mipi_dsi_lane_clock) != 0U) && s_clock_lanes_in_ulps) {
    ulpscr |= k_ra8_mipi_dsi_ulpscr_clexit;
    s_clock_lanes_in_ulps = false;
  }
  /* HUM Ch 65.2 "ULPSCR : ULPS Control Register", p 3844 */
  ra8_mipi_dsi()->ULPSCR = ulpscr;
  return k_ra8_ok;
}