ra8_mipi_dsi_regs.h File Reference

MIPI DSI Host (DSI-2) register layout for the RA8D2. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	r_mipi_dsi_descriptor_t
	One sequence-channel descriptor slot (4 x 32-bit registers). More...
struct	r_mipi_dsi_regs_t
	MIPI DSI host register block (full layout). More...

Enumerations
enum	ra8_mipi_dsi_addr_t : uintptr_t {   k_ra8_mipi_dsi_base_addr_s = 0x40346000UL ,   k_ra8_mipi_dsi_base_addr_ns = 0x50346000UL }
	Memory-mapped base addresses for the MIPI DSI host. More...
enum	ra8_mipi_dsi_size_t : uint16_t {   k_ra8_mipi_dsi_window_bytes = 0x880U ,   k_ra8_mipi_dsi_max_lanes = 2U ,   k_ra8_mipi_dsi_payload_max = 16U ,   k_ra8_mipi_dsi_rx_slots = 4U ,   k_ra8_mipi_dsi_descriptors = 8U ,   k_ra8_mipi_dsi_max_lp_bytes = 128U ,   k_ra8_mipi_dsi_max_hs_bytes = 1024U }
	Window size and key constants for the MIPI DSI block. More...
enum	ra8_mipi_dsi_busy_loop_t : uint32_t { k_ra8_mipi_dsi_busy_loop_max = 100000UL }
	Bounded poll iteration cap shared by every busy-wait helper. More...
enum	ra8_mipi_dsi_rxrinfoowscr_t : uint32_t {   k_ra8_mipi_dsi_rxrinfoow_sl0 = 1UL << 0 ,   k_ra8_mipi_dsi_rxrinfoow_sl1 = 1UL << 1 ,   k_ra8_mipi_dsi_rxrinfoow_sl2 = 1UL << 2 ,   k_ra8_mipi_dsi_rxrinfoow_sl3 = 1UL << 3 }
	Bit masks for RXRINFOOWSCR (receive-result info-overwrite clear). More...
enum	ra8_mipi_dsi_isr_mask_t : uint32_t {   k_ra8_mipi_dsi_isr_sq0 = 1UL << 0 ,   k_ra8_mipi_dsi_isr_sq1 = 1UL << 4 ,   k_ra8_mipi_dsi_isr_vm = 1UL << 8 ,   k_ra8_mipi_dsi_isr_rcv = 1UL << 12 ,   k_ra8_mipi_dsi_isr_ferr = 1UL << 16 ,   k_ra8_mipi_dsi_isr_ppi = 1UL << 20 }
	Bit masks for the top-level Interrupt Status Register (ISR). More...
enum	ra8_mipi_dsi_linksr_mask_t : uint32_t {   k_ra8_mipi_dsi_link_sq0run = 1UL << 0 ,   k_ra8_mipi_dsi_link_sq1run = 1UL << 4 ,   k_ra8_mipi_dsi_link_vrun = 1UL << 8 ,   k_ra8_mipi_dsi_link_hsbusy = 1UL << 12 ,   k_ra8_mipi_dsi_link_lpbusy = 1UL << 13 }
	Bit masks for the Link Status Register (LINKSR). More...
enum	ra8_mipi_dsi_txset_t : uint32_t {   k_ra8_mipi_dsi_txset_lane1 = 0UL << 0 ,   k_ra8_mipi_dsi_txset_lane2 = 1UL << 0 ,   k_ra8_mipi_dsi_txset_clen = 1UL << 8 ,   k_ra8_mipi_dsi_txset_dlen = 1UL << 9 }
	Bit fields for TXSETR (lane configuration). More...
enum	ra8_mipi_dsi_hsclk_t : uint32_t {   k_ra8_mipi_dsi_hsclk_start = 1UL << 0 ,   k_ra8_mipi_dsi_hsclk_continuous = 1UL << 1 }
	Bit fields for HSCLKSETR. More...
enum	ra8_mipi_dsi_ulpscr_t : uint32_t {   k_ra8_mipi_dsi_ulpscr_clent = 1UL << 24 ,   k_ra8_mipi_dsi_ulpscr_clexit = 1UL << 25 ,   k_ra8_mipi_dsi_ulpscr_dlent = 1UL << 28 ,   k_ra8_mipi_dsi_ulpscr_dlexit = 1UL << 29 }
	Bit fields for ULPSCR. More...
enum	ra8_mipi_dsi_rstcr_t : uint32_t {   k_ra8_mipi_dsi_rstcr_swrst = 1UL << 0 ,   k_ra8_mipi_dsi_rstcr_ftxstp = 1UL << 16 }
	Bit fields for RSTCR (software reset control). More...
enum	ra8_mipi_dsi_rstsr_t : uint32_t {   k_ra8_mipi_dsi_rstsr_rsths = 1UL << 0 ,   k_ra8_mipi_dsi_rstsr_rstlp = 1UL << 1 ,   k_ra8_mipi_dsi_rstsr_rstapb = 1UL << 2 ,   k_ra8_mipi_dsi_rstsr_rstaxi = 1UL << 3 ,   k_ra8_mipi_dsi_rstsr_rstv = 1UL << 4 ,   k_ra8_mipi_dsi_rstsr_dl0stp = 1UL << 8 ,   k_ra8_mipi_dsi_rstsr_dl1stp = 1UL << 9 ,   k_ra8_mipi_dsi_rstsr_dl0dir = 1UL << 15 ,   k_ra8_mipi_dsi_rstsr_all_reset = (1UL << 0) | (1UL << 1) | (1UL << 2) | (1UL << 3) | (1UL << 4) }
	Bit fields for RSTSR (software reset status). More...
enum	ra8_mipi_dsi_dsisetr_t : uint32_t {   k_ra8_mipi_dsi_dsisetr_eccen = 1UL << 16 ,   k_ra8_mipi_dsi_dsisetr_vc0crcen = 1UL << 20 ,   k_ra8_mipi_dsi_dsisetr_vc1crcen = 1UL << 21 ,   k_ra8_mipi_dsi_dsisetr_vc2crcen = 1UL << 22 ,   k_ra8_mipi_dsi_dsisetr_vc3crcen = 1UL << 23 ,   k_ra8_mipi_dsi_dsisetr_scren = 1UL << 29 ,   k_ra8_mipi_dsi_dsisetr_extemd = 1UL << 30 ,   k_ra8_mipi_dsi_dsisetr_eotpen = 1UL << 31 ,   k_ra8_mipi_dsi_dsisetr_mrpsz_mask = 0xFFFFUL ,   k_ra8_mipi_dsi_dsisetr_vc_crc_mask = (1UL << 20) | (1UL << 21) | (1UL << 22) | (1UL << 23) }
	Bit fields for DSISETR (DSI link configuration). More...
enum	ra8_mipi_dsi_rxsr_t : uint32_t {   k_ra8_mipi_dsi_rxsr_btarend = 1UL << 0 ,   k_ra8_mipi_dsi_rxsr_lrxhto = 1UL << 1 ,   k_ra8_mipi_dsi_rxsr_tato = 1UL << 2 ,   k_ra8_mipi_dsi_rxsr_rxresp = 1UL << 8 ,   k_ra8_mipi_dsi_rxsr_rxeotp = 1UL << 10 ,   k_ra8_mipi_dsi_rxsr_rxte = 1UL << 13 ,   k_ra8_mipi_dsi_rxsr_rxack = 1UL << 14 ,   k_ra8_mipi_dsi_rxsr_extedet = 1UL << 15 ,   k_ra8_mipi_dsi_rxsr_mlferr = 1UL << 16 ,   k_ra8_mipi_dsi_rxsr_eccerrm = 1UL << 17 ,   k_ra8_mipi_dsi_rxsr_unexerr = 1UL << 18 ,   k_ra8_mipi_dsi_rxsr_wcerr = 1UL << 20 ,   k_ra8_mipi_dsi_rxsr_crcerr = 1UL << 21 ,   k_ra8_mipi_dsi_rxsr_iberr = 1UL << 22 ,   k_ra8_mipi_dsi_rxsr_rxovferr = 1UL << 23 ,   k_ra8_mipi_dsi_rxsr_prtoerr = 1UL << 24 ,   k_ra8_mipi_dsi_rxsr_noreserr = 1UL << 25 ,   k_ra8_mipi_dsi_rxsr_rsizeerr = 1UL << 26 ,   k_ra8_mipi_dsi_rxsr_eccerrs = 1UL << 28 ,   k_ra8_mipi_dsi_rxsr_rxake = 1UL << 30 ,   k_ra8_mipi_dsi_rxsr_clear_all }
	Bit fields for RXSR / RXSCR / RXIER (receive status path). More...
enum	ra8_mipi_dsi_rxrssr_t : uint32_t {   k_ra8_mipi_dsi_rxrssr_slt0vld = 1UL << 0 ,   k_ra8_mipi_dsi_rxrssr_slt1vld = 1UL << 1 ,   k_ra8_mipi_dsi_rxrssr_slt2vld = 1UL << 2 ,   k_ra8_mipi_dsi_rxrssr_slt3vld = 1UL << 3 }
	Bit fields for RXRSSR / RXRSSCR (receive-result slot valid). More...
enum	ra8_mipi_dsi_rxrss_t : uint32_t {   k_ra8_mipi_dsi_rxrss_data0_mask = 0x000000FFUL ,   k_ra8_mipi_dsi_rxrss_data1_mask = 0x0000FF00UL ,   k_ra8_mipi_dsi_rxrss_dt_mask = 0x003F0000UL ,   k_ra8_mipi_dsi_rxrss_vc_mask = 0x00C00000UL ,   k_ra8_mipi_dsi_rxrss_fmt = 1UL << 24 ,   k_ra8_mipi_dsi_rxrss_rxsuc = 1UL << 25 ,   k_ra8_mipi_dsi_rxrss_rxferr = 1UL << 26 ,   k_ra8_mipi_dsi_rxrss_rxfail = 1UL << 27 ,   k_ra8_mipi_dsi_rxrss_rxpfail = 1UL << 28 ,   k_ra8_mipi_dsi_rxrss_rxcerr = 1UL << 29 ,   k_ra8_mipi_dsi_rxrss_rxake = 1UL << 30 ,   k_ra8_mipi_dsi_rxrss_infoow = 1UL << 31 }
	Decoded fields for an RXRSS slot value (header capture). More...
enum	ra8_mipi_dsi_akep_t : uint32_t {   k_ra8_mipi_dsi_akep_erep_mask = 0xFFFFUL ,   k_ra8_mipi_dsi_akep_vc_mask = 0xFUL << 16 }
	Bit fields for AKEPLATIR / AKEPACMSR / AKEPSCR. More...
enum	ra8_mipi_dsi_ferrsr_t : uint32_t {   k_ra8_mipi_dsi_ferrsr_htxto = 1UL << 0 ,   k_ra8_mipi_dsi_ferrsr_lrxhto = 1UL << 1 ,   k_ra8_mipi_dsi_ferrsr_tato = 1UL << 2 ,   k_ra8_mipi_dsi_ferrsr_escent = 1UL << 16 ,   k_ra8_mipi_dsi_ferrsr_syncesc = 1UL << 17 ,   k_ra8_mipi_dsi_ferrsr_ctrl = 1UL << 18 ,   k_ra8_mipi_dsi_ferrsr_clp0 = 1UL << 19 ,   k_ra8_mipi_dsi_ferrsr_clp1 = 1UL << 20 ,   k_ra8_mipi_dsi_ferrsr_clp0s = 1UL << 27 ,   k_ra8_mipi_dsi_ferrsr_clp1s = 1UL << 28 ,   k_ra8_mipi_dsi_ferrsr_clear_all }
	Bit fields for FERRSR / FERRSCR / FERRIER (fatal errors). More...
enum	ra8_mipi_dsi_plsr_t : uint32_t {   k_ra8_mipi_dsi_plsr_cluan = 1UL << 0 ,   k_ra8_mipi_dsi_plsr_clstp = 1UL << 1 ,   k_ra8_mipi_dsi_plsr_dl0rle = 1UL << 2 ,   k_ra8_mipi_dsi_plsr_dl0rue = 1UL << 3 ,   k_ra8_mipi_dsi_plsr_dl0uan = 1UL << 4 ,   k_ra8_mipi_dsi_plsr_dl1uan = 1UL << 5 ,   k_ra8_mipi_dsi_plsr_dl0stp = 1UL << 8 ,   k_ra8_mipi_dsi_plsr_dl1stp = 1UL << 9 ,   k_ra8_mipi_dsi_plsr_dl0rx2tx = 1UL << 12 ,   k_ra8_mipi_dsi_plsr_dl0tx2rx = 1UL << 13 ,   k_ra8_mipi_dsi_plsr_dl0dir = 1UL << 15 ,   k_ra8_mipi_dsi_plsr_clulpent = 1UL << 24 ,   k_ra8_mipi_dsi_plsr_clulpext = 1UL << 25 ,   k_ra8_mipi_dsi_plsr_cllp2hs = 1UL << 26 ,   k_ra8_mipi_dsi_plsr_clhs2lp = 1UL << 27 ,   k_ra8_mipi_dsi_plsr_dlulpent = 1UL << 28 ,   k_ra8_mipi_dsi_plsr_dlulpext = 1UL << 29 ,   k_ra8_mipi_dsi_plsr_clear_all }
	Bit fields for PLSR / PLSCR / PLIER (PHY/PPI lane status). More...
enum	ra8_mipi_dsi_vmset0_t : uint32_t {   k_ra8_mipi_dsi_vmset0_vstart = 1UL << 0 ,   k_ra8_mipi_dsi_vmset0_vstop = 1UL << 1 ,   k_ra8_mipi_dsi_vmset0_hsanolp = 1UL << 8 ,   k_ra8_mipi_dsi_vmset0_hbpnolp = 1UL << 9 ,   k_ra8_mipi_dsi_vmset0_hfpnolp = 1UL << 10 }
	Bit fields for VMSET0R (video-mode set 0). More...
enum	ra8_mipi_dsi_vmset1_t : uint32_t {   k_ra8_mipi_dsi_vmset1_dly_shift = 2U ,   k_ra8_mipi_dsi_vmset1_dly_mask = 0x3FFCUL }
	Bit fields for VMSET1R (video-mode set 1: pipeline delay). More...
enum	ra8_mipi_dsi_vmsr_t : uint32_t {   k_ra8_mipi_dsi_vmsr_running = 1UL << 0 ,   k_ra8_mipi_dsi_vmsr_virdy = 1UL << 4 ,   k_ra8_mipi_dsi_vmsr_stop = 1UL << 8 ,   k_ra8_mipi_dsi_vmsr_timerr = 1UL << 20 ,   k_ra8_mipi_dsi_vmsr_vbufudf = 1UL << 22 ,   k_ra8_mipi_dsi_vmsr_vbufovf = 1UL << 23 ,   k_ra8_mipi_dsi_vmsr_clear_all }
	Bit fields for VMSR / VMSCR / VMIER. More...
enum	ra8_mipi_dsi_vmppsetr_t : uint32_t {   k_ra8_mipi_dsi_vmpp_txesync = 1UL << 15 ,   k_ra8_mipi_dsi_vmpp_dt_shift = 16U ,   k_ra8_mipi_dsi_vmpp_dt_mask = 0x3FUL << 16 ,   k_ra8_mipi_dsi_vmpp_vc_shift = 22U ,   k_ra8_mipi_dsi_vmpp_vc_mask = 0x3UL << 22 }
	Bit fields for VMPPSETR (video-mode pixel-packet set). More...
enum	ra8_mipi_dsi_vmvssetr_t : uint32_t {   k_ra8_mipi_dsi_vmvs_vsa_mask = 0x00000FFFUL ,   k_ra8_mipi_dsi_vmvs_vspol = 1UL << 15 ,   k_ra8_mipi_dsi_vmvs_vact_shift = 16U ,   k_ra8_mipi_dsi_vmvs_vact_mask = 0x7FFFUL << 16 }
	Bit fields for VMVSSETR (vertical sync timing). More...
enum	ra8_mipi_dsi_vmvpsetr_t : uint32_t {   k_ra8_mipi_dsi_vmvp_vbp_mask = 0x00001FFFUL ,   k_ra8_mipi_dsi_vmvp_vfp_shift = 16U ,   k_ra8_mipi_dsi_vmvp_vfp_mask = 0x1FFFUL << 16 }
	Bit fields for VMVPSETR (vertical porch timing). More...
enum	ra8_mipi_dsi_vmhssetr_t : uint32_t {   k_ra8_mipi_dsi_vmhs_hsa_mask = 0x00000FFFUL ,   k_ra8_mipi_dsi_vmhs_hspol = 1UL << 15 ,   k_ra8_mipi_dsi_vmhs_hact_shift = 16U ,   k_ra8_mipi_dsi_vmhs_hact_mask = 0x7FFFUL << 16 }
	Bit fields for VMHSSETR (horizontal sync timing). More...
enum	ra8_mipi_dsi_vmhpsetr_t : uint32_t {   k_ra8_mipi_dsi_vmhp_hbp_mask = 0x00001FFFUL ,   k_ra8_mipi_dsi_vmhp_hfp_shift = 16U ,   k_ra8_mipi_dsi_vmhp_hfp_mask = 0x1FFFUL << 16 }
	Bit fields for VMHPSETR (horizontal porch timing). More...
enum	ra8_mipi_dsi_clstpt_t : uint32_t {   k_ra8_mipi_dsi_clstpt_clkstpt_shift = 2U ,   k_ra8_mipi_dsi_clstpt_clkstpt_mask = 0xFFCUL ,   k_ra8_mipi_dsi_clstpt_clkbfht_shift = 16U ,   k_ra8_mipi_dsi_clstpt_clkbfht_mask = 0xFFUL << 16 ,   k_ra8_mipi_dsi_clstpt_clkkpt_shift = 24U ,   k_ra8_mipi_dsi_clstpt_clkkpt_mask = 0xFFUL << 24 }
	Bit fields for CLSTPTSETR (clock-lane stop / beforehand / keep). More...
enum	ra8_mipi_dsi_lptrnst_t : uint32_t { k_ra8_mipi_dsi_lptrnst_golpbkt_mask = 0x3FFUL }
	Bit fields for LPTRNSTSETR (LP transition timing). More...
enum	ra8_mipi_dsi_presptolp_t : uint32_t {   k_ra8_mipi_dsi_presptolp_lpwto_mask = 0xFFFFUL ,   k_ra8_mipi_dsi_presptolp_lprto_shift = 16U ,   k_ra8_mipi_dsi_presptolp_lprto_mask = 0xFFFFUL << 16 }
	Bit fields for PRESPTOLPSETR (LP read/write timeouts). More...
enum	ra8_mipi_dsi_presptohs_t : uint32_t {   k_ra8_mipi_dsi_presptohs_hswto_mask = 0xFFFFUL ,   k_ra8_mipi_dsi_presptohs_hsrto_shift = 16U ,   k_ra8_mipi_dsi_presptohs_hsrto_mask = 0xFFFFUL << 16 }
	Bit fields for PRESPTOHSSETR (HS read/write timeouts). More...
enum	ra8_mipi_dsi_sqch_t : uint32_t {   k_ra8_mipi_dsi_sqch_start = 1UL << 0 ,   k_ra8_mipi_dsi_sqch_chsel = 1UL << 23 ,   k_ra8_mipi_dsi_sqch_running = 1UL << 2 ,   k_ra8_mipi_dsi_sqch_aactfin = 1UL << 4 ,   k_ra8_mipi_dsi_sqch_adesfin = 1UL << 8 ,   k_ra8_mipi_dsi_sqch_dabort = 1UL << 16 ,   k_ra8_mipi_dsi_sqch_sizeerr = 1UL << 19 ,   k_ra8_mipi_dsi_sqch_txiberr = 1UL << 24 ,   k_ra8_mipi_dsi_sqch_rxferr = 1UL << 26 ,   k_ra8_mipi_dsi_sqch_rxfail = 1UL << 27 ,   k_ra8_mipi_dsi_sqch_rxpfail = 1UL << 28 ,   k_ra8_mipi_dsi_sqch_rxcorerr = 1UL << 29 ,   k_ra8_mipi_dsi_sqch_rxake = 1UL << 30 ,   k_ra8_mipi_dsi_sqch_clear_all }
	Bit fields for SQCH0SET0R / SQCH1SET0R / SQCH*SR. More...
enum	ra8_mipi_dsi_dsc0a_shift_t : uint8_t {   k_ra8_mipi_dsi_dsc0a_shift_data0 = 0U ,   k_ra8_mipi_dsi_dsc0a_shift_data1 = 8U ,   k_ra8_mipi_dsi_dsc0a_shift_dt = 16U ,   k_ra8_mipi_dsi_dsc0a_shift_vc = 22U ,   k_ra8_mipi_dsi_dsc0a_shift_fmt = 24U ,   k_ra8_mipi_dsi_dsc0a_shift_spd = 25U ,   k_ra8_mipi_dsi_dsc0a_shift_bta = 26U ,   k_ra8_mipi_dsi_dsc0a_shift_nxact = 28U }
	Bit shifts for SQCH*DSC?AR (descriptor word A). More...
enum	ra8_mipi_dsi_dsc0b_t : uint32_t {   k_ra8_mipi_dsi_dsc0b_dtsel_txppd = 0UL << 24 ,   k_ra8_mipi_dsi_dsc0b_dtsel_seqrm = 1UL << 24 }
	SQCH*DSC?BR (descriptor word B) DTSEL field. More...
enum	ra8_mipi_dsi_dsc0c_t : uint32_t {   k_ra8_mipi_dsi_dsc0c_finact = 1UL << 0 ,   k_ra8_mipi_dsi_dsc0c_auxop = 1UL << 22 ,   k_ra8_mipi_dsi_dsc0c_actcode_shift = 24U ,   k_ra8_mipi_dsi_dsc0c_actcode_mask = 0xFFUL << 24 }
	SQCH*DSC?CR (descriptor word C) bit fields. More...
enum	ra8_mipi_dsi_bta_t : uint8_t {   k_ra8_mipi_dsi_bta_none = 0U ,   k_ra8_mipi_dsi_bta_after = 1U ,   k_ra8_mipi_dsi_bta_read = 2U ,   k_ra8_mipi_dsi_bta_no_write = 3U }
	Bus Turn Around (BTA) selector for descriptor word A. More...
enum	ra8_mipi_dsi_reserved_words_t : uint8_t {   k_ra8_mipi_dsi_rsv_words_isr_to_linksr = 3U ,   k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr = 59U ,   k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd = 15U ,   k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr = 36U ,   k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd = 28U ,   k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto = 4U ,   k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr = 5U ,   k_ra8_mipi_dsi_rsv_words_plier_to_vmset = 53U ,   k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0 = 98U ,   k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr = 3U ,   k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1 = 9U ,   k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc = 89U }
	Reserved-word array sizes (in 32-bit words) used by the host register block to keep named offsets aligned with HUM Ch 65. More...
enum	ra8_mipi_dsi_offset_t : uint16_t {   k_ra8_mipi_dsi_offset_akeplatir = 0x220U ,   k_ra8_mipi_dsi_offset_vmppsetr = 0x420U ,   k_ra8_mipi_dsi_offset_sqch0dsc = 0x780U ,   k_ra8_mipi_dsi_offset_sqch1dsc = 0x800U }
	Verified MMIO offsets (in bytes) of select named registers. More...

Functions
static volatile r_mipi_dsi_regs_t *	ra8_mipi_dsi (void)
	Pointer to the RA8D2 MIPI DSI host register block.

Detailed Description

MIPI DSI Host (DSI-2) register layout for the RA8D2.

The RA8D2 MIPI DSI Host module is a MIPI DSI-2 transmitter that pairs with the GLCDC parallel-RGB stream and the on-die D-PHY (1 or 2 lanes, 80-720 Mbps/lane). The block exposes a 0x880-byte window at base 0x40346000 (Secure alias) / 0x50346000 (Non-Secure alias).

This header is the complete register layout for HUM Ch 65 (MIPI DSI, p 3839-3934). Every documented offset is named, and every documented bit field is exposed via a typed enum so the driver code can stay magic-number-free.

Register table (slim summary – bit fields are in dedicated enums below):

Offset	Name	Width	Purpose
0x000	ISR	32	Top-level interrupt status (read-only).
0x010	LINKSR	32	Link status (SQ0/SQ1/VRUN/HSBUSY/LPBUSY).
0x100	TXSETR	32	Number of lanes + clock/data lane enable.
0x104	HSCLKSETR	32	HS clock start + continuous mode select.
0x108	ULPSSETR	32	ULPS wakeup period.
0x10C	ULPSCR	32	ULPS enter/exit pulses (clock + data lanes).
0x110	RSTCR	32	Software reset + force-Tx-stop.
0x114	RSTSR	32	Reset status (HS/LP/APB/AXI/Video, lane stop, lane dir).
0x120	DSISETR	32	DSI link configuration (ECC, CRC, scramble, EoTp, etc).
0x160	TXPPD0..3R	32	Transmit packet payload data 0..15 (4 x 32-bit).
0x200	RXSR	32	Receive status register.
0x204	RXSCR	32	Receive status clear register.
0x208	RXIER	32	Receive interrupt enable.
0x210	PRESPTOBTASETR	32	Peripheral response timeout (BTA).
0x214	PRESPTOLPSETR	32	Peripheral response timeout (LP read/write).
0x218	PRESPTOHSSETR	32	Peripheral response timeout (HS read/write).
0x220	AKEPLATIR	32	Ack-and-error report latest info (RO).
0x224	AKEPACMSR	32	Ack-and-error report accumulated status (RO).
0x228	AKEPSCR	32	Ack-and-error report status clear.
0x230	RXRSSR	32	Receive Result Save status (slot valid bits).
0x234	RXRSSCR	32	Receive Result Save status clear.
0x238	RXRINFOOWSR	32	Receive Result info-overwrite status.
0x23C	RXRINFOOWSCR	32	Receive Result info-overwrite status clear.
0x240	RXRSS0..3R	32	Receive result save slot 0..3 (header captured).
0x2C0	RXPPD0..3R	32	Receive packet payload data (4 x 32-bit, 16 bytes).
0x2E0	HSTXTOSETR	32	HS transmit timeout count.
0x2E4	LRXHTOSETR	32	LP-RX host processor timeout.
0x2E8	TATOSETR	32	Turnaround acknowledge timeout.
0x300	FERRSR/SCR/IER	32	Fatal-error status / clear / enable.
0x314	CLSTPTSETR	32	Clock-lane stop / beforehand / keep timing.
0x318	LPTRNSTSETR	32	LP transition (Go LP and Back) timing.
0x320	PLSR/SCR/IER	32	PHY (PPI) status / clear / enable.
0x400	VMSET0R	32	Video-mode set 0 (HSA/HBP/HFP no-LP, START/STOP).
0x404	VMSET1R	32	Video-mode set 1 (DLY value).
0x410	VMSR/SCR/IER	32	Video-mode status / clear / enable.
0x420	VMPPSETR	32	Video-mode pixel-packet set (TXESYNC, DT, VC).
0x428	VMVSSETR	32	Vertical sync (VSA, VSPOL, VACT).
0x42C	VMVPSETR	32	Vertical porch (VBP, VFP).
0x430	VMHSSETR	32	Horizontal sync (HSA, HSPOL, HACT).
0x434	VMHPSETR	32	Horizontal porch (HBP, HFP).
0x5C0	SQCH0SET0R	32	Sequence channel 0 START bit.
0x5D0	SQCH0SR/SCR/IER	32	Sequence channel 0 status / clear / enable.
0x600	SQCH1SET0R	32	Sequence channel 1 START bit.
0x610	SQCH1SR/SCR/IER	32	Sequence channel 1 status / clear / enable.
0x780	SQCH0DSC0..7	32x4	Sequence ch0 descriptor 0..7 (A/B/C/D each).
0x800	SQCH1DSC0..7	32x4	Sequence ch1 descriptor 0..7 (A/B/C/D each).

Citations: HUM Ch 65 "MIPI DSI" subsections 65.2.1..65.2.140, pages 3839-3934. The struct member offsets and total window size (0x880 bytes) match the FSP R_MIPI_DSI_Type declaration in R7KA8D2KF_core0.h line 54968-61047.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_mipi_dsi_regs.h.

Enumeration Type Documentation

ra8_mipi_dsi_addr_t

enum ra8_mipi_dsi_addr_t : uintptr_t

Memory-mapped base addresses for the MIPI DSI host.

HUM Ch 65.2.1 lists the Secure alias as 0x4034_6000 and the Non-Secure alias as 0x5034_6000. The bare-metal driver always targets the Secure alias.

Enumerator
k_ra8_mipi_dsi_base_addr_s	Secure-world MMIO base.
k_ra8_mipi_dsi_base_addr_ns	Non-Secure alias base.

Definition at line 99 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_akep_t

enum ra8_mipi_dsi_akep_t : uint32_t

Bit fields for AKEPLATIR / AKEPACMSR / AKEPSCR.

HUM Ch 65.2 "Register Description" – AKEPLATIR @ 0x220, AKEPACMSR @ 0x224, AKEPSCR @ 0x228, p 3839-3934. EREP[15:0] is the 16-bit DSI ack/error-report bitmap, VC[19:16] tags the virtual channel that issued the report.

Enumerator
k_ra8_mipi_dsi_akep_erep_mask	16-bit error report.
k_ra8_mipi_dsi_akep_vc_mask	Virtual channel id.

Definition at line 361 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_bta_t

enum ra8_mipi_dsi_bta_t : uint8_t

Bus Turn Around (BTA) selector for descriptor word A.

HUM Ch 65.2 "Register Description" – SQCH0DSC0AR.BTA[27:26]. Mirrors MIPI_DSI_CMD_FLAG_BTA* from the FSP.

Enumerator
k_ra8_mipi_dsi_bta_none	No bus-turnaround.
k_ra8_mipi_dsi_bta_after	BTA after Tx (default ack request).
k_ra8_mipi_dsi_bta_read	BTA followed by read.
k_ra8_mipi_dsi_bta_no_write	Immediate BTA, no write first.

Definition at line 702 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_busy_loop_t

enum ra8_mipi_dsi_busy_loop_t : uint32_t

Bounded poll iteration cap shared by every busy-wait helper.

Honours NASA Power of 10 Rule 2: every loop in the driver has a statically provable upper bound. Tuned so the worst-case wait is still under one ms at 1 GHz Cortex-M85, but small enough that the unit tests on host don't spin meaningfully.

Enumerator
k_ra8_mipi_dsi_busy_loop_max	Max iterations per wait.

Definition at line 128 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_clstpt_t

enum ra8_mipi_dsi_clstpt_t : uint32_t

Bit fields for CLSTPTSETR (clock-lane stop / beforehand / keep).

HUM Ch 65.2 "Register Description" – CLSTPTSETR @ 0x314. CLKSTPT[11:2], CLKBFHT[23:16], CLKKPT[31:24].

Enumerator
k_ra8_mipi_dsi_clstpt_clkstpt_shift	CLKSTPT pos.
k_ra8_mipi_dsi_clstpt_clkstpt_mask	CLKSTPT[11:2].
k_ra8_mipi_dsi_clstpt_clkbfht_shift	CLKBFHT pos.
k_ra8_mipi_dsi_clstpt_clkbfht_mask	CLKBFHT[23:16] mask, sets the LP-to-HS clock guard time.
k_ra8_mipi_dsi_clstpt_clkkpt_shift	CLKKPT pos.
k_ra8_mipi_dsi_clstpt_clkkpt_mask	CLKKPT[31:24] mask, sets the HS-to-LP clock keep time.

Definition at line 556 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_dsc0a_shift_t

enum ra8_mipi_dsi_dsc0a_shift_t : uint8_t

Bit shifts for SQCH*DSC?AR (descriptor word A).

HUM Ch 65.2 "Register Description" – SQCH0DSC0AR @ 0x780. Bit layout: [DATA0:8][DATA1:8][DT:6][VC:2][FMT:1][SPD:1][BTA:2] [NXACT:2][rsvd:2]. Used to assemble a generic DSI short or long packet header in software.

Enumerator
k_ra8_mipi_dsi_dsc0a_shift_data0	Byte 1 of short packet.
k_ra8_mipi_dsi_dsc0a_shift_data1	Byte 2 of short packet.
k_ra8_mipi_dsi_dsc0a_shift_dt	DSI data type (cmd id).
k_ra8_mipi_dsi_dsc0a_shift_vc	Virtual channel.
k_ra8_mipi_dsi_dsc0a_shift_fmt	0 = short packet, 1 = long.
k_ra8_mipi_dsi_dsc0a_shift_spd	0 = HS, 1 = LP escape.
k_ra8_mipi_dsi_dsc0a_shift_bta	Bus Turn Around bits.
k_ra8_mipi_dsi_dsc0a_shift_nxact	Next-action bits.

Definition at line 653 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_dsc0b_t

enum ra8_mipi_dsi_dsc0b_t : uint32_t

SQCH*DSC?BR (descriptor word B) DTSEL field.

HUM Ch 65.2 "Register Description" – SQCH0DSC0BR @ 0x784. DTSEL[25:24]: 0 = TXPPD, 1 = sequence RAM.

Enumerator
k_ra8_mipi_dsi_dsc0b_dtsel_txppd	Use TXPPD0..3R buffer.
k_ra8_mipi_dsi_dsc0b_dtsel_seqrm	Use sequence RAM.

Definition at line 672 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_dsc0c_t

enum ra8_mipi_dsi_dsc0c_t : uint32_t

SQCH*DSC?CR (descriptor word C) bit fields.

HUM Ch 65.2 "Register Description" – SQCH0DSC0CR @ 0x788. FINACT[0], AUXOP[22], ACTCODE[31:24]. AUXOP signals an auxiliary operation (BTA / skew calibration / NOOP); ACTCODE picks the specific aux command.

Enumerator
k_ra8_mipi_dsi_dsc0c_finact	Finish action flag.
k_ra8_mipi_dsi_dsc0c_auxop	Auxiliary op flag.
k_ra8_mipi_dsi_dsc0c_actcode_shift	Action code shift.
k_ra8_mipi_dsi_dsc0c_actcode_mask	ACTCODE[31:24].

Definition at line 687 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_dsisetr_t

enum ra8_mipi_dsi_dsisetr_t : uint32_t

Bit fields for DSISETR (DSI link configuration).

HUM Ch 65.2 "Register Description" – DSISETR @ 0x120, p 3839-3934. MRPSZ[15:0] is the maximum return packet size (set as a value, not a single-bit mask, so it is exposed as a shift).

Enumerator
k_ra8_mipi_dsi_dsisetr_eccen	ECC check enable.
k_ra8_mipi_dsi_dsisetr_vc0crcen	VC-0 CRC check enable.
k_ra8_mipi_dsi_dsisetr_vc1crcen	VC-1 CRC check enable.
k_ra8_mipi_dsi_dsisetr_vc2crcen	VC-2 CRC check enable.
k_ra8_mipi_dsi_dsisetr_vc3crcen	VC-3 CRC check enable.
k_ra8_mipi_dsi_dsisetr_scren	Data scramble enable.
k_ra8_mipi_dsi_dsisetr_extemd	External tearing detect.
k_ra8_mipi_dsi_dsisetr_eotpen	HS Tx EoTp enable.
k_ra8_mipi_dsi_dsisetr_mrpsz_mask	MRPSZ field mask.
k_ra8_mipi_dsi_dsisetr_vc_crc_mask	Mask for the four per-VC CRC enable bits.

Definition at line 260 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_ferrsr_t

enum ra8_mipi_dsi_ferrsr_t : uint32_t

Bit fields for FERRSR / FERRSCR / FERRIER (fatal errors).

HUM Ch 65.2 "Register Description" – FERRSR @ 0x300, FERRSCR @ 0x304, FERRIER @ 0x308, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_ferrsr_htxto	HS Tx timeout.
k_ra8_mipi_dsi_ferrsr_lrxhto	LP-RX host timeout.
k_ra8_mipi_dsi_ferrsr_tato	Turnaround ack timeout.
k_ra8_mipi_dsi_ferrsr_escent	Escape-mode entry error.
k_ra8_mipi_dsi_ferrsr_syncesc	LPDT sync error.
k_ra8_mipi_dsi_ferrsr_ctrl	Control error.
k_ra8_mipi_dsi_ferrsr_clp0	LP0 contention error.
k_ra8_mipi_dsi_ferrsr_clp1	LP1 contention error.
k_ra8_mipi_dsi_ferrsr_clp0s	LP0 contention status (RO).
k_ra8_mipi_dsi_ferrsr_clp1s	LP1 contention status (RO).
k_ra8_mipi_dsi_ferrsr_clear_all	RW1C-able fields in FERRSCR (status-only bits 27/28 excluded).

Definition at line 374 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_hsclk_t

enum ra8_mipi_dsi_hsclk_t : uint32_t

Bit fields for HSCLKSETR.

HUM Ch 65.2 "Register Description" – HSCLKSETR @ 0x104, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_hsclk_start	HSCLST: HS clock start.
k_ra8_mipi_dsi_hsclk_continuous	HSCLMD: continuous mode.

Definition at line 200 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_isr_mask_t

enum ra8_mipi_dsi_isr_mask_t : uint32_t

Bit masks for the top-level Interrupt Status Register (ISR).

HUM Ch 65.2.1 "ISR : Interrupt Status Register" p 3840.

Enumerator
k_ra8_mipi_dsi_isr_sq0	Sequence channel 0 interrupt.
k_ra8_mipi_dsi_isr_sq1	Sequence channel 1 interrupt.
k_ra8_mipi_dsi_isr_vm	Video-mode interrupt.
k_ra8_mipi_dsi_isr_rcv	Receive interrupt.
k_ra8_mipi_dsi_isr_ferr	Fatal-error interrupt.
k_ra8_mipi_dsi_isr_ppi	PPI (D-PHY) interrupt.

Definition at line 154 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_linksr_mask_t

enum ra8_mipi_dsi_linksr_mask_t : uint32_t

Bit masks for the Link Status Register (LINKSR).

HUM Ch 65.2 "Register Description" – LINKSR @ 0x010, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_link_sq0run	Sequence ch 0 running.
k_ra8_mipi_dsi_link_sq1run	Sequence ch 1 running.
k_ra8_mipi_dsi_link_vrun	Video-mode operation running.
k_ra8_mipi_dsi_link_hsbusy	HS operation busy.
k_ra8_mipi_dsi_link_lpbusy	LP operation busy.

Definition at line 170 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_lptrnst_t

enum ra8_mipi_dsi_lptrnst_t : uint32_t

Bit fields for LPTRNSTSETR (LP transition timing).

HUM Ch 65.2 "Register Description" – LPTRNSTSETR @ 0x318. GOLPBKT[9:0].

Enumerator
k_ra8_mipi_dsi_lptrnst_golpbkt_mask	GOLPBKT[9:0].

Definition at line 575 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_offset_t

enum ra8_mipi_dsi_offset_t : uint16_t

Verified MMIO offsets (in bytes) of select named registers.

Used by static_assert declarations below to lock layout to the HUM/FSP register window definition.

Enumerator
k_ra8_mipi_dsi_offset_akeplatir	AKEPLATIR offset.
k_ra8_mipi_dsi_offset_vmppsetr	VMPPSETR offset.
k_ra8_mipi_dsi_offset_sqch0dsc	SQCH0DSC[0] offset.
k_ra8_mipi_dsi_offset_sqch1dsc	SQCH1DSC[0] offset.

Definition at line 758 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_plsr_t

enum ra8_mipi_dsi_plsr_t : uint32_t

Bit fields for PLSR / PLSCR / PLIER (PHY/PPI lane status).

HUM Ch 65.2 "Register Description" – PLSR @ 0x320, PLSCR @ 0x324, PLIER @ 0x328, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_plsr_cluan	CL UlpsActiveNot status.
k_ra8_mipi_dsi_plsr_clstp	CL stop status.
k_ra8_mipi_dsi_plsr_dl0rle	DL0 RxLpdtEsc status.
k_ra8_mipi_dsi_plsr_dl0rue	DL0 RxUlpsEsc status.
k_ra8_mipi_dsi_plsr_dl0uan	DL0 UlpsActiveNot.
k_ra8_mipi_dsi_plsr_dl1uan	DL1 UlpsActiveNot.
k_ra8_mipi_dsi_plsr_dl0stp	DL0 stop status.
k_ra8_mipi_dsi_plsr_dl1stp	DL1 stop status.
k_ra8_mipi_dsi_plsr_dl0rx2tx	DL0 RX-to-TX transition.
k_ra8_mipi_dsi_plsr_dl0tx2rx	DL0 TX-to-RX transition.
k_ra8_mipi_dsi_plsr_dl0dir	DL0 direction.
k_ra8_mipi_dsi_plsr_clulpent	CL ULPS enter event.
k_ra8_mipi_dsi_plsr_clulpext	CL ULPS exit event.
k_ra8_mipi_dsi_plsr_cllp2hs	CL LP-to-HS transition.
k_ra8_mipi_dsi_plsr_clhs2lp	CL HS-to-LP transition.
k_ra8_mipi_dsi_plsr_dlulpent	DL ULPS enter event.
k_ra8_mipi_dsi_plsr_dlulpext	DL ULPS exit event.
k_ra8_mipi_dsi_plsr_clear_all	Bit subset that is RW1C in PLSCR (steady-state lane bits aren't).

Definition at line 398 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_presptohs_t

enum ra8_mipi_dsi_presptohs_t : uint32_t

Bit fields for PRESPTOHSSETR (HS read/write timeouts).

HUM Ch 65.2 "Register Description" – PRESPTOHSSETR @ 0x218. HSWTO[15:0], HSRTO[31:16].

Enumerator
k_ra8_mipi_dsi_presptohs_hswto_mask	HSWTO[15:0].
k_ra8_mipi_dsi_presptohs_hsrto_shift	HSRTO position.
k_ra8_mipi_dsi_presptohs_hsrto_mask	HSRTO[31:16] mask, sets the HS-mode peripheral read timeout.

Definition at line 602 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_presptolp_t

enum ra8_mipi_dsi_presptolp_t : uint32_t

Bit fields for PRESPTOLPSETR (LP read/write timeouts).

HUM Ch 65.2 "Register Description" – PRESPTOLPSETR @ 0x214. LPWTO[15:0], LPRTO[31:16].

Enumerator
k_ra8_mipi_dsi_presptolp_lpwto_mask	LPWTO[15:0].
k_ra8_mipi_dsi_presptolp_lprto_shift	LPRTO position.
k_ra8_mipi_dsi_presptolp_lprto_mask	LPRTO[31:16] mask, sets the LP-mode peripheral read timeout.

Definition at line 587 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_reserved_words_t

enum ra8_mipi_dsi_reserved_words_t : uint8_t

Reserved-word array sizes (in 32-bit words) used by the host register block to keep named offsets aligned with HUM Ch 65.

Each value corresponds to a reserved gap between named registers. Replaces inline magic numbers in the r_mipi_dsi_regs_t struct.

Enumerator
k_ra8_mipi_dsi_rsv_words_isr_to_linksr	+0x004..0x00C gap.
k_ra8_mipi_dsi_rsv_words_linksr_to_txsetr	+0x014..0x0FC gap.
k_ra8_mipi_dsi_rsv_words_dsisetr_to_txppd	+0x124..0x15C gap.
k_ra8_mipi_dsi_rsv_words_txppd_to_rxsr	+0x170..0x1FC gap.
k_ra8_mipi_dsi_rsv_words_rxrss_to_rxppd	+0x250..0x2BC gap.
k_ra8_mipi_dsi_rsv_words_rxppd_to_hstxto	+0x2D0..0x2DC gap.
k_ra8_mipi_dsi_rsv_words_tato_to_ferrsr	+0x2EC..0x2FC gap.
k_ra8_mipi_dsi_rsv_words_plier_to_vmset	+0x32C..0x3FC gap.
k_ra8_mipi_dsi_rsv_words_hsporch_to_sqch0	+0x438..0x5BC gap.
k_ra8_mipi_dsi_rsv_words_sqch0_set0_to_sr	+0x5C4..0x5CC gap.
k_ra8_mipi_dsi_rsv_words_sqch0_ier_to_ch1	+0x5DC..0x5FC gap.
k_ra8_mipi_dsi_rsv_words_sqch1_ier_to_dsc	+0x61C..0x77C gap.

Definition at line 735 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rstcr_t

enum ra8_mipi_dsi_rstcr_t : uint32_t

Bit fields for RSTCR (software reset control).

HUM Ch 65.2 "Register Description" – RSTCR @ 0x110, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_rstcr_swrst	Assert software reset.
k_ra8_mipi_dsi_rstcr_ftxstp	Force Tx stop mode.

Definition at line 226 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rstsr_t

enum ra8_mipi_dsi_rstsr_t : uint32_t

Bit fields for RSTSR (software reset status).

HUM Ch 65.2 "Register Description" – RSTSR @ 0x114, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_rstsr_rsths	HS subsystem in reset.
k_ra8_mipi_dsi_rstsr_rstlp	LP subsystem in reset.
k_ra8_mipi_dsi_rstsr_rstapb	APB bridge in reset.
k_ra8_mipi_dsi_rstsr_rstaxi	AXI bridge in reset.
k_ra8_mipi_dsi_rstsr_rstv	Video subsystem in reset.
k_ra8_mipi_dsi_rstsr_dl0stp	Data lane 0 stopped.
k_ra8_mipi_dsi_rstsr_dl1stp	Data lane 1 stopped.
k_ra8_mipi_dsi_rstsr_dl0dir	Data lane 0 direction.
k_ra8_mipi_dsi_rstsr_all_reset	Composite mask: HS|LP|APB|AXI|V (all 5 reset bits).

Definition at line 238 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rxrinfoowscr_t

enum ra8_mipi_dsi_rxrinfoowscr_t : uint32_t

Bit masks for RXRINFOOWSCR (receive-result info-overwrite clear).

HUM Ch 65.2 "Register Description" – RXRINFOOWSR @ 0x238, RXRINFOOWSCR @ 0x23C.

Enumerator
k_ra8_mipi_dsi_rxrinfoow_sl0	Slot 0 overwrite flag.
k_ra8_mipi_dsi_rxrinfoow_sl1	Slot 1 overwrite flag.
k_ra8_mipi_dsi_rxrinfoow_sl2	Slot 2 overwrite flag.
k_ra8_mipi_dsi_rxrinfoow_sl3	Slot 3 overwrite flag.

Definition at line 140 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rxrss_t

enum ra8_mipi_dsi_rxrss_t : uint32_t

Decoded fields for an RXRSS slot value (header capture).

HUM Ch 65.2 "Register Description" – RXRSS0..3R @ 0x240..0x24C. Each 32-bit slot register packs a captured DSI packet header: DATA0[7:0], DATA1[15:8], DT[21:16], VC[23:22], FMT[24], status flags RXSUC[25], RXFERR[26], RXFAIL[27], RXPFAIL[28], RXCERR[29], RXAKE[30], INFOOW[31].

Enumerator
k_ra8_mipi_dsi_rxrss_data0_mask	DATA0 byte 1 of pkt.
k_ra8_mipi_dsi_rxrss_data1_mask	DATA1 byte 2 of pkt.
k_ra8_mipi_dsi_rxrss_dt_mask	DT data type bits.
k_ra8_mipi_dsi_rxrss_vc_mask	Virtual channel.
k_ra8_mipi_dsi_rxrss_fmt	Long-packet flag.
k_ra8_mipi_dsi_rxrss_rxsuc	Receive success.
k_ra8_mipi_dsi_rxrss_rxferr	Fatal error.
k_ra8_mipi_dsi_rxrss_rxfail	Receive fail.
k_ra8_mipi_dsi_rxrss_rxpfail	Packet data fail.
k_ra8_mipi_dsi_rxrss_rxcerr	Correctable error.
k_ra8_mipi_dsi_rxrss_rxake	Ack/error report.
k_ra8_mipi_dsi_rxrss_infoow	Info overwritten.

Definition at line 336 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rxrssr_t

enum ra8_mipi_dsi_rxrssr_t : uint32_t

Bit fields for RXRSSR / RXRSSCR (receive-result slot valid).

HUM Ch 65.2 "Register Description" – RXRSSR @ 0x230, RXRSSCR @ 0x234.

Enumerator
k_ra8_mipi_dsi_rxrssr_slt0vld	Slot 0 valid flag.
k_ra8_mipi_dsi_rxrssr_slt1vld	Slot 1 valid flag.
k_ra8_mipi_dsi_rxrssr_slt2vld	Slot 2 valid flag.
k_ra8_mipi_dsi_rxrssr_slt3vld	Slot 3 valid flag.

Definition at line 318 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_rxsr_t

enum ra8_mipi_dsi_rxsr_t : uint32_t

Bit fields for RXSR / RXSCR / RXIER (receive status path).

HUM Ch 65.2 "Register Description" – RXSR @ 0x200, RXSCR @ 0x204, RXIER @ 0x208, p 3839-3934. The same layout is used for status (read-only), clear (RW1C), and interrupt enable.

Enumerator
k_ra8_mipi_dsi_rxsr_btarend	BTA request end.
k_ra8_mipi_dsi_rxsr_lrxhto	LP-RX host processor TO.
k_ra8_mipi_dsi_rxsr_tato	Turnaround ack timeout.
k_ra8_mipi_dsi_rxsr_rxresp	Response packet received.
k_ra8_mipi_dsi_rxsr_rxeotp	EoTp received.
k_ra8_mipi_dsi_rxsr_rxte	Tearing-effect trigger rx.
k_ra8_mipi_dsi_rxsr_rxack	ACK trigger received.
k_ra8_mipi_dsi_rxsr_extedet	External TE detect.
k_ra8_mipi_dsi_rxsr_mlferr	Malform error.
k_ra8_mipi_dsi_rxsr_eccerrm	Multi-bit ECC error.
k_ra8_mipi_dsi_rxsr_unexerr	Unexpected packet error.
k_ra8_mipi_dsi_rxsr_wcerr	Word count error.
k_ra8_mipi_dsi_rxsr_crcerr	CRC error.
k_ra8_mipi_dsi_rxsr_iberr	Internal bus error.
k_ra8_mipi_dsi_rxsr_rxovferr	Receive buffer overflow.
k_ra8_mipi_dsi_rxsr_prtoerr	Peripheral resp timeout.
k_ra8_mipi_dsi_rxsr_noreserr	No response error.
k_ra8_mipi_dsi_rxsr_rsizeerr	Return packet size error.
k_ra8_mipi_dsi_rxsr_eccerrs	Single-bit ECC error.
k_ra8_mipi_dsi_rxsr_rxake	Ack-and-error report rx.
k_ra8_mipi_dsi_rxsr_clear_all	Mask of every defined RXSR bit – write to RXSCR to scrub.

Definition at line 283 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_size_t

enum ra8_mipi_dsi_size_t : uint16_t

Window size and key constants for the MIPI DSI block.

Enumerator
k_ra8_mipi_dsi_window_bytes	Total MMIO window (FSP size).
k_ra8_mipi_dsi_max_lanes	D-PHY lane configurations 1/2.
k_ra8_mipi_dsi_payload_max	TXPPD bytes (4 x 32-bit regs).
k_ra8_mipi_dsi_rx_slots	RXRSS0..3 receive slot count.
k_ra8_mipi_dsi_descriptors	8 descriptors per channel.
k_ra8_mipi_dsi_max_lp_bytes	LP (ch 0) max long-pkt size.
k_ra8_mipi_dsi_max_hs_bytes	HS (ch 1) max long-pkt size.

Definition at line 108 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_sqch_t

enum ra8_mipi_dsi_sqch_t : uint32_t

Bit fields for SQCH0SET0R / SQCH1SET0R / SQCH*SR.

HUM Ch 65.2 "Register Description" – SQCH0SET0R @ 0x5C0, SQCH0SR @ 0x5D0, SQCH1SET0R @ 0x600, SQCH1SR @ 0x610. Same layout applies to both channels and to the corresponding SCR / IER registers.

NOTE on SQCH*SET0R: the FSP source emits bit 23 alongside the START bit (SQCHnSET0R_BIT_23 | (n == channel)). That extra bit is the channel select latch. Both bits are exposed here.

Enumerator
k_ra8_mipi_dsi_sqch_start	START: kick sequence.
k_ra8_mipi_dsi_sqch_chsel	Channel-select bit (FSP).
k_ra8_mipi_dsi_sqch_running	RUNNING flag in *SR.
k_ra8_mipi_dsi_sqch_aactfin	AACTFIN: all actions done.
k_ra8_mipi_dsi_sqch_adesfin	ADESFIN: all descriptors.
k_ra8_mipi_dsi_sqch_dabort	DABORT: descriptor abort.
k_ra8_mipi_dsi_sqch_sizeerr	SIZEERR: packet size error.
k_ra8_mipi_dsi_sqch_txiberr	TXIBERR: Tx int-bus error.
k_ra8_mipi_dsi_sqch_rxferr	RXFERR: Rx fatal error.
k_ra8_mipi_dsi_sqch_rxfail	RXFAIL: Rx fail.
k_ra8_mipi_dsi_sqch_rxpfail	RXPFAIL: Rx packet fail.
k_ra8_mipi_dsi_sqch_rxcorerr	RXCORERR: Rx correctable.
k_ra8_mipi_dsi_sqch_rxake	RXAKE: ack/error report rx.
k_ra8_mipi_dsi_sqch_clear_all	Mask of every RW1C bit in SQCH*SCR.

Definition at line 623 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_txset_t

enum ra8_mipi_dsi_txset_t : uint32_t

Bit fields for TXSETR (lane configuration).

HUM Ch 65.2 "Register Description" – TXSETR @ 0x100, p 3839-3934. NUMLANE [1:0] = 0 -> 1 lane, 1 -> 2 lanes.

Enumerator
k_ra8_mipi_dsi_txset_lane1	NUMLANE = 0: 1 data lane.
k_ra8_mipi_dsi_txset_lane2	NUMLANE = 1: 2 data lanes.
k_ra8_mipi_dsi_txset_clen	CLEN: clock-lane enable.
k_ra8_mipi_dsi_txset_dlen	DLEN: data-lane enable.

Definition at line 186 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_ulpscr_t

enum ra8_mipi_dsi_ulpscr_t : uint32_t

Bit fields for ULPSCR.

HUM Ch 65.2 "Register Description" – ULPSCR @ 0x10C, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_ulpscr_clent	Clock-lane ULPS enter.
k_ra8_mipi_dsi_ulpscr_clexit	Clock-lane ULPS exit.
k_ra8_mipi_dsi_ulpscr_dlent	Data-lane ULPS enter.
k_ra8_mipi_dsi_ulpscr_dlexit	Data-lane ULPS exit.

Definition at line 212 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmhpsetr_t

enum ra8_mipi_dsi_vmhpsetr_t : uint32_t

Bit fields for VMHPSETR (horizontal porch timing).

HUM Ch 65.2 "Register Description" – VMHPSETR @ 0x434. HBP[12:0], HFP[28:16].

Enumerator
k_ra8_mipi_dsi_vmhp_hbp_mask	HBP[12:0].
k_ra8_mipi_dsi_vmhp_hfp_shift	HFP shift.
k_ra8_mipi_dsi_vmhp_hfp_mask	HFP[28:16].

Definition at line 542 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmhssetr_t

enum ra8_mipi_dsi_vmhssetr_t : uint32_t

Bit fields for VMHSSETR (horizontal sync timing).

HUM Ch 65.2 "Register Description" – VMHSSETR @ 0x430. HSA[11:0], HSPOL[15], HACT[30:16].

Enumerator
k_ra8_mipi_dsi_vmhs_hsa_mask	HSA[11:0].
k_ra8_mipi_dsi_vmhs_hspol	HSYNC polarity.
k_ra8_mipi_dsi_vmhs_hact_shift	HACT shift.
k_ra8_mipi_dsi_vmhs_hact_mask	HACT[30:16].

Definition at line 527 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmppsetr_t

enum ra8_mipi_dsi_vmppsetr_t : uint32_t

Bit fields for VMPPSETR (video-mode pixel-packet set).

HUM Ch 65.2 "Register Description" – VMPPSETR @ 0x420. TXESYNC[15], DT[21:16], VC[23:22].

Enumerator
k_ra8_mipi_dsi_vmpp_txesync	Transmit end-of-sync.
k_ra8_mipi_dsi_vmpp_dt_shift	DT field position.
k_ra8_mipi_dsi_vmpp_dt_mask	DT[21:16] mask, used to clamp the data-type field.
k_ra8_mipi_dsi_vmpp_vc_shift	VC field position.
k_ra8_mipi_dsi_vmpp_vc_mask	VC[23:22] mask, used to clamp the virtual-channel field.

Definition at line 480 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmset0_t

enum ra8_mipi_dsi_vmset0_t : uint32_t

Bit fields for VMSET0R (video-mode set 0).

HUM Ch 65.2 "Register Description" – VMSET0R @ 0x400, p 3839-3934.

Enumerator
k_ra8_mipi_dsi_vmset0_vstart	VSTART: start video mode.
k_ra8_mipi_dsi_vmset0_vstop	VSTOP : request video stop.
k_ra8_mipi_dsi_vmset0_hsanolp	HSA period stays HS.
k_ra8_mipi_dsi_vmset0_hbpnolp	HBP period stays HS.
k_ra8_mipi_dsi_vmset0_hfpnolp	HFP period stays HS.

Definition at line 428 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmset1_t

enum ra8_mipi_dsi_vmset1_t : uint32_t

Bit fields for VMSET1R (video-mode set 1: pipeline delay).

HUM Ch 65.2 "Register Description" – VMSET1R @ 0x404, p 3839-3934. DLY[13:2] – 12-bit delay value, scaled by 4 by hardware.

Enumerator
k_ra8_mipi_dsi_vmset1_dly_shift	DLY position.
k_ra8_mipi_dsi_vmset1_dly_mask	DLY[13:2] field mask.

Definition at line 444 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmsr_t

enum ra8_mipi_dsi_vmsr_t : uint32_t

Bit fields for VMSR / VMSCR / VMIER.

HUM Ch 65.2 "Register Description" – VMSR @ 0x410, VMSCR @ 0x414, VMIER @ 0x418, p 3839-3934. NOTE the VMSR layout from the FSP shows start[0] / stop[1] / running[2] / virdy[3] but the HUM places RUNNING at bit 0 and VIRDY at bit 4. We follow the HUM (and downstream test fixtures) which use the latter layout.

Enumerator
k_ra8_mipi_dsi_vmsr_running	Video mode running.
k_ra8_mipi_dsi_vmsr_virdy	Video mode ready (started).
k_ra8_mipi_dsi_vmsr_stop	Video mode stopped.
k_ra8_mipi_dsi_vmsr_timerr	Timing error.
k_ra8_mipi_dsi_vmsr_vbufudf	Video buffer underflow.
k_ra8_mipi_dsi_vmsr_vbufovf	Video buffer overflow.
k_ra8_mipi_dsi_vmsr_clear_all	Mask of every defined VMSR bit – write to VMSCR to scrub.

Definition at line 460 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmvpsetr_t

enum ra8_mipi_dsi_vmvpsetr_t : uint32_t

Bit fields for VMVPSETR (vertical porch timing).

HUM Ch 65.2 "Register Description" – VMVPSETR @ 0x42C. VBP[12:0], VFP[28:16].

Enumerator
k_ra8_mipi_dsi_vmvp_vbp_mask	VBP[12:0].
k_ra8_mipi_dsi_vmvp_vfp_shift	VFP shift.
k_ra8_mipi_dsi_vmvp_vfp_mask	VFP[28:16].

Definition at line 513 of file ra8_mipi_dsi_regs.h.

ra8_mipi_dsi_vmvssetr_t

enum ra8_mipi_dsi_vmvssetr_t : uint32_t

Bit fields for VMVSSETR (vertical sync timing).

HUM Ch 65.2 "Register Description" – VMVSSETR @ 0x428. VSA[11:0], VSPOL[15], VACT[30:16].

Enumerator
k_ra8_mipi_dsi_vmvs_vsa_mask	VSA[11:0].
k_ra8_mipi_dsi_vmvs_vspol	VSYNC polarity.
k_ra8_mipi_dsi_vmvs_vact_shift	VACT shift.
k_ra8_mipi_dsi_vmvs_vact_mask	VACT[30:16].

Definition at line 498 of file ra8_mipi_dsi_regs.h.

Function Documentation

ra8_mipi_dsi()

volatile r_mipi_dsi_regs_t * ra8_mipi_dsi ( void )

inlinestatic

Pointer to the RA8D2 MIPI DSI host register block.

Always returns the Secure-world alias. In RA8_OFF_TARGET the host test harness has already mmap'd the peripheral window so this pointer is dereferenceable.

Precondition

Caller has called ra8_mstp_enable(k_ra8_mstp_mipi_dsi) first (or this is the call site doing it).

The peripheral bus clock is running.

Postcondition

Returned pointer is non-NULL and aligned to 32 bits.

Returned pointer is volatile-qualified.

Returns

Volatile pointer to the MIPI DSI register block.

Note

Thread-safety: returned pointer is shared, all accesses go to the same physical block; the driver serialises register I/O.

See also

ra8_mipi_dsi_init

Since

0.1.0

Definition at line 917 of file ra8_mipi_dsi_regs.h.

References k_ra8_mipi_dsi_base_addr_s.

Referenced by internal_check_link_state(), internal_program_link(), internal_program_timeouts(), internal_ra8_mipi_dsi_clear_all_status(), internal_ra8_mipi_dsi_pulse_start(), internal_ra8_mipi_dsi_stage_payload(), internal_send_stage_and_pulse(), ra8_mipi_dsi_ack_error_get(), ra8_mipi_dsi_clear_status(), ra8_mipi_dsi_deinit(), ra8_mipi_dsi_dispatch(), ra8_mipi_dsi_dispatch_fatal(), ra8_mipi_dsi_dispatch_phy(), ra8_mipi_dsi_dispatch_receive(), ra8_mipi_dsi_dispatch_seq0(), ra8_mipi_dsi_dispatch_seq1(), ra8_mipi_dsi_dispatch_video(), ra8_mipi_dsi_get_status(), ra8_mipi_dsi_hs_clock_start(), ra8_mipi_dsi_hs_clock_stop(), ra8_mipi_dsi_irq_enable(), ra8_mipi_dsi_link_status_get(), ra8_mipi_dsi_rx_payload_read(), ra8_mipi_dsi_rx_result_get(), ra8_mipi_dsi_soft_reset(), ra8_mipi_dsi_te_event_clear(), ra8_mipi_dsi_te_event_pending(), ra8_mipi_dsi_ulps_enter(), ra8_mipi_dsi_ulps_exit(), ra8_mipi_dsi_video_configure(), ra8_mipi_dsi_video_start(), and ra8_mipi_dsi_video_stop().