EK-RA8D2 BSP – MIPI-DSI panel + J-Link VCOM serial bring-up. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_board_ek_ra8d2_internal.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_mipi_dsi.h"
#include "ra8_mipi_phy.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_sci.h"
#include "ra8_time_constants.h"

Include dependency graph for ra8_board_ek_ra8d2_comms.c:

Enumerations
enum	ra8_board_mipi_panel_geometry_t : uint16_t { k_ra8_board_mipi_panel_h_active = 480U , k_ra8_board_mipi_panel_v_active = 854U , k_ra8_board_mipi_panel_line_rate_mbps = 480U }
	Static placeholder geometry + line rate for the J32 panel. More...
enum	ra8_board_uart_console_clock_t : uint32_t { k_ra8_board_uart_console_min_pclka_hz }
	Minimum SCI module operating clock accepted by the console init. More...

Functions
ra8_err_t	ra8_board_clocks_init (ra8_board_clock_rates_t *out_rates)
	Initialize the board-standard PLL1 clock tree and publish its rates.
ra8_err_t	ra8_board_mipi_dsi_init (void)
	Bring the MIPI-DSI link up (PHY + DSI controller).
ra8_err_t	ra8_board_uart_console_init (uint32_t baud)
	Configure SCI8 + PD02/PD03 as the debug-console UART.
ra8_err_t	ra8_board_uart_console_write (const uint8_t *data, size_t len)
	Polled blocking write to the J-Link OB VCOM console.
ra8_err_t	ra8_board_uart_console_read (uint8_t out, size_t cap, size_t out_len)
	Polled non-blocking read from the J-Link OB VCOM console.
bool	priv_ra8_board_uart_console_is_up (void)
	Implementation of priv_ra8_board_uart_console_is_up() – reads the same flag the write / read / flush entry points below consult.
ra8_err_t	ra8_board_uart_console_flush (void)
	Block until every byte queued on the J-Link OB VCOM console has finished clocking out on the wire.

Variables
static const ra8_mipi_dsi_config_t	s_mipi_panel_cfg
	MIPI DSI host link-layer config for the J32 mezzanine.
static const ra8_mipi_phy_timing_t	s_mipi_phy_timing_placeholder
	Placeholder D-PHY HS/LP transition timing block.
static const ra8_mipi_phy_config_t	s_mipi_phy_cfg
	MIPI D-PHY config for the J32 mezzanine.
static bool	s_uart_console_initialized = false
	Tracks whether ra8_board_uart_console_init has succeeded.

Detailed Description

EK-RA8D2 BSP – MIPI-DSI panel + J-Link VCOM serial bring-up.

Tag: [Ring 5 / BSP] {World: S}

Sibling translation unit of ra8_board_ek_ra8d2.c carrying the two display/serial communication links the EK-RA8D2 exposes:

The J32 MIPI-DSI mezzanine (Renesas RTKMIPILCDB00000BE) panel bring-up (PHY -> DSI host -> HS clock start).
The on-board J-Link OB VCOM serial bridge over SCI8 (TXD8/RXD8).

Like the primary unit, the BSP itself never touches MCU registers; ra8_mipi_* / ra8_sci_* / ra8_pfs_route_peripheral carry every register write. Source-of-truth for the pin tables is docs/reference/ek-ra8d2-v1-users-manual.pdf (R20UT5523EG0101 Rev 1.01, October 2025).

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file ra8_board_ek_ra8d2_comms.c.

Enumeration Type Documentation

◆ ra8_board_mipi_panel_geometry_t

enum ra8_board_mipi_panel_geometry_t : uint16_t

Static placeholder geometry + line rate for the J32 panel.

The Renesas MIPI Graphics Expansion Board (RTKMIPILCDB00000BE) carries a Focus-LCD E45RA-MW276-C 480 x 854 panel driven over a 2-lane D-PHY link. The exact per-lane bit rate is panel-vendor information; the placeholder 480 Mbps/lane lands in the HAL's PMUL=1/4 band so the PLL coefficient block below is at least self-consistent at compile time.

TODO(panel-datasheet): replace these three values with the row from the RTKMIPILCDB00000BE / Focus E45RA-MW276-C datasheet.

Enumerator
k_ra8_board_mipi_panel_h_active	RA8 board mipi panel h active.
k_ra8_board_mipi_panel_v_active	RA8 board mipi panel v active.
k_ra8_board_mipi_panel_line_rate_mbps	RA8 board mipi panel line rate mbps.

Definition at line 92 of file ra8_board_ek_ra8d2_comms.c.

◆ ra8_board_uart_console_clock_t

enum ra8_board_uart_console_clock_t : uint32_t

Minimum SCI module operating clock accepted by the console init.

The RA8D2 SCI_B peripheral takes its baud-rate generator clock from PCLKA (chip HUM Ch 38.2 "SCI registers" – the SCI module operating clock is the high-speed peripheral clock PCLKA, NOT PCLKB as some lower-end RA chips). After ra8_cgc_init() brings PLL1 up, PCLKA = PLL1P/8 = 125 MHz on this project's CGC tree (k_ra8_pclka_hz in ra8_time_constants.h). Before that, the chip sits on MOCO (~8 MHz), which is far too low for a usable 115200 baud BRR – so the console init refuses to come up until CGC has published a post-PLL PCLKA value. This minimum is set well above MOCO and well below the 125 MHz target so a different CGC tree can still bring the console up as long as PCLKA is in a reasonable UART range.

Enumerator
k_ra8_board_uart_console_min_pclka_hz	RA8 board UART console minimum pclka Hz.

Definition at line 235 of file ra8_board_ek_ra8d2_comms.c.

Function Documentation

◆ priv_ra8_board_uart_console_is_up()

bool priv_ra8_board_uart_console_is_up ( void )

nodiscard

Implementation of priv_ra8_board_uart_console_is_up() – reads the same flag the write / read / flush entry points below consult.

Report whether ra8_board_uart_console_init has succeeded.

Definition at line 343 of file ra8_board_ek_ra8d2_comms.c.

References RA8_PRIV, and s_uart_console_initialized.

Referenced by ra8_board_console_stream().

◆ ra8_board_clocks_init()

ra8_err_t ra8_board_clocks_init ( ra8_board_clock_rates_t * out_rates )

nodiscard

Initialize the board-standard PLL1 clock tree and publish its rates.

Initialize the standard EK-RA8D2 clock tree and return its rates.

Delegates the register-level transition to the CGC HAL, then returns the board-qualified CPUCLK0 and PCLKA constants without exposing a concrete clock driver to application code.

Parameters

[out] out_rates Initialized board clock rates.

Returns: Board clock initialization status.

Return values

k_ra8_ok	Clock initialization and rate publication succeeded.
k_ra8_err_invalid_arg	`out_rates` is null.
other	Propagated clock-generator initialization error.

Precondition: Called from the single-threaded board boot path.

Postcondition: On success, PLL1 supplies the standard EK-RA8D2 clock tree.; On failure, out_rates is unchanged when nonnull.

Note: Not thread-safe; call once during board initialization.

Since: 0.1.0

Definition at line 58 of file ra8_board_ek_ra8d2_comms.c.

References k_ra8_cpuclk0_hz, k_ra8_err_invalid_arg, k_ra8_ok, k_ra8_pclka_hz, and ra8_cgc_init().

Referenced by internal_c6_cam_setup_or_halt(), internal_setup_or_halt(), and pdm_demo_clocks_or_halt().

◆ ra8_board_mipi_dsi_init()

ra8_err_t ra8_board_mipi_dsi_init ( void )

nodiscard

Bring the MIPI-DSI link up (PHY + DSI controller).

Return values

k_ra8_ok / k_ra8_err_not_supported (until MIPI-DSI HAL lands)

Since: 0.1.0

Definition at line 173 of file ra8_board_ek_ra8d2_comms.c.

References k_ra8_ok, ra8_mipi_dsi_hs_clock_start(), ra8_mipi_dsi_init(), ra8_mipi_phy_init(), s_mipi_panel_cfg, and s_mipi_phy_cfg.

◆ ra8_board_uart_console_flush()

ra8_err_t ra8_board_uart_console_flush ( void )

nodiscard

Block until every byte queued on the J-Link OB VCOM console has finished clocking out on the wire.

Block until every byte queued on the console has clocked out.

Thin wrapper around ra8_sci_flush(k_ra8_board_uart_console_sci_channel) that polls CSR.TEND on the SCI8 channel that backs the J-Link OB VCOM bridge (HUM Ch 38.2.17 "CSR : Common Status Register", p 2225). The intended caller is a panic-handler that needs the failure log to reach the host before WFI gates the SCI clock and silently drops the remaining FIFO contents.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	TEND observed (or fake stub).
k_ra8_err_not_initialized	ra8_board_uart_console_init not called.
k_ra8_err_hw_timeout	Spin budget elapsed without TEND.

Precondition: ra8_board_uart_console_init succeeded.

Postcondition: On success, every byte previously passed to ra8_board_uart_console_write has been transmitted.

Note: Not thread-safe with respect to a concurrent ra8_board_uart_console_write – the writer may refill the shift register while the flush is polling.

See also: ra8_sci_flush; ra8_board_uart_console_write

Since: 0.1.0

Definition at line 348 of file ra8_board_ek_ra8d2_comms.c.

◆ ra8_board_uart_console_init()

ra8_err_t ra8_board_uart_console_init ( uint32_t baud )

nodiscard

Configure SCI8 + PD02/PD03 as the debug-console UART.

Routes PD02 -> TXD8 and PD03 -> RXD8 (PSEL = SCI async) and brings SCI8 up via ra8_sci_init with 8N1 framing at the requested baud. The SCI module operating clock on RA8D2 is PCLKA (chip HUM Ch 38.2 "SCI registers"); the BRR divisor is computed from the current PCLKA frequency reported by ra8_cgc_get_clock_hz, so callers must call ra8_cgc_init() before ra8_board_uart_console_init. Applications that retune CGC afterwards must additionally call ra8_sci_set_baud((uint8_t)k_ra8_board_uart_console_sci_channel, baud, new_pclka_hz) to recompute the divisor.

Parameters

[in] baud Target line rate in bps (e.g. 115200).

Return values

k_ra8_ok	Console up, ready to TX/RX.
k_ra8_err_invalid_arg	baud == 0.
k_ra8_err_not_initialized	ra8_cgc_init has not yet published a usable PCLKA value (chip still on MOCO / pre-PLL).
k_ra8_err_gpio_conflict	PD02 or PD03 already owned.
k_ra8_err_hw_init_failed	Underlying ra8_sci_init failed.

Precondition: HAL pin validator initialized (single-threaded boot context).; ra8_cgc_init() has run and PCLKA is post-PLL.; ra8_mstp_init() has run.

Postcondition: SCI8 is enabled with TE=RE=1; PD02/PD03 are routed to SCI8.; BRR computed against the live PCLKA value (no hardcoded clock).

Note: Not thread-safe; call once during board bring-up.

Since: 0.1.0

Definition at line 240 of file ra8_board_ek_ra8d2_comms.c.

◆ ra8_board_uart_console_read()

ra8_err_t ra8_board_uart_console_read	(	uint8_t *	out,
		size_t	cap,
		size_t *	out_len )

nodiscard

Polled non-blocking read from the J-Link OB VCOM console.

Polled non-blocking read from the debug VCOM console.

Drains up to cap bytes from SCI8 RDR while RDRF stays set. Stops (without error) the first time RDRF clears so the call never blocks waiting for a host that is silent.

Parameters

[out]	out	Destination buffer (non-NULL when cap > 0).
[in]	cap	Capacity of out in bytes.
[out]	out_len	Number of bytes actually read; non-NULL.

Return values

k_ra8_ok	Read complete; *out_len in [0, cap].
k_ra8_err_invalid_arg	out / out_len NULL with non-zero cap.
k_ra8_err_not_initialized	Console not initialized.

Precondition: ra8_board_uart_console_init succeeded.

Postcondition: 0 <= *out_len <= cap.

Since: 0.1.0

Definition at line 308 of file ra8_board_ek_ra8d2_comms.c.

◆ ra8_board_uart_console_write()

ra8_err_t ra8_board_uart_console_write	(	const uint8_t *	data,
		size_t	len )

nodiscard

Polled blocking write to the J-Link OB VCOM console.

Polled blocking write to the debug VCOM console.

Parameters

[in]	data	Bytes to transmit; must be non-NULL when len > 0.
[in]	len	Number of bytes in data.

Return values

k_ra8_ok	All bytes pushed to TDR.
k_ra8_err_invalid_arg	data NULL with non-zero len.
k_ra8_err_not_initialized	ra8_board_uart_console_init not called.

Precondition: ra8_board_uart_console_init succeeded.

Postcondition: All len bytes have been handed to the SCI8 TDR shift register.

Since: 0.1.0

Definition at line 294 of file ra8_board_ek_ra8d2_comms.c.

Variable Documentation

◆ s_mipi_panel_cfg

const ra8_mipi_dsi_config_t s_mipi_panel_cfg

static

Initial value:

                                                    = {
  .lane_count             = k_ra8_mipi_dsi_lanes_2,
  .clock_mode             = k_ra8_mipi_dsi_clock_non_continuous,
  .max_return_packet_size = 16U,
  .ulps_wakeup_period     = 0U,
  .ecc_check_enable       = true,
  .eotp_enable            = true,
  .scramble_enable        = false,
  .tearing_detect_enable  = true,
  .crc_check_vc_mask      = 0x01U, 
  .timing                 = {},    
  .timeouts               = {},    
}

MIPI DSI host link-layer config for the J32 mezzanine.

Only fields whose values come from the SoC side (lane count, ECC / EoTP defaults, ULPS wake-up) are filled in here. The guard-band timing block and bus timeouts are left at the driver power-on defaults until the panel datasheet pins down concrete numbers.

TODO(panel-datasheet): populate timing (CLSTPTSETR / LPTRNSTSETR) and timeouts (HSTXTOSETR, LRXHTOSETR, TATOSETR, PRESPTO*SETR) from the panel datasheet – the empty-init values below are accepted by the driver but produce conservative blanking that may not meet the panel's minimum HSA / HBP / HFP windows.

Definition at line 113 of file ra8_board_ek_ra8d2_comms.c.

Referenced by ra8_board_mipi_dsi_init().

◆ s_mipi_phy_cfg

const ra8_mipi_phy_config_t s_mipi_phy_cfg

static

Initial value:

                                                  = {
  .mode           = k_ra8_mipi_phy_mode_dsi_host,
  .pclka_mhz      = k_panel_pclka_mhz,
  .line_rate_mbps = (uint16_t)k_ra8_board_mipi_panel_line_rate_mbps,
  .lane_count     = k_ra8_mipi_phy_lane_count_2,
  .clk_mode       = k_ra8_mipi_phy_clk_noncontinuous,
  .eotp           = k_ra8_mipi_phy_eotp_enabled,
  .pll =
    {
      .idiv     = k_ra8_mipi_phy_idiv_1,
      .pmul     = k_ra8_mipi_phy_pmul_4,
      .nfmul    = k_ra8_mipi_phy_nfmul_0_00,
      .nmul_int = k_panel_pll_nmul, 
    },
  .escdiv   = 0U,
  .p_timing = &s_mipi_phy_timing_placeholder,
}

MIPI D-PHY config for the J32 mezzanine.

PLL coefficients solve f = MOSC * (1/IDIV) * (NMUL+NFMUL) * (1/PMUL); the placeholder values below assume MOSC=20 MHz and target 240 MHz PLL out (480 Mbps/lane line rate, P=1/4 band).

TODO(panel-datasheet): re-solve once the panel datasheet pins the line rate down and the actual MOSC frequency on the EK-RA8D2 board is confirmed; today's pclka_mhz=60 assumes the chip's CGC reset default.

Definition at line 155 of file ra8_board_ek_ra8d2_comms.c.

Referenced by ra8_board_mipi_dsi_init().

◆ s_mipi_phy_timing_placeholder

const ra8_mipi_phy_timing_t s_mipi_phy_timing_placeholder

static

Initial value:

                                                                 = {
  .tinit = 1U,
}

Placeholder D-PHY HS/LP transition timing block.

The HAL exposes ra8_mipi_phy_select_timing to look the right DPHYTIM1..6 row up automatically; using it would be the right move once the line rate is locked. The placeholder below carries a single non-zero TINIT so the gap is obvious in a debugger.

TODO(panel-datasheet): swap for a ra8_mipi_phy_select_timing lookup keyed on the confirmed panel line rate.

Definition at line 139 of file ra8_board_ek_ra8d2_comms.c.

◆ s_uart_console_initialized

bool s_uart_console_initialized = false

static

Tracks whether ra8_board_uart_console_init has succeeded.

Set to true after ra8_sci_init returns ok and the PFS routes are programmed. The write/read helpers refuse to forward to ra8_sci when this flag is false so callers cannot accidentally drive an unconfigured channel.

Definition at line 217 of file ra8_board_ek_ra8d2_comms.c.

Referenced by priv_ra8_board_uart_console_is_up(), ra8_board_uart_console_flush(), ra8_board_uart_console_init(), ra8_board_uart_console_read(), and ra8_board_uart_console_write().

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ ra8_board_mipi_panel_geometry_t

◆ ra8_board_uart_console_clock_t

Function Documentation

◆ priv_ra8_board_uart_console_is_up()

◆ ra8_board_clocks_init()

◆ ra8_board_mipi_dsi_init()

◆ ra8_board_uart_console_flush()

◆ ra8_board_uart_console_init()

◆ ra8_board_uart_console_read()

◆ ra8_board_uart_console_write()

Variable Documentation

◆ s_mipi_panel_cfg

◆ s_mipi_phy_cfg

◆ s_mipi_phy_timing_placeholder

◆ s_uart_console_initialized