ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_cgc.h
Go to the documentation of this file.
1
16
17#pragma once
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include "ra8_cgc_regs.h"
24#include "ra8_err.h"
25
47[[nodiscard]] ra8_err_t ra8_cgc_init(void);
48
63[[nodiscard]] ra8_err_t ra8_cgc_use_hoco(void);
64
81
98[[nodiscard]] ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t* out_hz);
99
100/* =============================================================================
101 * runtime reconfigure + oscillation-stop interrupt
102 * =============================================================================
103 */
104
114typedef void (*ra8_cgc_ostd_fn_t)(void* ctx);
115
152[[nodiscard]] ra8_err_t ra8_cgc_switch_pll1_target(uint32_t new_cpuclk_hz);
153
178[[nodiscard]] ra8_err_t ra8_cgc_enable_stop_detection(ra8_cgc_ostd_fn_t handler, void* ctx);
179
193[[nodiscard]] ra8_err_t ra8_cgc_disable_stop_detection(void);
194
232[[nodiscard]] ra8_err_t ra8_cgc_usbhs_pll_enable(void);
233
283[[nodiscard]] ra8_err_t ra8_cgc_eswclk_init(void);
284
307[[nodiscard]] ra8_err_t ra8_cgc_eswclk_hz(uint32_t* out_hz);
308
369[[nodiscard]] ra8_err_t
370ra8_cgc_pll2_enable(uint8_t mul_int, uint8_t mul_quarters, ra8_plodiv_t p_div_code);
371
430[[nodiscard]] ra8_err_t ra8_cgc_usbfs_clock_enable(void);
431
452
453#ifdef __cplusplus
454}
455#endif
ra8_err_t ra8_cgc_eswclk_hz(uint32_t *out_hz)
Query the current ESWCLK (Ethernet Switch clock) frequency.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
ra8_err_t ra8_cgc_pll2_enable(uint8_t mul_int, uint8_t mul_quarters, ra8_plodiv_t p_div_code)
Bring up PLL2 with caller-supplied multiplier and P divider.
void ra8_cgc_fake_trigger_stop_detection(void)
Test helper: invoke the registered OSTD callback.
Definition ra8_cgc.c:883
ra8_err_t ra8_cgc_disable_stop_detection(void)
Disable oscillation-stop detection.
Definition ra8_cgc.c:874
ra8_err_t ra8_cgc_use_hoco(void)
Switch the system clock source to HOCO (20 MHz).
Definition ra8_cgc.c:763
ra8_err_t ra8_cgc_eswclk_init(void)
Bring up the Ethernet Switch Module (ESWM / RMAC) clock.
ra8_clock_id_t
Identifiers for the clock-tree frequencies queryable at runtime.
Definition ra8_cgc.h:69
@ k_ra8_clock_id_pclkc
PCLKC.
Definition ra8_cgc.h:75
@ k_ra8_clock_id_fclk
Flash/MRAM interface clock.
Definition ra8_cgc.h:78
@ k_ra8_clock_id_cpuclk1
Cortex-M33 CPUCLK1.
Definition ra8_cgc.h:71
@ k_ra8_clock_id_pclkd
PCLKD.
Definition ra8_cgc.h:76
@ k_ra8_clock_id_pclkb
PCLKB.
Definition ra8_cgc.h:74
@ k_ra8_clock_id_pclke
PCLKE.
Definition ra8_cgc.h:77
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
Definition ra8_cgc.h:70
@ k_ra8_clock_id_mriclk
MRAM bus clock.
Definition ra8_cgc.h:79
@ k_ra8_clock_id_pclka
PCLKA.
Definition ra8_cgc.h:73
@ k_ra8_clock_id_iclk
System ICLK.
Definition ra8_cgc.h:72
void(* ra8_cgc_ostd_fn_t)(void *ctx)
Oscillation-stop-detection callback.
Definition ra8_cgc.h:114
ra8_err_t ra8_cgc_enable_stop_detection(ra8_cgc_ostd_fn_t handler, void *ctx)
Enable oscillation-stop detection on the main crystal.
Definition ra8_cgc.c:857
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
ra8_err_t ra8_cgc_usbfs_clock_enable(void)
Bring up the USB-FS module clock (USBCKCR / USBCKDIVCR).
ra8_err_t ra8_cgc_usbhs_pll_enable(void)
Bring up the USBHS PHY reference clock + module clock.
ra8_err_t ra8_cgc_switch_pll1_target(uint32_t new_cpuclk_hz)
Retune PLL1 to a new CPUCLK0 target without a full deinit.
Definition ra8_cgc.c:814
Clock Generation Circuit (CGC) field layouts for the Renesas RA8D2.
ra8_plodiv_t
PLL output divider codes for PLODIVP/Q/R fields in PLLCCR2.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546