ra8_cgc_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* =============================================================================
 * SCKDIVCR (System Clock Division Control Register) bit fields
 * =============================================================================
 *
 * SCKDIVCR is 32 bits wide. Each nibble selects a divider for one of
 * the clock domains. The divider code-to-ratio map below comes from
 * HUM section 10.2.2.
 */

typedef enum : uint8_t {
  k_ra8_sckdivcr_pckd_shift = 0U,  
  k_ra8_sckdivcr_pckc_shift = 4U,  
  k_ra8_sckdivcr_pckb_shift = 8U,  
  k_ra8_sckdivcr_pcka_shift = 12U, 
  k_ra8_sckdivcr_bck_shift  = 16U, 
  k_ra8_sckdivcr_pcke_shift = 20U, 
  k_ra8_sckdivcr_ick_shift  = 24U, 
  k_ra8_sckdivcr_fck_shift  = 28U, 
} ra8_sckdivcr_shift_t;

typedef enum : uint8_t {
  k_ra8_clock_div_1  = 0x0U, 
  k_ra8_clock_div_2  = 0x1U, 
  k_ra8_clock_div_4  = 0x2U, 
  k_ra8_clock_div_8  = 0x3U, 
  k_ra8_clock_div_16 = 0x4U, 
  k_ra8_clock_div_32 = 0x5U, 
  k_ra8_clock_div_64 = 0x6U, 
} ra8_clock_div_t;
 
/* =============================================================================
 * SCKDIVCR2 bit fields (CPU clocks + MRAM clock)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sckdivcr2_cpuclk0_shift = 0U,  
  k_ra8_sckdivcr2_cpuclk1_shift = 4U,  
  k_ra8_sckdivcr2_npuclk_shift  = 8U,  
  k_ra8_sckdivcr2_mriclk_shift  = 12U, 
} ra8_sckdivcr2_shift_t;
 
/* =============================================================================
 * SCKSCR (System Clock Source Control Register)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_cksel_hoco  = 0U, 
  k_ra8_cksel_moco  = 1U, 
  k_ra8_cksel_loco  = 2U, 
  k_ra8_cksel_main  = 3U, 
  k_ra8_cksel_subck = 4U, 
  k_ra8_cksel_pll1  = 5U, 
  k_ra8_cksel_pll2  = 6U, 
} ra8_cksel_t;
 
/* =============================================================================
 * PLLCCR (PLL1 Clock Control Register) -- RA8D2 layout
 * =============================================================================
 *
 * Cited from FSP CMSIS device header `R7KA8D2KF_core0.h` and
 * FSP `bsp_clocks.c`:
 *   - PLIDIV   [1:0]  -- input divider code
 *                       (0=/1, 1=/2, 2=/3, 3=/4, ... ratio = code+1 for /1../6)
 *   - PLSRCSEL [4]    -- PLL input source (0 = Main / XTAL, 1 = HOCO)
 *   - PLLMULNF [7:6]  -- fractional multiplier in 0.25 steps
 *   - PLLMUL   [16:8] -- integer multiplier (9 bits, 1..511)
 *
 * Composite multiplier = PLLMUL + (PLLMULNF / 4). FSP packs the value
 * as `(integer_mul * 4 + fraction_quarters) << 6`, which puts the
 * integer part in [16:8] and the fraction in [7:6] simultaneously.
 *
 * For the EK-RA8D2 quickstart target (XTAL=24 MHz, /3 in, x250.00,
 * P=/2, Q=/6, R=/5): PLLCCR = 0xFA02.
 */

typedef enum : uint8_t {
  k_ra8_pllccr_shift_plidiv   = 0U, 
  k_ra8_pllccr_shift_plsrcsel = 4U, 
  k_ra8_pllccr_shift_quarters = 6U, 
} ra8_pllccr_shift_t;

typedef enum : uint32_t {
  k_ra8_pllccr_mask_plidiv   = 0x00000003UL, 
  k_ra8_pllccr_mask_quarters = 0x000007FFUL, 
} ra8_pllccr_mask_t;

typedef enum : uint8_t {
  k_ra8_plidiv_div1 = 0U, 
  k_ra8_plidiv_div2 = 1U, 
  k_ra8_plidiv_div3 = 2U, 
} ra8_plidiv_t;

typedef enum : uint8_t {
  k_ra8_plsrcsel_main = 0U, 
  k_ra8_plsrcsel_hoco = 1U, 
} ra8_plsrcsel_t;
 
/* =============================================================================
 * PLLCCR2 (PLL1 Output Divider Register) -- RA8D2 layout
 * =============================================================================
 *
 * Cited from FSP CMSIS device header `R7KA8D2KF_core0.h` and
 * FSP `bsp_clocks.c`:
 *   - PLODIVP [3:0]   -- PLL1P output divider code
 *   - PLODIVQ [7:4]   -- PLL1Q output divider code
 *   - PLODIVR [11:8]  -- PLL1R output divider code
 *
 * Code-to-ratio map matches FSP `BSP_CLOCKS_PLL_DIV_*`:
 *   /1=0, /2=1, /3=2, /4=3, /5=4, /6=5, /8=7, /9=8, /16=15.
 * For ratios 1..6 the code is `ratio - 1`; /7 is not supported.
 *
 * Quickstart EK-RA8D2: P=/2 (1), Q=/6 (5), R=/5 (4) -> PLLCCR2 = 0x451.
 */

typedef enum : uint8_t {
  k_ra8_pllccr2_shift_plodivp = 0U, 
  k_ra8_pllccr2_shift_plodivq = 4U, 
  k_ra8_pllccr2_shift_plodivr = 8U, 
} ra8_pllccr2_shift_t;

typedef enum : uint8_t {
  k_ra8_plodiv_div2  = 1U,  
  k_ra8_plodiv_div3  = 2U,  
  k_ra8_plodiv_div4  = 3U,  
  k_ra8_plodiv_div5  = 4U,  
  k_ra8_plodiv_div6  = 5U,  
  k_ra8_plodiv_div8  = 7U,  
  k_ra8_plodiv_div9  = 8U,  
  k_ra8_plodiv_div16 = 15U, 
} ra8_plodiv_t;
 
/* =============================================================================
 * PLL2CCR / PLL2CR / PLL2CCR2 -- PLL2 register encodings
 * =============================================================================
 *
 * PLL2 has the same field layout as PLL1 except the multiplier is 8 bits
 * (vs 9 for PLL1) and the register width is 16 bits (vs 32). The shifts
 * and the (mul*4 + quarters) packing trick are identical, so we reuse
 * `k_ra8_pllccr_shift_*`, `k_ra8_plidiv_*`, `k_ra8_plsrcsel_*` and
 * `k_ra8_plodiv_*` from above and only add what is unique to PLL2:
 *
 *   - PLL2CR.PLL2STP at bit 0 (write 1 = stop, 0 = run).
 *   - PLL2MUL is 8 bits (1..255), still encoded as `mul * 4 + quarters`
 *     shifted by 6 so the integer part falls in [15:8] and the fraction
 *     in [7:6].
 *
 * Cross-reference: FSP CMSIS device header (RA8 Gen2 family)
 * `R_SYSTEM_PLL2CR_PLL2STP_Pos`, `R_SYSTEM_PLL2CCR_PL2IDIV_Pos`,
 * `R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos`, `R_SYSTEM_PLL2CCR_PLL2MUL_Pos`,
 * `R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos` etc.
 */

typedef enum : uint8_t {
  k_ra8_pll2cr_run  = 0x00U, 
  k_ra8_pll2cr_stop = 0x01U, 
} ra8_pll2cr_val_t;

typedef enum : uint32_t {
  k_ra8_pll2ccr_mask_plidiv   = 0x00000003U, 
  k_ra8_pll2ccr_mask_quarters = 0x000007FFU, 
} ra8_pll2ccr_mask_t;
 
/* =============================================================================
 * HOCOCR / MOSCWTCR bit fields
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_hococr_hcstp = 0U, 
} ra8_hococr_bit_t;

typedef enum : uint8_t {
  k_ra8_moscwtcr_2_to_16_cycles = 0x09U, 
} ra8_moscwtcr_val_t;
 
#ifdef __cplusplus
}
#endif