ra8_cgc_regs.h File Reference

Clock Generation Circuit (CGC) field layouts for the Renesas RA8D2. More...

#include <stdint.h>

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Enumerations
enum	ra8_sckdivcr_shift_t : uint8_t {   k_ra8_sckdivcr_pckd_shift = 0U ,   k_ra8_sckdivcr_pckc_shift = 4U ,   k_ra8_sckdivcr_pckb_shift = 8U ,   k_ra8_sckdivcr_pcka_shift = 12U ,   k_ra8_sckdivcr_bck_shift = 16U ,   k_ra8_sckdivcr_pcke_shift = 20U ,   k_ra8_sckdivcr_ick_shift = 24U ,   k_ra8_sckdivcr_fck_shift = 28U }
	Bit shifts for the divider nibbles in SCKDIVCR. More...
enum	ra8_clock_div_t : uint8_t {   k_ra8_clock_div_1 = 0x0U ,   k_ra8_clock_div_2 = 0x1U ,   k_ra8_clock_div_4 = 0x2U ,   k_ra8_clock_div_8 = 0x3U ,   k_ra8_clock_div_16 = 0x4U ,   k_ra8_clock_div_32 = 0x5U ,   k_ra8_clock_div_64 = 0x6U }
	Divider codes written into SCKDIVCR nibbles. More...
enum	ra8_sckdivcr2_shift_t : uint8_t {   k_ra8_sckdivcr2_cpuclk0_shift = 0U ,   k_ra8_sckdivcr2_cpuclk1_shift = 4U ,   k_ra8_sckdivcr2_npuclk_shift = 8U ,   k_ra8_sckdivcr2_mriclk_shift = 12U }
	Bit shifts for the divider nibbles in SCKDIVCR2. More...
enum	ra8_cksel_t : uint8_t {   k_ra8_cksel_hoco = 0U ,   k_ra8_cksel_moco = 1U ,   k_ra8_cksel_loco = 2U ,   k_ra8_cksel_main = 3U ,   k_ra8_cksel_subck = 4U ,   k_ra8_cksel_pll1 = 5U ,   k_ra8_cksel_pll2 = 6U }
	System clock source selector values written to SCKSCR.CKSEL. More...
enum	ra8_pllccr_shift_t : uint8_t {   k_ra8_pllccr_shift_plidiv = 0U ,   k_ra8_pllccr_shift_plsrcsel = 4U ,   k_ra8_pllccr_shift_quarters = 6U }
	Field shifts inside the 32-bit PLLCCR. More...
enum	ra8_pllccr_mask_t : uint32_t {   k_ra8_pllccr_mask_plidiv = 0x00000003UL ,   k_ra8_pllccr_mask_quarters = 0x000007FFUL }
	Bitfield masks (post-shift) inside PLLCCR. More...
enum	ra8_plidiv_t : uint8_t {   k_ra8_plidiv_div1 = 0U ,   k_ra8_plidiv_div2 = 1U ,   k_ra8_plidiv_div3 = 2U }
	PLL input divider codes for PLIDIV[1:0] in PLLCCR. More...
enum	ra8_plsrcsel_t : uint8_t {   k_ra8_plsrcsel_main = 0U ,   k_ra8_plsrcsel_hoco = 1U }
	PLL1 input source selection (PLLCCR.PLSRCSEL, bit 4). More...
enum	ra8_pllccr2_shift_t : uint8_t {   k_ra8_pllccr2_shift_plodivp = 0U ,   k_ra8_pllccr2_shift_plodivq = 4U ,   k_ra8_pllccr2_shift_plodivr = 8U }
	Field shifts inside the 16-bit PLLCCR2. More...
enum	ra8_plodiv_t : uint8_t {   k_ra8_plodiv_div2 = 1U ,   k_ra8_plodiv_div3 = 2U ,   k_ra8_plodiv_div4 = 3U ,   k_ra8_plodiv_div5 = 4U ,   k_ra8_plodiv_div6 = 5U ,   k_ra8_plodiv_div8 = 7U ,   k_ra8_plodiv_div9 = 8U ,   k_ra8_plodiv_div16 = 15U }
	PLL output divider codes for PLODIVP/Q/R fields in PLLCCR2. More...
enum	ra8_pll2cr_val_t : uint8_t {   k_ra8_pll2cr_run = 0x00U ,   k_ra8_pll2cr_stop = 0x01U }
	Discrete values written to the 8-bit PLL2CR register. More...
enum	ra8_pll2ccr_mask_t : uint32_t {   k_ra8_pll2ccr_mask_plidiv = 0x00000003U ,   k_ra8_pll2ccr_mask_quarters = 0x000007FFU }
	Field masks (post-shift) inside PLL2CCR. More...
enum	ra8_hococr_bit_t : uint8_t { k_ra8_hococr_hcstp = 0U }
	Bit positions in HOCOCR. More...
enum	ra8_moscwtcr_val_t : uint8_t { k_ra8_moscwtcr_2_to_16_cycles = 0x09U }
	Values written to MOSCWTCR to control main-osc wait cycles. More...

Detailed Description

Clock Generation Circuit (CGC) field layouts for the Renesas RA8D2.

The CGC is logically a separate peripheral but physically lives inside the SYSC register block (ra8_system_regs.h). This header provides the bit-field encodings, divider ratios and clock-source selectors needed to programme the PLL and clock tree from ra8_cgc.c.

Registers covered

Reg	Offset	Width	Notes
SCKDIVCR	0x020	32	PCLKA..E, BCLK, ICLK, FCLK dividers
SCKDIVCR2	0x024	16	CPUCLK0, CPUCLK1, NPUCLK, MRICLK
SCKSCR	0x026	8	System clock source select (CKSEL)
PLLCR	0x02A	8	PLL1 stop control
PLLCCR	0x0AC	32	PLL1 multiplier / divider / source
HOCOCR	0x036	8	HOCO stop control (HCSTP)
MOSCWTCR	0x0A2	8	Main osc wait cycles

Full field layouts come from the RA8D2 Hardware User's Manual section 10 ("Clock Generation Circuit").

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_cgc_regs.h.

Enumeration Type Documentation

ra8_cksel_t

enum ra8_cksel_t : uint8_t

System clock source selector values written to SCKSCR.CKSEL.

Enumerator
k_ra8_cksel_hoco	High-speed on-chip oscillator.
k_ra8_cksel_moco	Middle-speed on-chip osc.
k_ra8_cksel_loco	Low-speed on-chip osc.
k_ra8_cksel_main	Main oscillator (XTAL).
k_ra8_cksel_subck	Sub-clock osc.
k_ra8_cksel_pll1	PLL1 output.
k_ra8_cksel_pll2	PLL2 output.

Definition at line 108 of file ra8_cgc_regs.h.

ra8_clock_div_t

enum ra8_clock_div_t : uint8_t

Divider codes written into SCKDIVCR nibbles.

The RA8 SCKDIVCR nibble encodes divide-by-2^N where the nibble value is N, except that 0 means divide-by-1. See HUM Table 10.x for the full list; we only expose the values the project uses.

Enumerator
k_ra8_clock_div_1	Divide by 1.
k_ra8_clock_div_2	Divide by 2.
k_ra8_clock_div_4	Divide by 4.
k_ra8_clock_div_8	Divide by 8.
k_ra8_clock_div_16	Divide by 16.
k_ra8_clock_div_32	Divide by 32.
k_ra8_clock_div_64	Divide by 64.

Definition at line 73 of file ra8_cgc_regs.h.

ra8_hococr_bit_t

enum ra8_hococr_bit_t : uint8_t

Bit positions in HOCOCR.

Enumerator
k_ra8_hococr_hcstp	HCSTP: 0 operating, 1 stopped.

Definition at line 286 of file ra8_cgc_regs.h.

ra8_moscwtcr_val_t

enum ra8_moscwtcr_val_t : uint8_t

Values written to MOSCWTCR to control main-osc wait cycles.

The wait count covers main-osc stabilisation at startup. 0x09 (2^16 cycles) is the default recommended value for the 24 MHz crystal on the EK-RA8D2 and yields ~2.7 ms of wait time.

Enumerator
k_ra8_moscwtcr_2_to_16_cycles	RA8 moscwtcr 2 to 16 cycles.

Definition at line 299 of file ra8_cgc_regs.h.

ra8_plidiv_t

enum ra8_plidiv_t : uint8_t

PLL input divider codes for PLIDIV[1:0] in PLLCCR.

Quickstart EK-RA8D2 picks /3 (code 2). Code = ratio - 1 for the supported ratios 1, 2, 3.

Enumerator
k_ra8_plidiv_div1	PLL input divide by 1.
k_ra8_plidiv_div2	PLL input divide by 2.
k_ra8_plidiv_div3	PLL input divide by 3.

Definition at line 165 of file ra8_cgc_regs.h.

ra8_pll2ccr_mask_t

enum ra8_pll2ccr_mask_t : uint32_t

Field masks (post-shift) inside PLL2CCR.

RA8D2's PLL2MUL field is 9 bits wide (HUM Ch 9.2.9), so the (mul*4 + quarters) payload fits in 11 bits (9 integer + 2 fractional) once shifted by 6 to span PLL2MULNF[7:6] and PLL2MUL[16:8].

Enumerator
k_ra8_pll2ccr_mask_plidiv	PL2IDIV 2-bit field.
k_ra8_pll2ccr_mask_quarters	11-bit (mul*4) field.

Definition at line 272 of file ra8_cgc_regs.h.

ra8_pll2cr_val_t

enum ra8_pll2cr_val_t : uint8_t

Discrete values written to the 8-bit PLL2CR register.

Enumerator
k_ra8_pll2cr_run	Clear PLL2STP -> PLL2 runs.
k_ra8_pll2cr_stop	Set PLL2STP -> PLL2 stops.

Definition at line 259 of file ra8_cgc_regs.h.

ra8_pllccr2_shift_t

enum ra8_pllccr2_shift_t : uint8_t

Field shifts inside the 16-bit PLLCCR2.

Enumerator
k_ra8_pllccr2_shift_plodivp	PLODIVP field starts at bit 0.
k_ra8_pllccr2_shift_plodivq	PLODIVQ field starts at bit 4.
k_ra8_pllccr2_shift_plodivr	PLODIVR field starts at bit 8.

Definition at line 201 of file ra8_cgc_regs.h.

ra8_pllccr_mask_t

enum ra8_pllccr_mask_t : uint32_t

Bitfield masks (post-shift) inside PLLCCR.

Enumerator
k_ra8_pllccr_mask_plidiv	PLIDIV 2-bit field.
k_ra8_pllccr_mask_quarters	11-bit (mul*4) field.

Definition at line 152 of file ra8_cgc_regs.h.

ra8_pllccr_shift_t

enum ra8_pllccr_shift_t : uint8_t

Field shifts inside the 32-bit PLLCCR.

Enumerator
k_ra8_pllccr_shift_plidiv	PLIDIV field starts at bit 0.
k_ra8_pllccr_shift_plsrcsel	PLSRCSEL field is bit 4.
k_ra8_pllccr_shift_quarters	(mul * 4) goes here.

Definition at line 142 of file ra8_cgc_regs.h.

ra8_plodiv_t

enum ra8_plodiv_t : uint8_t

PLL output divider codes for PLODIVP/Q/R fields in PLLCCR2.

Encoded as ratio - 1 for ratios 1..6, plus discrete codes for /8, /9, /16. The quickstart EK-RA8D2 uses /2 for P, /6 for Q, /5 for R.

Warning

Per HUM Ch 9.2.7 (PLLCCR2) and Ch 9.2.10/9.2.12 (PLL2CCR2) the bit pattern 0000 is listed as "Setting prohibited". Writing code 0 in any PLODIVP/Q/R field is silently rejected by hardware: the entire 16-bit register write is dropped and the register stays at its previous (often reset-default) value. Use a valid divider code in every field, even for outputs you do not consume. k_ra8_plodiv_div1 is therefore intentionally absent from this enum.

Enumerator
k_ra8_plodiv_div2	PLL output divide by 2.
k_ra8_plodiv_div3	PLL output divide by 3.
k_ra8_plodiv_div4	PLL output divide by 4.
k_ra8_plodiv_div5	PLL output divide by 5.
k_ra8_plodiv_div6	PLL output divide by 6.
k_ra8_plodiv_div8	PLL output divide by 8.
k_ra8_plodiv_div9	PLL output divide by 9.
k_ra8_plodiv_div16	PLL output divide by 16.

Definition at line 223 of file ra8_cgc_regs.h.

ra8_plsrcsel_t

enum ra8_plsrcsel_t : uint8_t

PLL1 input source selection (PLLCCR.PLSRCSEL, bit 4).

Enumerator
k_ra8_plsrcsel_main	Main-oscillator input (default on EK board).
k_ra8_plsrcsel_hoco	HOCO input (useful for XTAL-less boards).

Definition at line 175 of file ra8_cgc_regs.h.

ra8_sckdivcr2_shift_t

enum ra8_sckdivcr2_shift_t : uint8_t

Bit shifts for the divider nibbles in SCKDIVCR2.

Enumerator
k_ra8_sckdivcr2_cpuclk0_shift	CPUCLK0 (M85) divider @ [3:0].
k_ra8_sckdivcr2_cpuclk1_shift	CPUCLK1 (M33) divider @ [7:4].
k_ra8_sckdivcr2_npuclk_shift	NPUCLK divider @ [11:8].
k_ra8_sckdivcr2_mriclk_shift	MRAM bus clk divider @ [15:12].

Definition at line 92 of file ra8_cgc_regs.h.

ra8_sckdivcr_shift_t

enum ra8_sckdivcr_shift_t : uint8_t

Bit shifts for the divider nibbles in SCKDIVCR.

Enumerator
k_ra8_sckdivcr_pckd_shift	PCLKD divider nibble @ [3:0].
k_ra8_sckdivcr_pckc_shift	PCLKC divider nibble @ [7:4].
k_ra8_sckdivcr_pckb_shift	PCLKB divider nibble @ [11:8].
k_ra8_sckdivcr_pcka_shift	PCLKA divider nibble @ [15:12].
k_ra8_sckdivcr_bck_shift	BCLK divider nibble @ [19:16].
k_ra8_sckdivcr_pcke_shift	PCLKE divider nibble @ [23:20].
k_ra8_sckdivcr_ick_shift	ICLK divider nibble @ [27:24].
k_ra8_sckdivcr_fck_shift	FCLK divider nibble @ [31:28].

Definition at line 53 of file ra8_cgc_regs.h.