System, clocks & power

ICU/ELC/ISR, CGC, MSTP, LPM/PWR, reset, MPC/ports, SRAM, IPC. More...

Collaboration diagram for System, clocks & power:

Files
file	ra8_bkup.h
	Battery Backup Function (VBATT) HAL driver – public API.
file	ra8_bkup_regs.h
	Battery Backup Function (VBATT / BAT*) register layout for the RA8D2.
file	ra8_ble.h
	BLE HCI transport seam (host-side).
file	ra8_bscan.h
	JTAG / IEEE-1149.1 Boundary Scan TAP HAL surface.
file	ra8_bscan_regs.h
	JTAG / IEEE-1149.1 Boundary Scan TAP constants for the RA8D2.
file	ra8_cac.h
	Clock Accuracy Check driver.
file	ra8_cac_regs.h
	Clock Accuracy Check (CAC) register layout for the Renesas RA8D2.
file	ra8_cache.h
	Cortex-M85 L1 cache maintenance, enable/disable, and I-cache invalidate.
file	ra8_cgc.h
	High-level Clock Generation Circuit driver.
file	ra8_cgc_regs.h
	Clock Generation Circuit (CGC) field layouts for the Renesas RA8D2.
file	ra8_doc.h
	Data Operation Circuit (DOC) driver header.
file	ra8_doc_regs.h
	Data Operation Circuit (DOC) register layout for the Renesas RA8D2.
file	ra8_dual_core.h
	Dual-core (CPU0 / CPU1) lifecycle helper – public API.
file	ra8_dual_core_job.h
	Cross-core compile-job dispatch seam + status contract (#149).
file	ra8_elc.h
	Event Link Controller driver.
file	ra8_elc_regs.h
	Event Link Controller (ELC) register layout for the Renesas RA8D2.
file	ra8_ethosu_kernel.h
	First-party TFLite-micro Ethos-U custom-op registration probe (RA8P1-only).
file	ra8_ethosu_shim.h
	Arm ethos-u-core-driver C API shim over the ra8_npu driver (RA8P1-only).
file	ra8_fpu_probe.h
	Double-precision FPU probe – codegen witness for the RA8P1 DP-FPU.
file	ra8_hw_err.h
	Bounded wait-flag primitives for RA8D2 HAL drivers.
file	ra8_hw_intrinsics.h
	Shared CPU-intrinsic seam for the HAL drivers (host/target split).
file	ra8_icu.h
	Interrupt Control Unit driver (IRQ pins, NMI).
file	ra8_icu_regs.h
	Interrupt Control Unit (ICU) register layout for the Renesas RA8D2.
file	ra8_ipc.h
	Inter-Processor Communication (IPC) HAL driver – public API.
file	ra8_ipc_regs.h
	Inter-Processor Communication (IPC) register layout for the RA8D2.
file	ra8_ipc_sync.h
	Inter-Processor Communication (IPC) HAL driver – sync API.
file	ra8_ipc_types.h
	Inter-Processor Communication (IPC) HAL driver – public types.
file	ra8_ipc_xfer.h
	Inter-Processor Communication (IPC) HAL driver – transfer API.
file	ra8_isr.h
	NVIC + ICU IELSR allocator.
file	ra8_lpm.h
	Low Power Mode (LPM) HAL driver – public API.
file	ra8_lpm_regs.h
	Low Power Mode (LPM) register layout for the Renesas RA8D2.
file	ra8_lpm_safe_boot.h
	Self-healing LPM register reset for very early boot.
file	ra8_lvd.h
	Programmable Voltage Detection (PVD / LVD) HAL driver.
file	ra8_lvd_api.h
	Programmable Voltage Detection (PVD / LVD) HAL function prototypes.
file	ra8_lvd_regs.h
	Programmable Voltage Detection (PVD / LVD) register layout for the RA8D2.
file	ra8_lvd_types.h
	Programmable Voltage Detection (PVD / LVD) HAL types.
file	ra8_mpc.h
	Multi-function Pin Controller (MPC) facade.
file	ra8_mpu_regs.h
	Memory Protection Unit register layout for the Renesas RA8D2.
file	ra8_mrms_regs.h
	MRAM Memory System (MRMS) wait-state register layout for the RA8D2.
file	ra8_mstp.h
	Ref-counted Module Stop Control wrapper for the RA8D2.
file	ra8_mstp_regs.h
	Module Stop Control (MSTP) register layout for the Renesas RA8D2.
file	ra8_npu.h
	Arm Ethos-U55 NPU command/queue driver foundation (RA8P1-only).
file	ra8_npu_blob.h
	.npub linkable-blob container for a Vela-compiled Ethos-U55 model
file	ra8_npu_fake_cmd.h
	ra8_emulator / host-test command-stream convention for the Ethos-U55 model
file	ra8_npu_loader.h
	On-target loader: .npub Vela blob -> ra8_npu_job_t (RA8P1-only).
file	ra8_npu_quant.h
	Affine (scale + zero-point) tensor quantization for the NPU runtime.
file	ra8_npu_regs.h
	Arm Ethos-U55 NPU register window on the Renesas RA8P1 (RA8P1-only).
file	ra8_ofs.h
	Option Function Select (OFS) boot-map inventory for the active RA8 device.
file	ra8_pcntr.h
	CPU1-safe combined direction+level PORT primitive over PCNTR1/PCNTR2.
file	ra8_pdg.h
	PWM Delay Generation Circuit (PDG) driver public API.
file	ra8_pdg_regs.h
	PWM Delay Generation Circuit (PDG) register layout for the Renesas RA8D2.
file	ra8_pfs_regs.h
	Pin Function Select (PFS) register layout for the Renesas RA8D2.
file	ra8_port_regs.h
	IOPORT (GPIO) register layout for the Renesas RA8D2.
file	ra8_port_utils.h
	High-level GPIO helpers on top of the PORT + PFS register layer.
file	ra8_pwr.h
	Low Power Mode + clock-domain wrapper.
file	ra8_register_protection.h
	Scoped PRCR unlock helper.
file	ra8_regs.h
	Top-level peripheral register header for the Renesas RA8D2.
file	ra8_reset.h
	Reset cause introspection + software reset trigger.
file	ra8_reset_regs.h
	Reset block register layout (offsets, bit masks, accessors)for the Renesas RA8D2.
file	ra8_system_regs.h
	System Control (SYSC) register layout for the Renesas RA8D2.
file	ra8_vreg.h
	Internal Voltage Regulator (DCDC / LDO) driver – full HUM Ch 68 surface.
file	ra8_vreg_regs.h
	Internal Voltage Regulator (VREG / DCDC / LDO) register layout for RA8D2.
file	ra8_bkup_internal.h
	Cross-TU shared surface for the ra8_bkup driver split.
file	ra8_cgc_internal.h
	Cross-TU sharing for the split Clock Generation Circuit driver.
file	ra8_hal_internal.h
	Cross-translation-unit private helpers shared inside ra8_hal.
file	ra8_lvd_internal.h
	Test-access surface for ra8_lvd internal helpers (MC/DC).
file	ra8_mstp_internal.h
	Cross-TU surface for the ra8_mstp module-stop driver (test access).

Detailed Description

ICU/ELC/ISR, CGC, MSTP, LPM/PWR, reset, MPC/ports, SRAM, IPC.