ra8_lpm_regs.h File Reference

Low Power Mode (LPM) register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_lpm_regs.h:

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Go to the source code of this file.

Enumerations
enum	ra8_lpm_addr_t : uintptr_t {   k_ra8_lpm_sysc_base_addr = 0x4001E000UL ,   k_ra8_lpm_icu_base_addr = 0x4000C000UL }
	Hardware base addresses used by the LPM HAL driver. More...
enum	ra8_lpm_off_t : uint16_t {   k_ra8_lpm_sbycr_off = 0x00CU ,   k_ra8_lpm_lpscr_off = 0xA90U ,   k_ra8_lpm_sscr1_off = 0xA98U ,   k_ra8_lpm_dpsbycr_off = 0xA00U ,   k_ra8_lpm_opccr_off = 0x0A0U ,   k_ra8_lpm_prcr_off = 0x3FAU ,   k_ra8_lpm_pdramscr0_off = 0x140U ,   k_ra8_lpm_pdramscr1_off = 0x142U ,   k_ra8_lpm_pll1ldocr_off = 0xB04U ,   k_ra8_lpm_pll2ldocr_off = 0xB08U ,   k_ra8_lpm_hocoldocr_off = 0xB0CU ,   k_ra8_lpm_dpsier0_off = 0xA08U ,   k_ra8_lpm_dpsier1_off = 0xA0CU ,   k_ra8_lpm_dpsier2_off = 0xA10U ,   k_ra8_lpm_dpsier3_off = 0xA14U ,   k_ra8_lpm_dpsifr0_off = 0xA18U ,   k_ra8_lpm_dpsifr1_off = 0xA1CU ,   k_ra8_lpm_dpsifr2_off = 0xA20U ,   k_ra8_lpm_dpsifr3_off = 0xA24U ,   k_ra8_lpm_dpsiegr0_off = 0xA28U ,   k_ra8_lpm_dpsiegr1_off = 0xA2CU ,   k_ra8_lpm_dpsiegr2_off = 0xA30U ,   k_ra8_lpm_pdctrgd_off = 0x110U ,   k_ra8_lpm_mosccr_off = 0x032U ,   k_ra8_lpm_hococr_off = 0x036U ,   k_ra8_lpm_mococr_off = 0x038U ,   k_ra8_lpm_lococr_off = 0x400U ,   k_ra8_lpm_sosccr_off = 0xC00U ,   k_ra8_lpm_wupen0_off = 0x1A0U ,   k_ra8_lpm_wupen1_off = 0x1A4U }
	Byte offsets of every LPM-relevant register from its block base. More...
enum	ra8_sleep_mode_t : uint8_t {   k_ra8_sleep_mode_sleep = 0U ,   k_ra8_sleep_mode_deep_sleep = 2U ,   k_ra8_sleep_mode_software_std = 0x5U ,   k_ra8_sleep_mode_deep_standby_1 = 0x8U ,   k_ra8_sleep_mode_deep_standby_2 = 0x9U ,   k_ra8_sleep_mode_deep_standby_3 = 0xAU }
	Software-selectable sleep modes (LPSCR.LPMD encoding). More...
enum	ra8_lpm_sbycr_bits_t : uint8_t {   k_ra8_lpm_sbycr_ope_mask = 0x40U ,   k_ra8_lpm_sbycr_reset_val = 0x40U }
	SBYCR bit positions and reset value (HUM Ch 11.2.18 p 456). More...
enum	ra8_lpm_dpsbycr_bits_t : uint8_t {   k_ra8_lpm_dpsbycr_dcssmode_shift = 2U ,   k_ra8_lpm_dpsbycr_dcssmode_mask = 0x0CU ,   k_ra8_lpm_dpsbycr_iokeep_mask = 0x40U ,   k_ra8_lpm_dpsbycr_reset_val = 0x14U }
	DPSBYCR bit fields and reset value (HUM Ch 11.2.21 p 458). More...
enum	ra8_lpm_dcssmode_t : uint8_t {   k_ra8_lpm_dcssmode_128us = 0x1U ,   k_ra8_lpm_dcssmode_256us = 0x2U ,   k_ra8_lpm_dcssmode_512us = 0x3U }
	DPSBYCR.DCSSMODE encoding (HUM Ch 11.2.21 p 458). More...
enum	ra8_lpm_sscr1_bits_t : uint8_t {   k_ra8_lpm_sscr1_ss2fr_mask = 0x01U ,   k_ra8_lpm_sscr1_ss2lp_shift = 2U ,   k_ra8_lpm_sscr1_ss2lp_mask = 0x0CU }
	SSCR1 bit fields (HUM Ch 11.2.19 p 456). More...
enum	ra8_lpm_sscr1_ss2lp_t : uint8_t {   k_ra8_lpm_ss2lp_default = 0x0U ,   k_ra8_lpm_ss2lp_low = 0x1U }
	SSCR1.SS2LP encoding (HUM Ch 11.2.19 p 456). More...
enum	ra8_lpm_lpscr_bits_t : uint8_t { k_ra8_lpm_lpscr_lpmd_mask = 0x0FU }
	LPSCR bit fields (HUM Ch 11.2.20 p 457). More...
enum	ra8_lpm_opccr_bits_t : uint8_t {   k_ra8_lpm_opccr_opcm_mask = 0x03U ,   k_ra8_lpm_opccr_opcmtsf_msk = 0x10U }
	OPCCR bit fields (HUM Ch 11.2.11 p 451). More...
enum	ra8_lpm_prcr_bits_t : uint16_t {   k_ra8_lpm_prcr_key = 0xA500U ,   k_ra8_lpm_prcr_prc0_msk = 0x0001U ,   k_ra8_lpm_prcr_prc1_msk = 0x0002U ,   k_ra8_lpm_prcr_prc2_msk = 0x0008U }
	PRCR (write-protect) key + group masks (HUM Ch 11.2.18 p 456). More...
enum	ra8_lpm_pdramscr0_groups_t : uint16_t {   k_ra8_lpm_pdramscr0_sram0_keep = 0x000FU ,   k_ra8_lpm_pdramscr0_sram1_keep = 0x00F0U ,   k_ra8_lpm_pdramscr0_sram2_keep = 0x0F00U ,   k_ra8_lpm_pdramscr0_sram3_keep = 0x1000U ,   k_ra8_lpm_pdramscr0_all_keep = 0x1FFFU ,   k_ra8_lpm_pdramscr0_writable = 0x7FFFU }
	Useful PDRAMSCR0 RKEEP[12:0] preset masks (HUM Ch 11.2.16 p 453). More...
enum	ra8_lpm_pdramscr1_bits_t : uint8_t {   k_ra8_lpm_pdramscr1_rkeep0_mask = 0x01U ,   k_ra8_lpm_pdramscr1_rkeep1_mask = 0x02U }
	PDRAMSCR1 bit positions (HUM Ch 11.2.17 p 455). More...
enum	ra8_lpm_ldocr_bits_t : uint8_t {   k_ra8_lpm_ldocr_ldostp_mask = 0x01U ,   k_ra8_lpm_ldocr_skeep_mask = 0x02U ,   k_ra8_lpm_ldocr_skeep_shift = 1U }
	PLL[12]LDOCR / HOCOLDOCR shared bit fields (HUM Ch 11.2.40..42 p 475..476). More...
enum	ra8_lpm_ldo_state_t : uint8_t {   k_ra8_lpm_ldo_disabled = 0U ,   k_ra8_lpm_ldo_retained = 1U }
	LDOCR.SKEEP encoding for ra8_lpm_set_ldo_standby. More...
enum	ra8_lpm_clock_stop_bits_t : uint8_t { k_ra8_lpm_clock_stop_mask = 0x01U }
	Per-oscillator stop bit (HUM Ch 9.2.13..18 p 343..346). More...
enum	ra8_lpm_pdctr_bits_t : uint8_t {   k_ra8_lpm_pdctr_pdde_mask = 0x01U ,   k_ra8_lpm_pdctr_pdcsf_mask = 0x40U ,   k_ra8_lpm_pdctr_pdpgsf_mask = 0x80U }
	PDCTRGD power-gating field masks (HUM Ch 11.2.14 p 452). More...
enum	ra8_lpm_dpsier_idx_t : uint8_t {   k_ra8_lpm_dpsier_idx_0 = 0U ,   k_ra8_lpm_dpsier_idx_1 = 1U ,   k_ra8_lpm_dpsier_idx_2 = 2U ,   k_ra8_lpm_dpsier_idx_3 ,   k_ra8_lpm_dpsier_idx_count = 4U }
	Selector for DPSIER0..3 / DPSIFR0..3 / DPSIEGR0..2 helpers (HUM Ch 11.2.22..36 p 459..463). More...
enum	ra8_lpm_dpsier2_bits_t : uint8_t {   k_ra8_lpm_dpsier2_dpvd1ie_mask = 0x01U ,   k_ra8_lpm_dpsier2_dpvd2ie_mask = 0x02U ,   k_ra8_lpm_dpsier2_drtciie_mask = 0x04U ,   k_ra8_lpm_dpsier2_drtcaie_mask = 0x08U ,   k_ra8_lpm_dpsier2_dnmie_mask = 0x10U }
	DPSIER2 cancel-source bit positions (HUM Ch 11.2.24 p 460). More...
enum	ra8_lpm_dpsier3_bits_t : uint8_t {   k_ra8_lpm_dpsier3_dusbfsie_mask = 0x01U ,   k_ra8_lpm_dpsier3_dusbhsie_mask = 0x02U ,   k_ra8_lpm_dpsier3_dulpt0ie_mask = 0x04U ,   k_ra8_lpm_dpsier3_dulpt1ie_mask = 0x08U ,   k_ra8_lpm_dpsier3_diwdtie_mask = 0x20U ,   k_ra8_lpm_dpsier3_dsostdie_mask = 0x40U ,   k_ra8_lpm_dpsier3_dvbattadie_msk = 0x80U }
	DPSIER3 cancel-source bit positions (HUM Ch 11.2.25 p 461). More...
enum	ra8_lpm_wupen0_bits_t : uint32_t {   k_ra8_lpm_wupen0_irq0 = 1UL << 0 ,   k_ra8_lpm_wupen0_irq1 = 1UL << 1 ,   k_ra8_lpm_wupen0_irq2 = 1UL << 2 ,   k_ra8_lpm_wupen0_irq3 = 1UL << 3 ,   k_ra8_lpm_wupen0_irq4 = 1UL << 4 ,   k_ra8_lpm_wupen0_irq5 = 1UL << 5 ,   k_ra8_lpm_wupen0_irq6 = 1UL << 6 ,   k_ra8_lpm_wupen0_irq7 = 1UL << 7 ,   k_ra8_lpm_wupen0_iwdt = 1UL << 16 ,   k_ra8_lpm_wupen0_pvd1 = 1UL << 18 ,   k_ra8_lpm_wupen0_pvd2 = 1UL << 19 ,   k_ra8_lpm_wupen0_vbatt = 1UL << 20 ,   k_ra8_lpm_wupen0_rtcalm = 1UL << 24 ,   k_ra8_lpm_wupen0_rtcprd = 1UL << 25 ,   k_ra8_lpm_wupen0_usbhs = 1UL << 26 ,   k_ra8_lpm_wupen0_usbfs = 1UL << 27 ,   k_ra8_lpm_wupen0_agt1ud = 1UL << 28 ,   k_ra8_lpm_wupen0_agt1ca = 1UL << 29 ,   k_ra8_lpm_wupen0_agt1cb = 1UL << 30 ,   k_ra8_lpm_wupen0_riic0 = 1UL << 31 ,   k_ra8_lpm_wupen0_acmphs0 = k_ra8_lpm_wupen0_pvd1 }
	WUPEN0 bit masks for common wake-up sources (HUM Ch 14.2.19 p 550). More...
enum	ra8_lpm_wupen1_bits_t : uint32_t {   k_ra8_lpm_wupen1_comphs0 = 1UL << 3 ,   k_ra8_lpm_wupen1_sosc = 1UL << 7 ,   k_ra8_lpm_wupen1_ulpt0u = 1UL << 8 ,   k_ra8_lpm_wupen1_ulpt0a = 1UL << 9 ,   k_ra8_lpm_wupen1_ulpt0b = 1UL << 10 ,   k_ra8_lpm_wupen1_i3c0 = 1UL << 11 ,   k_ra8_lpm_wupen1_ulpt1u = 1UL << 12 ,   k_ra8_lpm_wupen1_ulpt1a = 1UL << 13 ,   k_ra8_lpm_wupen1_ulpt1b = 1UL << 14 ,   k_ra8_lpm_wupen1_pdm = 1UL << 15 }
	WUPEN1 bit masks for ULPT/I3C/SOSC/PDM/COMP sources (HUM Ch 14.2.20 p 552). More...
enum	ra8_lpm_scb_t : uintptr_t { k_ra8_lpm_scb_scr_addr = 0xE000ED10UL }
	ARM Cortex-M System Control Block address used for SLEEPDEEP. More...
enum	ra8_lpm_scb_field_t : uint32_t { k_ra8_lpm_scb_scr_sleepdeep = 0x4UL }
	ARM Cortex-M85 SCB.SCR field bits used for sleep entry. More...

Functions
static volatile uint32_t *	ra8_lpm_scb_scr (void)
	Return a typed pointer to the Cortex-M SCB->SCR register.
static volatile uint8_t *	ra8_lpm_sysc_reg8 (ra8_lpm_off_t off)
	Return a typed pointer to an 8-bit SYSC register.
static volatile uint16_t *	ra8_lpm_sysc_reg16 (ra8_lpm_off_t off)
	Return a typed pointer to a 16-bit SYSC register.
static volatile uint32_t *	ra8_lpm_icu_reg32 (ra8_lpm_off_t off)
	Return a typed pointer to a 32-bit ICU/WUPEN register.

Detailed Description

Low Power Mode (LPM) register layout for the Renesas RA8D2.

Hand-derived register map covering every register the LPM HAL driver in libs/ra8_hal/src/ra8_lpm.c touches. Sources:

• HUM Ch 11 "Low Power Mode" (pages 429..497) covers SBYCR, DPSBYCR, LPSCR, SSCR1, OPCCR, PDRAMSCR0/1, DPSIER0..3, DPSIFR0..3, DPSIEGR0..2, PLL1LDOCR, PLL2LDOCR, HOCOLDOCR.
• HUM Ch 9 "Clock Generation Circuit" (pages 317..419) covers MOSCCR, MOCOCR, HOCOCR, LOCOCR, SOSCCR (per-oscillator stop bits used by the LPM clock-shutdown matrix).
• HUM Ch 14 "Interrupt Controller Unit" (pages 549..553) covers WUPEN0 / WUPEN1 (wake-up source enables).

Two distinct hardware base addresses are involved:

• SYSC = 0x4001_E000 – SBYCR/DPSBYCR/LPSCR/SSCR1/OPCCR/PDRAMSCR family / DPSIER family / DPSIFR family / DPSIEGR family / PLL1LDOCR / PLL2LDOCR / HOCOLDOCR / MOSCCR / MOCOCR / HOCOCR / LOCOCR / SOSCCR / PRCR.
• ICU = 0x4000_C000 – WUPEN0/WUPEN1 (this is the WUPEN sub-block of ICU; the IELSR/NMI sub-block lives at 0x4000_6000).

The LPM driver works in terms of byte offsets relative to those two bases. Every offset enumerator below is byte-accurate against the HUM reference.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_lpm_regs.h.

Enumeration Type Documentation

ra8_lpm_addr_t

enum ra8_lpm_addr_t : uintptr_t

Hardware base addresses used by the LPM HAL driver.

Both bases live inside the 0x4000_0000 peripheral window so the host fake's blanket 8 MiB mmap covers them automatically.

Enumerator
k_ra8_lpm_sysc_base_addr	SYSC base (HUM Ch 11.2.18 p 456).
k_ra8_lpm_icu_base_addr	ICU/WUPEN base (HUM Ch 14.2.19 p 550).

Definition at line 59 of file ra8_lpm_regs.h.

ra8_lpm_clock_stop_bits_t

enum ra8_lpm_clock_stop_bits_t : uint8_t

Per-oscillator stop bit (HUM Ch 9.2.13..18 p 343..346).

Every oscillator control register (MOSCCR/HOCOCR/MOCOCR/LOCOCR/ SOSCCR) places its stop bit at bit 0:

• MOSCCR.MOSTP = bit 0
• HOCOCR.HCSTP = bit 0
• MOCOCR.MCSTP = bit 0
• LOCOCR.LCSTP = bit 0
• SOSCCR.SOSTP = bit 0

Enumerator
k_ra8_lpm_clock_stop_mask	STOP @ bit 0 in every OCR.

Definition at line 338 of file ra8_lpm_regs.h.

ra8_lpm_dcssmode_t

enum ra8_lpm_dcssmode_t : uint8_t

DPSBYCR.DCSSMODE encoding (HUM Ch 11.2.21 p 458).

Selects the wake-up time from Deep Software Standby with DCDC. Encoding 0b00 is "Setting prohibited"; the driver only exposes the three valid encodings.

Enumerator
k_ra8_lpm_dcssmode_128us	128 us soft-start (cold-reset default).
k_ra8_lpm_dcssmode_256us	256 us soft-start.
k_ra8_lpm_dcssmode_512us	512 us soft-start.

Definition at line 207 of file ra8_lpm_regs.h.

ra8_lpm_dpsbycr_bits_t

enum ra8_lpm_dpsbycr_bits_t : uint8_t

DPSBYCR bit fields and reset value (HUM Ch 11.2.21 p 458).

DCSSMODE[1:0] occupies bits 3:2; IOKEEP is bit 6. Reset value is 0x14 – bit 4 reads-as-1 plus DCSSMODE=01b (128 us soft-start).

Enumerator
k_ra8_lpm_dpsbycr_dcssmode_shift	DCSSMODE[1:0] starts at bit 2.
k_ra8_lpm_dpsbycr_dcssmode_mask	DCSSMODE[1:0] mask.
k_ra8_lpm_dpsbycr_iokeep_mask	IOKEEP @ bit 6.
k_ra8_lpm_dpsbycr_reset_val	Cold-reset value.

Definition at line 191 of file ra8_lpm_regs.h.

ra8_lpm_dpsier2_bits_t

enum ra8_lpm_dpsier2_bits_t : uint8_t

DPSIER2 cancel-source bit positions (HUM Ch 11.2.24 p 460).

Enumerator
k_ra8_lpm_dpsier2_dpvd1ie_mask	DPVD1IE @ bit 0.
k_ra8_lpm_dpsier2_dpvd2ie_mask	DPVD2IE @ bit 1.
k_ra8_lpm_dpsier2_drtciie_mask	DRTCIIE @ bit 2.
k_ra8_lpm_dpsier2_drtcaie_mask	DRTCAIE @ bit 3.
k_ra8_lpm_dpsier2_dnmie_mask	DNMIE @ bit 4.

Definition at line 383 of file ra8_lpm_regs.h.

ra8_lpm_dpsier3_bits_t

enum ra8_lpm_dpsier3_bits_t : uint8_t

DPSIER3 cancel-source bit positions (HUM Ch 11.2.25 p 461).

Enumerator
k_ra8_lpm_dpsier3_dusbfsie_mask	DUSBFSIE @ bit 0.
k_ra8_lpm_dpsier3_dusbhsie_mask	DUSBHSIE @ bit 1.
k_ra8_lpm_dpsier3_dulpt0ie_mask	DULPT0IE @ bit 2.
k_ra8_lpm_dpsier3_dulpt1ie_mask	DULPT1IE @ bit 3.
k_ra8_lpm_dpsier3_diwdtie_mask	DIWDTIE @ bit 5.
k_ra8_lpm_dpsier3_dsostdie_mask	DSOSTDIE @ bit 6.
k_ra8_lpm_dpsier3_dvbattadie_msk	DVBATTADIE@ bit 7.

Definition at line 395 of file ra8_lpm_regs.h.

ra8_lpm_dpsier_idx_t

enum ra8_lpm_dpsier_idx_t : uint8_t

Selector for DPSIER0..3 / DPSIFR0..3 / DPSIEGR0..2 helpers (HUM Ch 11.2.22..36 p 459..463).

Enumerator
k_ra8_lpm_dpsier_idx_0	DPSIER0 / DPSIFR0 / DPSIEGR0.
k_ra8_lpm_dpsier_idx_1	DPSIER1 / DPSIFR1 / DPSIEGR1.
k_ra8_lpm_dpsier_idx_2	DPSIER2 / DPSIFR2 / DPSIEGR2.
k_ra8_lpm_dpsier_idx_3	DPSIER3 / DPSIFR3 (HUM Ch 11.2.25 p 461 – DPSIEGR3 @ 0xA34 exists, unexposed here).
k_ra8_lpm_dpsier_idx_count	RA8 lpm dpsier index count.

Definition at line 369 of file ra8_lpm_regs.h.

ra8_lpm_ldo_state_t

enum ra8_lpm_ldo_state_t : uint8_t

LDOCR.SKEEP encoding for ra8_lpm_set_ldo_standby.

SKEEP=1 retains the LDO state across Software Standby; SKEEP=0 disables the LDO during standby for additional power savings.

Enumerator
k_ra8_lpm_ldo_disabled	LDO stops during standby (SKEEP=0).
k_ra8_lpm_ldo_retained	LDO retains state (SKEEP=1).

Definition at line 319 of file ra8_lpm_regs.h.

ra8_lpm_ldocr_bits_t

enum ra8_lpm_ldocr_bits_t : uint8_t

PLL[12]LDOCR / HOCOLDOCR shared bit fields (HUM Ch 11.2.40..42 p 475..476).

Enumerator
k_ra8_lpm_ldocr_ldostp_mask	LDOSTP @ bit 0 – stop in normal mode.
k_ra8_lpm_ldocr_skeep_mask	SKEEP @ bit 1 – retain in standby.
k_ra8_lpm_ldocr_skeep_shift	SKEEP starts at bit 1.

Definition at line 305 of file ra8_lpm_regs.h.

ra8_lpm_lpscr_bits_t

enum ra8_lpm_lpscr_bits_t : uint8_t

LPSCR bit fields (HUM Ch 11.2.20 p 457).

Enumerator
k_ra8_lpm_lpscr_lpmd_mask	LPMD[3:0] occupies bits 3..0.

Definition at line 236 of file ra8_lpm_regs.h.

ra8_lpm_off_t

enum ra8_lpm_off_t : uint16_t

Byte offsets of every LPM-relevant register from its block base.

Citations cite the exact HUM section + page where the offset is documented. Offsets in the SYSC group are relative to k_ra8_lpm_sysc_base_addr; WUPEN offsets are relative to k_ra8_lpm_icu_base_addr.

Enumerator
k_ra8_lpm_sbycr_off	SBYCR (8b) – HUM Ch 11.2.18 p 456.
k_ra8_lpm_lpscr_off	LPSCR (8b) – HUM Ch 11.2.20 p 457.
k_ra8_lpm_sscr1_off	SSCR1 (8b) – HUM Ch 11.2.19 p 456.
k_ra8_lpm_dpsbycr_off	DPSBYCR (8b) – HUM Ch 11.2.21 p 458.
k_ra8_lpm_opccr_off	OPCCR (8b) – HUM Ch 11.2.11 p 451.
k_ra8_lpm_prcr_off	PRCR (16b) – HUM Ch 11.2.18 p 456.
k_ra8_lpm_pdramscr0_off	PDRAMSCR0 (16b) – HUM Ch 11.2.16 p 453.
k_ra8_lpm_pdramscr1_off	PDRAMSCR1 (8b) – HUM Ch 11.2.17 p 455.
k_ra8_lpm_pll1ldocr_off	PLL1LDOCR (8b) – HUM Ch 11.2.40 p 475.
k_ra8_lpm_pll2ldocr_off	PLL2LDOCR (8b) – HUM Ch 11.2.41 p 475.
k_ra8_lpm_hocoldocr_off	HOCOLDOCR (8b) – HUM Ch 11.2.42 p 476.
k_ra8_lpm_dpsier0_off	DPSIER0 (8b) – HUM Ch 11.2.22 p 459.
k_ra8_lpm_dpsier1_off	DPSIER1 (8b) – HUM Ch 11.2.23 p 459.
k_ra8_lpm_dpsier2_off	DPSIER2 (8b) – HUM Ch 11.2.24 p 460.
k_ra8_lpm_dpsier3_off	DPSIER3 (8b) – HUM Ch 11.2.25 p 461.
k_ra8_lpm_dpsifr0_off	DPSIFR0 (8b) – HUM Ch 11.2.28 p 462.
k_ra8_lpm_dpsifr1_off	DPSIFR1 (8b) – HUM Ch 11.2.29 p 462.
k_ra8_lpm_dpsifr2_off	DPSIFR2 (8b) – HUM Ch 11.2.30 p 462.
k_ra8_lpm_dpsifr3_off	DPSIFR3 (8b) – HUM Ch 11.2.31 p 462.
k_ra8_lpm_dpsiegr0_off	DPSIEGR0 (8b) – HUM Ch 11.2.34 p 463.
k_ra8_lpm_dpsiegr1_off	DPSIEGR1 (8b) – HUM Ch 11.2.35 p 463.
k_ra8_lpm_dpsiegr2_off	DPSIEGR2 (8b) – HUM Ch 11.2.36 p 463.
k_ra8_lpm_pdctrgd_off	PDCTRGD (8b) – HUM Ch 11.2.14 p 452.
k_ra8_lpm_mosccr_off	MOSCCR (8b) – HUM Ch 9.2.13 p 343.
k_ra8_lpm_hococr_off	HOCOCR (8b) – HUM Ch 9.2.16 p 345.
k_ra8_lpm_mococr_off	MOCOCR (8b) – HUM Ch 9.2.18 p 346.
k_ra8_lpm_lococr_off	LOCOCR (8b) – HUM Ch 9.2.15 p 344.
k_ra8_lpm_sosccr_off	SOSCCR (8b) – HUM Ch 9.2.14 p 343.
k_ra8_lpm_wupen0_off	WUPEN0 (32b) – HUM Ch 14.2.19 p 550.
k_ra8_lpm_wupen1_off	WUPEN1 (32b) – HUM Ch 14.2.20 p 552.

Definition at line 79 of file ra8_lpm_regs.h.

ra8_lpm_opccr_bits_t

enum ra8_lpm_opccr_bits_t : uint8_t

OPCCR bit fields (HUM Ch 11.2.11 p 451).

Enumerator
k_ra8_lpm_opccr_opcm_mask	OPCM[1:0] @ bits 1..0 – power mode.
k_ra8_lpm_opccr_opcmtsf_msk	OPCMTSF @ bit 4 – mode-transition flag.

Definition at line 244 of file ra8_lpm_regs.h.

ra8_lpm_pdctr_bits_t

enum ra8_lpm_pdctr_bits_t : uint8_t

PDCTRGD power-gating field masks (HUM Ch 11.2.14 p 452).

The graphics power domain covers MIPI DSI, MIPI CSI, VIN, DRW and GLCDC (HUM Ch 11.5.1 Table 11.7 p 480). Its reset value is 0x81 – PDPGSF = 1 (domain gated OFF) and PDDE = 1 (power off the target domain) – so every one of those peripherals is unpowered until firmware clears PDDE. Bench-confirmed on an EK-RA8D2: with PDCTRGD = 0x81 the DRW HWREVISION register reads 0x00000000; after clearing PDDE it reads 0x0FBE0107.

PDDE polarity is inverted relative to the obvious reading: 0 powers the domain ON, 1 powers it OFF.

Enumerator
k_ra8_lpm_pdctr_pdde_mask	PDDE @ bit 0: 1 = powered OFF.
k_ra8_lpm_pdctr_pdcsf_mask	PDCSF @ bit 6: control busy.
k_ra8_lpm_pdctr_pdpgsf_mask	PDPGSF @ bit 7: 1 = gated off.

Definition at line 358 of file ra8_lpm_regs.h.

ra8_lpm_pdramscr0_groups_t

enum ra8_lpm_pdramscr0_groups_t : uint16_t

Useful PDRAMSCR0 RKEEP[12:0] preset masks (HUM Ch 11.2.16 p 453).

Per HUM Table 11.5 the RKEEP bits group as:

• SRAM0 = b3..b0 (must be all 1 or all 0 – 0xF or 0x0).
• SRAM1 = b7..b4 (mask 0xF0).
• SRAM2 = b11..b8 (mask 0xF00).
• SRAM3 = b12 (single bit, mask 0x1000).

Bit 13 reads-as-1; bit 14 reads-as-1; bit 15 reads-as-0. The "all keep" mask therefore sets bits 12..0 plus the read-as-1 bits 14..13, which is the cold-reset value.

Enumerator
k_ra8_lpm_pdramscr0_sram0_keep	Retain SRAM0 (b3..b0).
k_ra8_lpm_pdramscr0_sram1_keep	Retain SRAM1 (b7..b4).
k_ra8_lpm_pdramscr0_sram2_keep	Retain SRAM2 (b11..b8).
k_ra8_lpm_pdramscr0_sram3_keep	Retain SRAM3 (b12).
k_ra8_lpm_pdramscr0_all_keep	Retain all banks.
k_ra8_lpm_pdramscr0_writable	b14..b0 writable mask.

Definition at line 282 of file ra8_lpm_regs.h.

ra8_lpm_pdramscr1_bits_t

enum ra8_lpm_pdramscr1_bits_t : uint8_t

PDRAMSCR1 bit positions (HUM Ch 11.2.17 p 455).

Enumerator
k_ra8_lpm_pdramscr1_rkeep0_mask	RKEEP0 @ bit 0 – CPU0 TCM.
k_ra8_lpm_pdramscr1_rkeep1_mask	RKEEP1 @ bit 1 – CPU1 TCM.

Definition at line 295 of file ra8_lpm_regs.h.

ra8_lpm_prcr_bits_t

enum ra8_lpm_prcr_bits_t : uint16_t

PRCR (write-protect) key + group masks (HUM Ch 11.2.18 p 456).

The protection register is 16 bits wide. The upper byte must be 0xA5 on every write; the lower byte selects which protected groups are unlocked. PRC1 (bit 1) gates LPM/SYSC writes used by this driver.

Enumerator
k_ra8_lpm_prcr_key	Mandatory password in upper byte.
k_ra8_lpm_prcr_prc0_msk	PRC0 – CGC + LVD group.
k_ra8_lpm_prcr_prc1_msk	PRC1 – LPM/SYSC group.
k_ra8_lpm_prcr_prc2_msk	PRC3 (LVD reset) – not used here.

Definition at line 259 of file ra8_lpm_regs.h.

ra8_lpm_sbycr_bits_t

enum ra8_lpm_sbycr_bits_t : uint8_t

SBYCR bit positions and reset value (HUM Ch 11.2.18 p 456).

Enumerator
k_ra8_lpm_sbycr_ope_mask	OPE @ bit 6 – bus-signal output keep.
k_ra8_lpm_sbycr_reset_val	Cold-reset value (OPE=1, all else 0).

Definition at line 178 of file ra8_lpm_regs.h.

ra8_lpm_scb_field_t

enum ra8_lpm_scb_field_t : uint32_t

ARM Cortex-M85 SCB.SCR field bits used for sleep entry.

Only SLEEPDEEP is driven by the LPM driver; sibling bits such as SLEEPONEXIT and SEVONPEND are preserved by read-modify-write.

Invariant

Each enumerator is a single-bit mask within SCR.

See also

ra8_lpm_scb_scr() Accessor returning the typed pointer.

Since

0.1.0

Enumerator
k_ra8_lpm_scb_scr_sleepdeep	SCR.SLEEPDEEP @ bit 2.

Definition at line 494 of file ra8_lpm_regs.h.

ra8_lpm_scb_t

enum ra8_lpm_scb_t : uintptr_t

ARM Cortex-M System Control Block address used for SLEEPDEEP.

SCB->SCR lives at 0xE000_E000 + 0x10 in the System Control Space; the SLEEPDEEP bit instructs WFI to enter Deep Sleep / Software Standby instead of plain CPU sleep. This is an Arm core register (Armv8-M SCS), not an RA8D2 peripheral, so it carries no HUM citation. The host unit-test build backs the SCS window with RAM (ra8_fake_mmap core region at 0xE0000000), so the driver's read-modify-write sequence runs unchanged on every build.

Invariant

The single enumerator is the architectural SCR address.

See also

ra8_lpm_scb_scr() Accessor returning the typed pointer.

ra8_lpm_scb_field_t SCR field masks used by the LPM driver.

Since

0.1.0

Enumerator
k_ra8_lpm_scb_scr_addr	SCB->SCR address (Cortex-M85).

Definition at line 477 of file ra8_lpm_regs.h.

ra8_lpm_sscr1_bits_t

enum ra8_lpm_sscr1_bits_t : uint8_t

SSCR1 bit fields (HUM Ch 11.2.19 p 456).

Enumerator
k_ra8_lpm_sscr1_ss2fr_mask	SS2FR @ bit 0 – fast return.
k_ra8_lpm_sscr1_ss2lp_shift	SS2LP[1:0] starts at bit 2.
k_ra8_lpm_sscr1_ss2lp_mask	SS2LP[1:0] mask.

Definition at line 217 of file ra8_lpm_regs.h.

ra8_lpm_sscr1_ss2lp_t

enum ra8_lpm_sscr1_ss2lp_t : uint8_t

SSCR1.SS2LP encoding (HUM Ch 11.2.19 p 456).

Enumerator
k_ra8_lpm_ss2lp_default	SS2LP_0 – default mode.
k_ra8_lpm_ss2lp_low	SS2LP_1 – low power setting 1.

Definition at line 227 of file ra8_lpm_regs.h.

ra8_lpm_wupen0_bits_t

enum ra8_lpm_wupen0_bits_t : uint32_t

WUPEN0 bit masks for common wake-up sources (HUM Ch 14.2.19 p 550).

WUPEN0 packs IRQ0..IRQ15 into bits 15..0 plus assorted peripheral wake-up enables in bits 31..16. The driver provides per-source masks for the bits the firmware actually targets; raw 32-bit writes work for everything else.

Enumerator
k_ra8_lpm_wupen0_irq0	IRQ0 @ bit 0.
k_ra8_lpm_wupen0_irq1	IRQ1 @ bit 1.
k_ra8_lpm_wupen0_irq2	IRQ2 @ bit 2.
k_ra8_lpm_wupen0_irq3	IRQ3 @ bit 3.
k_ra8_lpm_wupen0_irq4	IRQ4 @ bit 4.
k_ra8_lpm_wupen0_irq5	IRQ5 @ bit 5.
k_ra8_lpm_wupen0_irq6	IRQ6 @ bit 6.
k_ra8_lpm_wupen0_irq7	IRQ7 @ bit 7.
k_ra8_lpm_wupen0_iwdt	IWDTWUPEN.
k_ra8_lpm_wupen0_pvd1	PVD1WUPEN.
k_ra8_lpm_wupen0_pvd2	PVD2WUPEN.
k_ra8_lpm_wupen0_vbatt	VBATTWUPEN.
k_ra8_lpm_wupen0_rtcalm	RTCALMWUPEN.
k_ra8_lpm_wupen0_rtcprd	RTCPRDWUPEN.
k_ra8_lpm_wupen0_usbhs	USBHSWUPEN.
k_ra8_lpm_wupen0_usbfs	USBFS0WUPEN.
k_ra8_lpm_wupen0_agt1ud	AGT1UDWUPEN.
k_ra8_lpm_wupen0_agt1ca	AGT1CAWUPEN.
k_ra8_lpm_wupen0_agt1cb	AGT1CBWUPEN.
k_ra8_lpm_wupen0_riic0	RIIC0WUPEN.
k_ra8_lpm_wupen0_acmphs0	legacy alias for PVD1 path.

Definition at line 416 of file ra8_lpm_regs.h.

ra8_lpm_wupen1_bits_t

enum ra8_lpm_wupen1_bits_t : uint32_t

WUPEN1 bit masks for ULPT/I3C/SOSC/PDM/COMP sources (HUM Ch 14.2.20 p 552).

Enumerator
k_ra8_lpm_wupen1_comphs0	COMPHS0WUPEN @ bit 3.
k_ra8_lpm_wupen1_sosc	SOSCWUPEN @ bit 7.
k_ra8_lpm_wupen1_ulpt0u	ULP0UWUPEN @ bit 8.
k_ra8_lpm_wupen1_ulpt0a	ULP0AWUPEN @ bit 9.
k_ra8_lpm_wupen1_ulpt0b	ULP0BWUPEN @ bit 10.
k_ra8_lpm_wupen1_i3c0	I3CWUPEN @ bit 11.
k_ra8_lpm_wupen1_ulpt1u	ULP1UWUPEN @ bit 12.
k_ra8_lpm_wupen1_ulpt1a	ULP1AWUPEN @ bit 13.
k_ra8_lpm_wupen1_ulpt1b	ULP1BWUPEN @ bit 14.
k_ra8_lpm_wupen1_pdm	PDMWUPEN @ bit 15.

Definition at line 445 of file ra8_lpm_regs.h.

ra8_sleep_mode_t

enum ra8_sleep_mode_t : uint8_t

Software-selectable sleep modes (LPSCR.LPMD encoding).

Values are the LPSCR.LPMD field encoding from HUM Ch 11.2.20 p 457 plus two pseudo-encodings (k_ra8_sleep_mode_sleep and k_ra8_sleep_mode_deep_sleep) for which LPMD stays at 0 (System Active) and only the Cortex-M85 SCR.SLEEPDEEP bit differs. The numeric values for the standby modes are the literal LPMD bit pattern so the driver can write mode directly into LPSCR.

Value	Meaning	LPMD	SLEEPDEEP
0	Sleep – CPU stop, peripherals run	0x0	0
2	Deep Sleep – CPU power-gate eligible	0x0	1
5	Software Standby	0x5	1
8	Deep Software Standby 1	0x8	1
9	Deep Software Standby 2	0x9	1
10	Deep Software Standby 3	0xA	1

The split between Deep Software Standby 1/2/3 follows HUM Ch 11.1 Table 11.3 (p 431..432): variants 2 and 3 progressively stop more domains (LOCO, sub-clock detection, voltage monitors).

Enumerator
k_ra8_sleep_mode_sleep	CPU sleep, peripherals run.
k_ra8_sleep_mode_deep_sleep	CPU deep sleep (SCR.SLEEPDEEP=1).
k_ra8_sleep_mode_software_std	Software Standby (LPMD=0x5).
k_ra8_sleep_mode_deep_standby_1	Deep Standby 1 (LPMD=0x8).
k_ra8_sleep_mode_deep_standby_2	Deep Standby 2 (LPMD=0x9).
k_ra8_sleep_mode_deep_standby_3	Deep Standby 3 (LPMD=0xA).

Definition at line 160 of file ra8_lpm_regs.h.

Function Documentation

ra8_lpm_icu_reg32()

volatile uint32_t * ra8_lpm_icu_reg32 ( ra8_lpm_off_t off )

inlinestatic

Return a typed pointer to a 32-bit ICU/WUPEN register.

Parameters

[in]

off

Byte offset (k_ra8_lpm_wupen0_off or k_ra8_lpm_wupen1_off).

Returns

Volatile pointer suitable for direct dereference.

Precondition

off corresponds to a documented 32-bit ICU register.

ICU bus is clocked.

Postcondition

No register has been modified by this call.

Returned pointer is non-NULL.

Note

Thread safety: pointer arithmetic is reentrant; the caller must serialize concurrent register writes.

Since

0.1.0

Definition at line 594 of file ra8_lpm_regs.h.

References k_ra8_lpm_icu_base_addr.

Referenced by ra8_lpm_arm_wupen0_bits(), ra8_lpm_arm_wupen1_bits(), ra8_lpm_clear_wupen0_bits(), ra8_lpm_clear_wupen1_bits(), ra8_lpm_deinit(), ra8_lpm_get_exit_cause(), ra8_lpm_set_wakeup_sources(), and ra8_lpm_snooze_set_request_sources().

ra8_lpm_scb_scr()

volatile uint32_t * ra8_lpm_scb_scr ( void )

inlinestatic

Return a typed pointer to the Cortex-M SCB->SCR register.

SCR is an Arm core register (Armv8-M System Control Space), shared by the LPM driver (SLEEPDEEP toggling around WFI) and the host unit tests (staging / asserting the toggle sequence through the fake mmap core window).

Returns

Volatile pointer suitable for direct dereference.

Precondition

Executing on the Cortex-M85 (or a host build with the SCS window RAM-backed by ra8_fake_mmap).

The address enum matches the Armv8-M architectural SCS layout.

Postcondition

No register has been modified by this call.

Returned pointer is non-NULL.

Note

Thread safety: pointer arithmetic is reentrant; the caller must serialize concurrent register writes.

Since

0.1.0

Definition at line 526 of file ra8_lpm_regs.h.

References k_ra8_lpm_scb_scr_addr.

Referenced by internal_set_sleepdeep().

ra8_lpm_sysc_reg16()

volatile uint16_t * ra8_lpm_sysc_reg16 ( ra8_lpm_off_t off )

inlinestatic

Return a typed pointer to a 16-bit SYSC register.

Parameters

[in]

off

Byte offset (one of k_ra8_lpm_*_off).

Returns

Volatile pointer suitable for direct dereference.

Precondition

off corresponds to a documented 16-bit register (PDRAMSCR0 or PRCR).

SYSC bus is clocked.

Postcondition

No register has been modified by this call.

Returned pointer is non-NULL.

Note

Thread safety: pointer arithmetic is reentrant; the caller must serialize concurrent register writes.

Since

0.1.0

Definition at line 571 of file ra8_lpm_regs.h.

References k_ra8_lpm_sysc_base_addr.

Referenced by ra8_lpm_prcr_relock(), ra8_lpm_prcr_unlock(), and ra8_lpm_set_ram_retention().

ra8_lpm_sysc_reg8()

volatile uint8_t * ra8_lpm_sysc_reg8 ( ra8_lpm_off_t off )

inlinestatic

Return a typed pointer to an 8-bit SYSC register.

Parameters

[in]

off

Byte offset (one of k_ra8_lpm_*_off).

Returns

Volatile pointer suitable for direct dereference.

Precondition

off corresponds to a documented 8-bit register.

SYSC bus is clocked.

Postcondition

No register has been modified by this call.

Returned pointer is non-NULL.

Note

Thread safety: pointer arithmetic is reentrant; the caller must serialize concurrent register writes.

Since

0.1.0

Definition at line 548 of file ra8_lpm_regs.h.

References k_ra8_lpm_sysc_base_addr.

Referenced by internal_graphics_clear_pdde(), internal_graphics_enable_moco(), internal_pdctrgd_wait(), ra8_lpm_arm_dpsier(), ra8_lpm_clear_dpsifr(), ra8_lpm_deinit(), ra8_lpm_enter_sleep(), ra8_lpm_get_clock_stop(), ra8_lpm_get_dpsi_state(), ra8_lpm_get_opccr(), ra8_lpm_get_status(), ra8_lpm_graphics_power_on(), ra8_lpm_init(), ra8_lpm_set_clock_stop(), ra8_lpm_set_dpsiegr(), ra8_lpm_set_ldo_standby(), ra8_lpm_set_ram_retention(), ra8_lpm_snooze_set_end_sources(), and ra8_lpm_wait_for_opccr().