ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_lpm_graphics.c
Go to the documentation of this file.
1
24
25#include <stdint.h>
26
27#include "ra8_attributes.h"
28#include "ra8_check.h"
29#include "ra8_err.h"
30#include "ra8_log.h"
31#include "ra8_lpm.h"
32#include "ra8_lpm_regs.h"
34
39static const char* s_tag = "LPM";
40
41/* =============================================================================
42 * Graphics power domain
43 * =============================================================================
44 */
45
66RA8_INTERNAL static ra8_err_t internal_pdctrgd_wait(uint8_t mask, bool want_set, uint32_t limit)
67{
68 for (uint32_t i = 0U; i < limit; ++i) {
69 /* HUM Ch 11.2.14 "PDCTRGD : Graphics Power Domain Control Register", p 452 */
70 const bool is_set = ((*ra8_lpm_sysc_reg8(k_ra8_lpm_pdctrgd_off) & mask) != 0U);
71 if (is_set == want_set) {
72 return k_ra8_ok;
73 }
74 }
76}
77
91{
93 {
94 /* HUM Ch 9.2.18 "MOCOCR : MOCO Control Register", p 341 */
95 volatile uint8_t* mococr = ra8_lpm_sysc_reg8(k_ra8_lpm_mococr_off);
96 *mococr = (uint8_t)(*mococr & (uint8_t)~k_ra8_lpm_clock_stop_mask);
97 }
98}
99
117{
118 ra8_err_t err = internal_pdctrgd_wait((uint8_t)k_ra8_lpm_pdctr_pdcsf_mask, false, limit);
119 RA8_RETURN_ON_ERROR(err, s_tag, "graphics_power_on: PDCSF busy");
120 err = internal_pdctrgd_wait((uint8_t)k_ra8_lpm_pdctr_pdpgsf_mask, true, limit);
121 return err;
122}
123
141{
142 ra8_err_t err = internal_pdctrgd_wait((uint8_t)k_ra8_lpm_pdctr_pdcsf_mask, false, limit);
143 /* GCOVR_EXCL_BR_START -- internal_pdctrgd_wait() error edge; PDCSF always clears off-target */
144 RA8_RETURN_ON_ERROR(err, s_tag, "graphics_power_on: PDCSF stuck");
145 /* GCOVR_EXCL_BR_STOP */
146 err = internal_pdctrgd_wait((uint8_t)k_ra8_lpm_pdctr_pdpgsf_mask, false, limit);
147 return err;
148}
149
163{
165 {
166 /* HUM Ch 11.2.14 "PDCTRGD : Graphics Power Domain Control Register", p 452 */
168 }
169}
170
171[[nodiscard]] ra8_err_t ra8_lpm_graphics_power_on(uint32_t timeout_iters)
172{
173 if (timeout_iters == 0U) {
174 ra8_log_error(s_tag, "graphics_power_on: timeout_iters == 0");
176 }
177
178 /* HUM Ch 11.2.14 "PDCTRGD : Graphics Power Domain Control Register", p 452 */
179 /* Already powered (PDPGSF = 0)? Idempotent no-op for multi-driver init. */
181 return k_ra8_ok;
182 }
183
185
186 ra8_err_t err = internal_graphics_confirm_ready(timeout_iters);
187 RA8_RETURN_ON_ERROR(err, s_tag, "graphics_power_on: not ready");
188
190
191 err = internal_graphics_confirm_powered(timeout_iters);
192 /* GCOVR_EXCL_BR_START -- internal_graphics_confirm_powered() error edge after clearing PDDE */
193 RA8_RETURN_ON_ERROR(err, s_tag, "graphics_power_on: still gated");
194 /* GCOVR_EXCL_BR_STOP */
195
196 ra8_log_info(s_tag, "graphics power domain on");
197 return k_ra8_ok;
198}
static const char * s_tag
Logging / check tag.
Definition ra8_app.c:17
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Validation and Error-Checking Macros for ra8-firmware.
#define RA8_RETURN_ON_ERROR(err, tag, message)
Early return on error, propagating the code upward.
Definition ra8_check.h:184
Error Code Definitions for ra8-firmware.
@ k_ra8_err_invalid_arg
Invalid function argument.
Definition ra8_err.h:152
@ k_ra8_err_hw_timeout
Hardware timed out waiting for a flag or handshake.
Definition ra8_err.h:304
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
Lightweight Logging Interface for ra8-firmware.
#define ra8_log_info(tag, message)
RA8 log info.
Definition ra8_log.h:364
#define ra8_log_error(tag, message)
RA8 log error.
Definition ra8_log.h:335
Low Power Mode (LPM) HAL driver – public API.
static void internal_graphics_enable_moco(void)
Start MOCO so the graphics power-gating controller has a clock.
static ra8_err_t internal_graphics_confirm_ready(uint32_t limit)
Wait until PDCSF = 0 and PDPGSF = 1 (domain ready for the clear).
static ra8_err_t internal_pdctrgd_wait(uint8_t mask, bool want_set, uint32_t limit)
Poll a PDCTRGD status flag until it reads the wanted level.
ra8_err_t ra8_lpm_graphics_power_on(uint32_t timeout_iters)
Power the graphics domain on (DRW / GLCDC / MIPI DSI+CSI / VIN).
static void internal_graphics_clear_pdde(void)
Clear PDDE under the PRC1 unlock so the domain powers on.
static ra8_err_t internal_graphics_confirm_powered(uint32_t limit)
Wait until PDCSF = 0 and PDPGSF = 0 (gating finished, domain live).
Low Power Mode (LPM) register layout for the Renesas RA8D2.
@ k_ra8_lpm_pdctr_pdcsf_mask
PDCSF @ bit 6: control busy.
@ k_ra8_lpm_pdctr_pdpgsf_mask
PDPGSF @ bit 7: 1 = gated off.
@ k_ra8_lpm_pdctrgd_off
PDCTRGD (8b) – HUM Ch 11.2.14 p 452.
@ k_ra8_lpm_mococr_off
MOCOCR (8b) – HUM Ch 9.2.18 p 346.
@ k_ra8_lpm_clock_stop_mask
STOP @ bit 0 in every OCR.
static volatile uint8_t * ra8_lpm_sysc_reg8(ra8_lpm_off_t off)
Return a typed pointer to an 8-bit SYSC register.
Scoped PRCR unlock helper.
#define RA8_PROTECTED_WRITE(unlock_val)
Scoped PRCR unlock block.
@ k_ra8_prcr_unlock_cgc
RA8 prcr unlock cgc.
@ k_ra8_prcr_unlock_lpm
RA8 prcr unlock lpm.