58typedef enum : uintptr_t {
67typedef enum : uint16_t {
121typedef enum : uint32_t {
134typedef enum : uint8_t {
149typedef enum : uint8_t {
164typedef enum : uint8_t {
181typedef enum : uint8_t {
194typedef enum : uint8_t {
227typedef enum : uint16_t {
260typedef enum : uint8_t {
271typedef enum : uint8_t {
494typedef enum : uint8_t {
505typedef enum : uint8_t {
602typedef enum : uint8_t {
619typedef enum : uint8_t {
691typedef enum : uint8_t {
static volatile uint8_t * ra8_sys_somcr(void)
Get pointer to the 8-bit SOMCR register (sub-clock oscillator mode).
static volatile uint8_t * ra8_sys_scickcr(void)
Get pointer to the 8-bit SCICKCR register (SCICLK source select).
static volatile uint8_t * ra8_sys_usbckcr(void)
Get pointer to the 8-bit USBCKCR (USB-FS source select).
static void ra8_sys_prcr_unlock_cgc(void)
Unlock the CGC + LVD protection group so CGC registers can be written.
ra8_prcr_t
Values to write to PRCR to unlock / lock protection groups.
@ k_ra8_prcr_unlock_rst
RA8 prcr unlock rst.
@ k_ra8_prcr_grp4_sar
PRC4 @ bit 4: security/privilege attribution.
@ k_ra8_prcr_grp0_cgc
PRC0 @ bit 0: clock generation circuit.
@ k_ra8_prcr_grp5_rst
PRC5 @ bit 5: reset control.
@ k_ra8_prcr_unlock_sar
RA8 prcr unlock sar.
@ k_ra8_prcr_unlock_cgc
RA8 prcr unlock cgc.
@ k_ra8_prcr_unlock_pvd
RA8 prcr unlock pvd.
@ k_ra8_prcr_key
Password in upper byte.
@ k_ra8_prcr_lock_all
RA8 prcr lock all.
@ k_ra8_prcr_unlock_lpm
RA8 prcr unlock lpm.
@ k_ra8_prcr_grp3_pvd
PRC3 @ bit 3: PVD + VBATTMNSELR.
@ k_ra8_prcr_grp1_lpm
PRC1 @ bit 1: low-power modes + VBATT backup.
@ k_ra8_sys_off_eswckdivcr
ESWCKDIVCR (8-bit) – ESWM module clock div.
@ k_ra8_sys_off_rstsr0
RSTSR0 (8-bit).
@ k_ra8_sys_off_pllcr
PLLCR (8-bit).
@ k_ra8_sys_off_eswpckcr
ESWPCKCR (8-bit) – ESWM-PHY clock source.
@ k_ra8_sys_off_vscr
VSCR voltage scaling control (32-bit).
@ k_ra8_sys_off_moscr
MOSCCR (8-bit).
@ k_ra8_sys_off_scickdivcr
SCICKDIVCR (8-bit).
@ k_ra8_sys_off_canfdckdivcr
CANFDCKDIVCR (8-bit) – HUM Ch 9.2.41 p 363.
@ k_ra8_sys_off_usb60ckcr
USB60CKCR (8-bit) – USBHS 60MHz src.
@ k_ra8_sys_off_rstsr2
RSTSR2 (8-bit).
@ k_ra8_sys_off_sosccr
SOSCCR (8-bit) – HUM Ch 9.2.14 p 339.
@ k_ra8_sys_off_pllccr
PLLCCR (32-bit).
@ k_ra8_sys_off_eswpckdivcr
ESWPCKDIVCR (8-bit) – ESWM-PHY clock div.
@ k_ra8_sys_off_usbckcr
USBCKCR (8-bit) – USB-FS clock src.
@ k_ra8_sys_off_canfdckcr
CANFDCKCR (8-bit) – HUM Ch 9.2.46 p 366.
@ k_ra8_sys_off_sckscr
SCKSCR (8-bit).
@ k_ra8_sys_off_usbckdivcr
USBCKDIVCR (8-bit) – USB-FS clock divider.
@ k_ra8_sys_off_pll2ccr
PLL2CCR – input/mul/source (32-bit, HUM Ch 9.2.9).
@ k_ra8_sys_off_moscwtcr
MOSCWTCR (8-bit).
@ k_ra8_sys_off_pdctreswm
PDCTRESWM (8-bit) – ESWM power-domain control.
@ k_ra8_sys_off_eswckcr
ESWCKCR (8-bit) – ESWM clock source.
@ k_ra8_sys_off_oscsf
OSCSF (8-bit).
@ k_ra8_sys_off_somcr
SOMCR (8-bit) – HUM Ch 9.2.29 p 351.
@ k_ra8_sys_off_usb60ckdivcr
USB60CKDIVCR (8-bit) – USBHS 60MHz divider.
@ k_ra8_sys_off_pllccr2
PLLCCR2 – PLL1 output dividers (16-bit).
@ k_ra8_sys_off_pll2ccr2
PLL2CCR2 – PLL2 output dividers (16-bit).
@ k_ra8_sys_off_scickcr
SCICKCR (8-bit).
@ k_ra8_sys_off_octackdivcr
OCTACKDIVCR (8-bit) – HUM Ch 9.2.40 p 357.
@ k_ra8_sys_off_prcr
PRCR (16-bit).
@ k_ra8_sys_off_pll2cr
PLL2CR – PLL2 stop control (8-bit).
@ k_ra8_sys_off_octackcr
OCTACKCR (8-bit) – HUM Ch 9.2.45 p 360.
@ k_ra8_sys_off_hococr
HOCOCR (8-bit).
@ k_ra8_sys_off_sckdivcr
SCKDIVCR (32-bit).
@ k_ra8_sys_off_rstsr1
RSTSR1 (32-bit).
@ k_ra8_sys_off_sckdivcr2
SCKDIVCR2 (16-bit).
@ k_ra8_sys_off_lococr
LOCOCR (8-bit) – HUM Ch 9.2.15 p 339.
static volatile uint8_t * ra8_sys_pllcr(void)
Get pointer to the 8-bit PLLCR register (PLL enable/stop).
static volatile uint32_t * ra8_sys_pll2ccr(void)
Get pointer to the 32-bit PLL2CCR register (PLL2 input/mul/source).
static volatile uint32_t * ra8_sys_vscr(void)
Get pointer to the 32-bit VSCR register (voltage scaling control).
ra8_rstsr2_bit_t
Reset Status Register 2 bit positions.
@ k_ra8_rstsr2_bit_iwdtrf
IWDT reset.
@ k_ra8_rstsr2_bit_swrf
Software reset.
@ k_ra8_rstsr2_bit_cwsf
Cold / warm start flag.
@ k_ra8_rstsr2_bit_wdtrf
WDT reset.
static volatile uint8_t * ra8_sys_octackcr(void)
Get pointer to the 8-bit OCTACKCR (Octal-SPI clock source select).
static volatile uint8_t * ra8_sys_octackdivcr(void)
Get pointer to the 8-bit OCTACKDIVCR (Octal-SPI clock divider).
static volatile uint16_t * ra8_sys_pll2ccr2(void)
Get pointer to the 16-bit PLL2CCR2 register (PLL2 output dividers).
static void ra8_sys_prcr_lock_all(void)
Re-lock every protection group (write password with all group bits clear).
ra8_oscsf_bit_t
Oscillation Stabilization Flag bit positions.
@ k_ra8_oscsf_bit_pll2sf
PLL2 stabilisation flag.
@ k_ra8_oscsf_bit_pll1sf
PLL1 stabilisation flag.
@ k_ra8_oscsf_bit_moscsf
Main oscillator stab flag.
@ k_ra8_oscsf_bit_hocosf
HOCO stabilisation flag.
static volatile uint8_t * ra8_sys_hococr(void)
Get pointer to the 8-bit HOCOCR register.
static volatile uint8_t * ra8_sys_pll2cr(void)
Get pointer to the 8-bit PLL2CR register (PLL2 stop control).
static volatile uint8_t * ra8_sys_canfdckcr(void)
Get pointer to the 8-bit CANFDCKCR (CANFD core clock source select).
static volatile uint8_t * ra8_sys_moscwtcr(void)
Get pointer to the 8-bit MOSCWTCR register.
static volatile uint16_t * ra8_sys_sckdivcr2(void)
Get pointer to the 16-bit SCKDIVCR2 register.
ra8_somcr_drv_t
SOMCR.SODRV[1:0] sub-clock drive-capability codes.
@ k_ra8_somcr_drv_standard
Standard drive (12.5 pF).
@ k_ra8_somcr_drv_lp1
Low-power mode 1 (9 pF).
@ k_ra8_somcr_drv_lp3
Low-power mode 3 (4 pF).
@ k_ra8_somcr_drv_lp2
Low-power mode 2 (7 pF).
static volatile uint8_t * ra8_sys_eswpckcr(void)
Get pointer to the 8-bit ESWPCKCR (Ethernet-PHY clock source).
static volatile uint8_t * ra8_sys_usbckdivcr(void)
Get pointer to the 8-bit USBCKDIVCR (USB clock divider).
static volatile uint8_t * ra8_sys_sosccr(void)
Get pointer to the 8-bit SOSCCR register (sub-clock oscillator stop).
static volatile uint8_t * ra8_sys_rstsr0(void)
Get pointer to the 8-bit RSTSR0 register.
static volatile uint16_t * ra8_sys_pllccr2(void)
Get pointer to the 16-bit PLLCCR2 register (PLL1 output dividers).
static volatile uint8_t * ra8_sys_lococr(void)
Get pointer to the 8-bit LOCOCR register (LOCO stop control).
static volatile uint8_t * ra8_sys_usb60ckdivcr(void)
Get pointer to the 8-bit USB60CKDIVCR (USBHS 60MHz divider).
static volatile uint8_t * ra8_sys_eswckcr(void)
Get pointer to the 8-bit ESWCKCR (Ethernet Switch / RMAC clock source).
static volatile uint8_t * ra8_sys_rstsr2(void)
Get pointer to the 8-bit RSTSR2 register.
static volatile uint8_t * ra8_sys_eswpckdivcr(void)
Get pointer to the 8-bit ESWPCKDIVCR (ESWPHYCLK divider; 4-bit CKDIV field).
ra8_lococr_bit_t
Bit mask in LOCOCR (Low-Speed On-Chip Oscillator Control Register).
@ k_ra8_lococr_lcstp_mask
LCSTP – 0 operates LOCO, 1 stops it.
ra8_sosccr_bit_t
Bit mask in SOSCCR (Sub-Clock Oscillator Control Register).
@ k_ra8_sosccr_sostp_mask
SOSTP – 0 operates SOSC, 1 stops it.
static volatile uint8_t * ra8_sys_pdctreswm(void)
Get pointer to the 8-bit PDCTRESWM (ESWM power-domain control).
ra8_eswcksel_t
ESWCKCR.CKSEL source codes (RA8D2 mapping).
@ k_ra8_eswcksel_pll1p
PLL1P (preferred for 125 MHz ESWCLK).
@ k_ra8_eswcksel_loco
LOCO.
@ k_ra8_eswcksel_pll2q
PLL2Q.
@ k_ra8_eswcksel_hoco
HOCO.
@ k_ra8_eswcksel_moco
MOCO.
@ k_ra8_eswcksel_main
Main XTAL.
@ k_ra8_eswcksel_pll1r
PLL1R.
@ k_ra8_eswcksel_pll1q
PLL1Q.
@ k_ra8_eswcksel_pll2r
PLL2R.
@ k_ra8_eswcksel_pll2p
PLL2P.
static volatile uint8_t * ra8_sys_oscsf(void)
Get pointer to the 8-bit OSCSF (oscillation stabilisation) register.
static volatile uint8_t * ra8_sys_usb60ckcr(void)
Get pointer to the 8-bit USB60CKCR (USBHS 60MHz source select).
@ k_ra8_system_base_addr
R_SYSTEM.
ra8_usbcksel_t
USBCKCR.USBCKSEL source codes (RA8D2 mapping).
@ k_ra8_usbcksel_pll2q
PLL2Q.
@ k_ra8_usbcksel_pll1p
PLL1P.
@ k_ra8_usbcksel_main
Main XTAL.
@ k_ra8_usbcksel_pll2r
PLL2R.
@ k_ra8_usbcksel_pll2p
PLL2P.
@ k_ra8_usbcksel_hoco
HOCO.
@ k_ra8_usbcksel_pll1q
PLL1Q.
@ k_ra8_usbcksel_pll1r
PLL1R.
ra8_eswckcr_bit_t
Bit positions in ESWCKCR.
@ k_ra8_eswckcr_shift_sel
CKSEL field starts at bit 0.
@ k_ra8_eswckcr_mask_sel
CKSEL field is 4 bits wide.
@ k_ra8_eswckcr_bit_sreq
CKSREQ – request switch.
@ k_ra8_eswckcr_bit_srdy
CKSRDY – handshake ready.
static volatile uint8_t * ra8_sys_eswckdivcr(void)
Get pointer to the 8-bit ESWCKDIVCR (ESWCLK divider; 4-bit CKDIV field).
static volatile uint8_t * ra8_sys_sckscr(void)
Get pointer to the 8-bit SCKSCR register.
static volatile uint32_t * ra8_sys_rstsr1(void)
Get pointer to the 32-bit RSTSR1 register.
static volatile uint32_t * ra8_sys_sckdivcr(void)
Get pointer to the 32-bit SCKDIVCR register.
static volatile uint32_t * ra8_sys_pllccr(void)
Get pointer to the 32-bit PLLCCR register.
static volatile uint16_t * ra8_sys_prcr(void)
Get pointer to the 16-bit PRCR register.
static volatile uint8_t * ra8_sys_scickdivcr(void)
Get pointer to the 8-bit SCICKDIVCR register (SCICLK divider).
ra8_pdctreswm_bit_t
Bit positions in PDCTRESWM (ESWM power-domain control).
@ k_ra8_pdctr_bit_pdpgsf
Read-only: power-gating status flag.
@ k_ra8_pdctr_bit_pdcsf
Read-only: power-control status flag.
@ k_ra8_pdctr_bit_pdde
1 = power disabled, 0 = power enabled.
ra8_vscr_bit_t
Bit masks in VSCR (Voltage Scaling Control Register).
@ k_ra8_vscr_bit_vscm
VSCM bit mask (write 1 = not-high-V).
@ k_ra8_vscr_bit_vscmtsf
VSCMTSF transition-in-flight mask.
ra8_usbckcr_bit_t
USBCKCR / USB60CKCR bit positions (HUM Ch 9).
@ k_ra8_usbckcr_shift_sel
USBCKSEL field starts at bit 0.
@ k_ra8_usbckcr_mask_sel
USBCKSEL field is 4 bits wide.
@ k_ra8_usbckcr_bit_srdy
USBCKSRDY – handshake ready.
@ k_ra8_usbckcr_bit_sreq
USBCKSREQ – request switch.
static volatile uint8_t * ra8_sys_canfdckdivcr(void)
Get pointer to the 8-bit CANFDCKDIVCR (CANFD core clock divider).
ra8_rstsr0_bit_t
Reset Status Register 0 bit positions.
@ k_ra8_rstsr0_bit_lvd0
Voltage-monitor 0 reset.
@ k_ra8_rstsr0_bit_lvd1
Voltage-monitor 1 reset.
@ k_ra8_rstsr0_bit_porf
Power-on reset.
@ k_ra8_rstsr0_bit_lvd2
Voltage-monitor 2 reset.
ra8_moscr_bit_t
Bit masks in MOSCCR (Main Clock Oscillator Control Register).
@ k_ra8_moscr_mostp_mask
MOSTP – 0 starts XTAL, 1 stops it.