System Control (SYSC) register layout for the Renesas RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_system_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_system_addr_t : uintptr_t { k_ra8_system_base_addr = 0x4001E000UL }
enum	ra8_system_offset_t : uint16_t { k_ra8_sys_off_vscr = 0x014U , k_ra8_sys_off_sckdivcr = 0x020U , k_ra8_sys_off_sckdivcr2 = 0x024U , k_ra8_sys_off_sckscr = 0x026U , k_ra8_sys_off_pllcr = 0x02AU , k_ra8_sys_off_moscr = 0x032U , k_ra8_sys_off_hococr = 0x036U , k_ra8_sys_off_oscsf = 0x03CU , k_ra8_sys_off_pll2cr = 0x04AU , k_ra8_sys_off_pllccr2 = 0x04CU , k_ra8_sys_off_pll2ccr2 = 0x04EU , k_ra8_sys_off_scickdivcr = 0x054U , k_ra8_sys_off_scickcr = 0x055U , k_ra8_sys_off_eswckdivcr = 0x0D5U , k_ra8_sys_off_eswpckdivcr = 0x0D6U , k_ra8_sys_off_eswckcr = 0x0DBU , k_ra8_sys_off_eswpckcr = 0x0DCU , k_ra8_sys_off_usbckdivcr = 0x06CU , k_ra8_sys_off_octackdivcr = 0x06DU , k_ra8_sys_off_canfdckdivcr = 0x06EU , k_ra8_sys_off_usb60ckdivcr = 0x06FU , k_ra8_sys_off_usbckcr = 0x074U , k_ra8_sys_off_octackcr = 0x075U , k_ra8_sys_off_canfdckcr = 0x076U , k_ra8_sys_off_usb60ckcr = 0x077U , k_ra8_sys_off_moscwtcr = 0x0A2U , k_ra8_sys_off_pdctreswm = 0x118U , k_ra8_sys_off_pllccr = 0x0ACU , k_ra8_sys_off_rstsr1 = 0x0C0U , k_ra8_sys_off_pll2ccr = 0x0C8U , k_ra8_sys_off_prcr = 0x3FAU , k_ra8_sys_off_rstsr0 = 0xA40U , k_ra8_sys_off_rstsr2 = 0xA44U , k_ra8_sys_off_lococr = 0x400U , k_ra8_sys_off_sosccr = 0xC00U , k_ra8_sys_off_somcr = 0xC01U }
enum	ra8_vscr_bit_t : uint32_t { k_ra8_vscr_bit_vscm = (1UL << 0U) , k_ra8_vscr_bit_vscmtsf = (1UL << 4U) }
	Bit masks in VSCR (Voltage Scaling Control Register). More...
enum	ra8_moscr_bit_t : uint8_t { k_ra8_moscr_mostp_mask = (1U << 0U) }
	Bit masks in MOSCCR (Main Clock Oscillator Control Register). More...
enum	ra8_sosccr_bit_t : uint8_t { k_ra8_sosccr_sostp_mask = (1U << 0U) }
	Bit mask in SOSCCR (Sub-Clock Oscillator Control Register). More...
enum	ra8_somcr_drv_t : uint8_t { k_ra8_somcr_drv_standard = 0x0U , k_ra8_somcr_drv_lp1 = 0x1U , k_ra8_somcr_drv_lp2 = 0x2U , k_ra8_somcr_drv_lp3 = 0x3U }
	SOMCR.SODRV[1:0] sub-clock drive-capability codes. More...
enum	ra8_lococr_bit_t : uint8_t { k_ra8_lococr_lcstp_mask = (1U << 0U) }
	Bit mask in LOCOCR (Low-Speed On-Chip Oscillator Control Register). More...
enum	ra8_oscsf_bit_t : uint8_t { k_ra8_oscsf_bit_hocosf = 0U , k_ra8_oscsf_bit_moscsf = 3U , k_ra8_oscsf_bit_pll1sf = 5U , k_ra8_oscsf_bit_pll2sf = 6U }
	Oscillation Stabilization Flag bit positions. More...
enum	ra8_prcr_t : uint16_t { k_ra8_prcr_key = 0xA500U , k_ra8_prcr_grp0_cgc = 0x0001U , k_ra8_prcr_grp1_lpm = 0x0002U , k_ra8_prcr_grp3_pvd = 0x0008U , k_ra8_prcr_grp4_sar = 0x0010U , k_ra8_prcr_grp5_rst = 0x0020U , k_ra8_prcr_unlock_cgc , k_ra8_prcr_unlock_lpm , k_ra8_prcr_unlock_pvd , k_ra8_prcr_unlock_sar , k_ra8_prcr_unlock_rst , k_ra8_prcr_lock_all = k_ra8_prcr_key }
	Values to write to PRCR to unlock / lock protection groups. More...
enum	ra8_rstsr0_bit_t : uint8_t { k_ra8_rstsr0_bit_porf = 0U , k_ra8_rstsr0_bit_lvd0 = 1U , k_ra8_rstsr0_bit_lvd1 = 2U , k_ra8_rstsr0_bit_lvd2 = 3U }
	Reset Status Register 0 bit positions. More...
enum	ra8_rstsr2_bit_t : uint8_t { k_ra8_rstsr2_bit_cwsf = 0U , k_ra8_rstsr2_bit_iwdtrf = 1U , k_ra8_rstsr2_bit_wdtrf = 2U , k_ra8_rstsr2_bit_swrf = 3U }
	Reset Status Register 2 bit positions. More...
enum	ra8_usbckcr_bit_t : uint8_t { k_ra8_usbckcr_shift_sel = 0U , k_ra8_usbckcr_mask_sel = 0x0FU , k_ra8_usbckcr_bit_sreq = 6U , k_ra8_usbckcr_bit_srdy = 7U }
	USBCKCR / USB60CKCR bit positions (HUM Ch 9). More...
enum	ra8_usbcksel_t : uint8_t { k_ra8_usbcksel_hoco = 0U , k_ra8_usbcksel_main = 3U , k_ra8_usbcksel_pll1p = 5U , k_ra8_usbcksel_pll2p = 6U , k_ra8_usbcksel_pll1q = 7U , k_ra8_usbcksel_pll1r = 8U , k_ra8_usbcksel_pll2q = 9U , k_ra8_usbcksel_pll2r = 10U }
	USBCKCR.USBCKSEL source codes (RA8D2 mapping). More...
enum	ra8_eswcksel_t : uint8_t { k_ra8_eswcksel_hoco = 0U , k_ra8_eswcksel_moco = 1U , k_ra8_eswcksel_loco = 2U , k_ra8_eswcksel_main = 3U , k_ra8_eswcksel_pll1p = 5U , k_ra8_eswcksel_pll2p = 6U , k_ra8_eswcksel_pll1q = 7U , k_ra8_eswcksel_pll1r = 8U , k_ra8_eswcksel_pll2q = 9U , k_ra8_eswcksel_pll2r = 10U }
	ESWCKCR.CKSEL source codes (RA8D2 mapping). More...
enum	ra8_eswckcr_bit_t : uint8_t { k_ra8_eswckcr_shift_sel = 0U , k_ra8_eswckcr_mask_sel = 0x0FU , k_ra8_eswckcr_bit_sreq = 6U , k_ra8_eswckcr_bit_srdy = 7U }
	Bit positions in ESWCKCR. More...
enum	ra8_pdctreswm_bit_t : uint8_t { k_ra8_pdctr_bit_pdde = 0U , k_ra8_pdctr_bit_pdcsf = 6U , k_ra8_pdctr_bit_pdpgsf = 7U }
	Bit positions in PDCTRESWM (ESWM power-domain control). More...

Functions
static volatile uint32_t *	ra8_sys_vscr (void)
	Get pointer to the 32-bit VSCR register (voltage scaling control).
static volatile uint32_t *	ra8_sys_sckdivcr (void)
	Get pointer to the 32-bit SCKDIVCR register.
static volatile uint8_t *	ra8_sys_scickdivcr (void)
	Get pointer to the 8-bit SCICKDIVCR register (SCICLK divider).
static volatile uint8_t *	ra8_sys_scickcr (void)
	Get pointer to the 8-bit SCICKCR register (SCICLK source select).
static volatile uint8_t *	ra8_sys_sckscr (void)
	Get pointer to the 8-bit SCKSCR register.
static volatile uint8_t *	ra8_sys_hococr (void)
	Get pointer to the 8-bit HOCOCR register.
static volatile uint8_t *	ra8_sys_sosccr (void)
	Get pointer to the 8-bit SOSCCR register (sub-clock oscillator stop).
static volatile uint8_t *	ra8_sys_somcr (void)
	Get pointer to the 8-bit SOMCR register (sub-clock oscillator mode).
static volatile uint8_t *	ra8_sys_lococr (void)
	Get pointer to the 8-bit LOCOCR register (LOCO stop control).
static volatile uint8_t *	ra8_sys_moscwtcr (void)
	Get pointer to the 8-bit MOSCWTCR register.
static volatile uint32_t *	ra8_sys_pllccr (void)
	Get pointer to the 32-bit PLLCCR register.
static volatile uint16_t *	ra8_sys_pllccr2 (void)
	Get pointer to the 16-bit PLLCCR2 register (PLL1 output dividers).
static volatile uint32_t *	ra8_sys_pll2ccr (void)
	Get pointer to the 32-bit PLL2CCR register (PLL2 input/mul/source).
static volatile uint8_t *	ra8_sys_pll2cr (void)
	Get pointer to the 8-bit PLL2CR register (PLL2 stop control).
static volatile uint16_t *	ra8_sys_pll2ccr2 (void)
	Get pointer to the 16-bit PLL2CCR2 register (PLL2 output dividers).
static volatile uint8_t *	ra8_sys_oscsf (void)
	Get pointer to the 8-bit OSCSF (oscillation stabilisation) register.
static volatile uint8_t *	ra8_sys_pllcr (void)
	Get pointer to the 8-bit PLLCR register (PLL enable/stop).
static volatile uint16_t *	ra8_sys_sckdivcr2 (void)
	Get pointer to the 16-bit SCKDIVCR2 register.
static volatile uint32_t *	ra8_sys_rstsr1 (void)
	Get pointer to the 32-bit RSTSR1 register.
static volatile uint16_t *	ra8_sys_prcr (void)
	Get pointer to the 16-bit PRCR register.
static volatile uint8_t *	ra8_sys_rstsr0 (void)
	Get pointer to the 8-bit RSTSR0 register.
static volatile uint8_t *	ra8_sys_rstsr2 (void)
	Get pointer to the 8-bit RSTSR2 register.
static volatile uint8_t *	ra8_sys_usbckdivcr (void)
	Get pointer to the 8-bit USBCKDIVCR (USB clock divider).
static volatile uint8_t *	ra8_sys_usbckcr (void)
	Get pointer to the 8-bit USBCKCR (USB-FS source select).
static volatile uint8_t *	ra8_sys_usb60ckcr (void)
	Get pointer to the 8-bit USB60CKCR (USBHS 60MHz source select).
static volatile uint8_t *	ra8_sys_usb60ckdivcr (void)
	Get pointer to the 8-bit USB60CKDIVCR (USBHS 60MHz divider).
static volatile uint8_t *	ra8_sys_canfdckcr (void)
	Get pointer to the 8-bit CANFDCKCR (CANFD core clock source select).
static volatile uint8_t *	ra8_sys_canfdckdivcr (void)
	Get pointer to the 8-bit CANFDCKDIVCR (CANFD core clock divider).
static volatile uint8_t *	ra8_sys_octackcr (void)
	Get pointer to the 8-bit OCTACKCR (Octal-SPI clock source select).
static volatile uint8_t *	ra8_sys_octackdivcr (void)
	Get pointer to the 8-bit OCTACKDIVCR (Octal-SPI clock divider).
static volatile uint8_t *	ra8_sys_eswckcr (void)
	Get pointer to the 8-bit ESWCKCR (Ethernet Switch / RMAC clock source).
static volatile uint8_t *	ra8_sys_eswckdivcr (void)
	Get pointer to the 8-bit ESWCKDIVCR (ESWCLK divider; 4-bit CKDIV field).
static volatile uint8_t *	ra8_sys_eswpckcr (void)
	Get pointer to the 8-bit ESWPCKCR (Ethernet-PHY clock source).
static volatile uint8_t *	ra8_sys_eswpckdivcr (void)
	Get pointer to the 8-bit ESWPCKDIVCR (ESWPHYCLK divider; 4-bit CKDIV field).
static volatile uint8_t *	ra8_sys_pdctreswm (void)
	Get pointer to the 8-bit PDCTRESWM (ESWM power-domain control).
static void	ra8_sys_prcr_unlock_cgc (void)
	Unlock the CGC + LVD protection group so CGC registers can be written.
static void	ra8_sys_prcr_lock_all (void)
	Re-lock every protection group (write password with all group bits clear).

Detailed Description

System Control (SYSC) register layout for the Renesas RA8D2.

Covers the System Control block at 0x4001E000. The SYSC block owns reset-cause reporting, software reset, protection-register unlock, and (along with CGC) clock-source selection.

Map (partial – only the registers this firmware touches)

Offset	Reg	Purpose
0x020	SCKDIVCR	System clock divider control
0x026	SCKSCR	System clock source select
0x036	HOCOCR	High-speed on-chip oscillator control
0x0A2	MOSCWTCR	Main clock oscillator wait control
0x0AC	PLLCCR	PLL1 clock control
0x0C0	RSTSR1	Reset status register 1
0x3FA	PRCR	Protection register (write with 0xA500 mask)
0xA40	RSTSR0	Reset status register 0
0xA44	RSTSR2	Reset status register 2

The full R_SYSTEM block spans 3456 bytes and contains dozens of other registers (RAM wait-state control, LVD, temperature monitor, VBAT, etc.). We expose only the subset the firmware actually uses and add new fields as we need them. This keeps the header small and makes every extension an explicit, reviewed change.

PRCR unlock sequence

Most CGC and LVD registers are protected. Write 0xA501 to unlock group 0 (CGC + LVD) before changing them, and 0xA500 to re-lock when done. The upper byte 0xA5 is the password; the low bit is the protection-enable for that group.

See the Hardware User's Manual section 12 ("Register Write Protection") for the full table.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_system_regs.h.

Enumeration Type Documentation

◆ ra8_eswckcr_bit_t

enum ra8_eswckcr_bit_t : uint8_t

Bit positions in ESWCKCR.

Enumerator
k_ra8_eswckcr_shift_sel	CKSEL field starts at bit 0.
k_ra8_eswckcr_mask_sel	CKSEL field is 4 bits wide.
k_ra8_eswckcr_bit_sreq	CKSREQ – request switch.
k_ra8_eswckcr_bit_srdy	CKSRDY – handshake ready.

Definition at line 619 of file ra8_system_regs.h.

◆ ra8_eswcksel_t

enum ra8_eswcksel_t : uint8_t

ESWCKCR.CKSEL source codes (RA8D2 mapping).

Layout matches USBCKCR / USB60CKCR – the CGC uses the same peripheral-clock-source enum for every CKSEL field. The Renesas FSP confirms this in bsp_clocks.c (single BSP_CLOCKS_SOURCE_CLOCK_* enum drives every peripheral clock select).

Enumerator
k_ra8_eswcksel_hoco	HOCO.
k_ra8_eswcksel_moco	MOCO.
k_ra8_eswcksel_loco	LOCO.
k_ra8_eswcksel_main	Main XTAL.
k_ra8_eswcksel_pll1p	PLL1P (preferred for 125 MHz ESWCLK).
k_ra8_eswcksel_pll2p	PLL2P.
k_ra8_eswcksel_pll1q	PLL1Q.
k_ra8_eswcksel_pll1r	PLL1R.
k_ra8_eswcksel_pll2q	PLL2Q.
k_ra8_eswcksel_pll2r	PLL2R.

Definition at line 602 of file ra8_system_regs.h.

◆ ra8_lococr_bit_t

enum ra8_lococr_bit_t : uint8_t

Bit mask in LOCOCR (Low-Speed On-Chip Oscillator Control Register).

LCSTP at bit 0: write 0 to operate the internal ~32.768 kHz LOCO, 1 to stop it. Reset value is 0 (running), so the LOCO is normally already available as a crystal-free RTC count source (HUM Ch 9.2.15 "LOCOCR : Low-Speed On-Chip Oscillator Control Register" p 339).

Enumerator
k_ra8_lococr_lcstp_mask	LCSTP – 0 operates LOCO, 1 stops it.

Definition at line 181 of file ra8_system_regs.h.

◆ ra8_moscr_bit_t

enum ra8_moscr_bit_t : uint8_t

Bit masks in MOSCCR (Main Clock Oscillator Control Register).

MOSTP at bit 0: write 0 to start the main oscillator, 1 to stop it (HUM Ch 9.2.13).

Enumerator
k_ra8_moscr_mostp_mask	MOSTP – 0 starts XTAL, 1 stops it.

Definition at line 134 of file ra8_system_regs.h.

◆ ra8_oscsf_bit_t

enum ra8_oscsf_bit_t : uint8_t

Oscillation Stabilization Flag bit positions.

Each bit is set by hardware when the corresponding oscillator has stabilised. The CGC driver polls these between starting an oscillator and using it as the system-clock source.

Enumerator
k_ra8_oscsf_bit_hocosf	HOCO stabilisation flag.
k_ra8_oscsf_bit_moscsf	Main oscillator stab flag.
k_ra8_oscsf_bit_pll1sf	PLL1 stabilisation flag.
k_ra8_oscsf_bit_pll2sf	PLL2 stabilisation flag.

Definition at line 194 of file ra8_system_regs.h.

◆ ra8_pdctreswm_bit_t

enum ra8_pdctreswm_bit_t : uint8_t

Bit positions in PDCTRESWM (ESWM power-domain control).

HUM Ch 9.2 "General Power Domain ESWM Control Register" + FSP R_SYSTEM_PDCTRESWM_PDDE_Pos. The PDDE bit is a write-1-to-DISABLE (counter-intuitive but matches the FSP comment "Turn on the domain power" by writing PDDE = 0). PDCSF / PDPGSF are read-only status flags that go to 0 once the requested transition completes.

Without PDDE = 0 the ESWM peripheral domain stays power-gated and the per-port RMAC / ETHA register windows read back 0 and silently drop every write – observed on EK-RA8D2 hardware.

Enumerator
k_ra8_pdctr_bit_pdde	1 = power disabled, 0 = power enabled.
k_ra8_pdctr_bit_pdcsf	Read-only: power-control status flag.
k_ra8_pdctr_bit_pdpgsf	Read-only: power-gating status flag.

Definition at line 691 of file ra8_system_regs.h.

◆ ra8_prcr_t

enum ra8_prcr_t : uint16_t

Values to write to PRCR to unlock / lock protection groups.

k_ra8_prcr_key is the mandatory 0xA5 password in the upper byte. OR with one of the group bits to enable writes to that group (counter-intuitive – bit set = unlocked), then write back with the group bit cleared to relock.

Group membership is HUM Ch 13.1 Table 13.1 "Association between PRCR bits and use of registers to be protected" p 520-521; the bit positions are HUM Ch 13.2.1 "PRCR_S : Protect Register for Secure" p 522. Bit 2 and bits 7:6 are reserved (read as 0, write 0).

A write to a protected register while its group is locked is silently discarded – no fault, no status bit. Every driver that touches a register named in Table 13.1 must therefore wrap the write in RA8_PROTECTED_WRITE with the matching group, or it will appear to work and change nothing.

Enumerator
k_ra8_prcr_key	Password in upper byte.
k_ra8_prcr_grp0_cgc	PRC0 @ bit 0: clock generation circuit.
k_ra8_prcr_grp1_lpm	PRC1 @ bit 1: low-power modes + VBATT backup.
k_ra8_prcr_grp3_pvd	PRC3 @ bit 3: PVD + VBATTMNSELR.
k_ra8_prcr_grp4_sar	PRC4 @ bit 4: security/privilege attribution.
k_ra8_prcr_grp5_rst	PRC5 @ bit 5: reset control.
k_ra8_prcr_unlock_cgc	RA8 prcr unlock cgc.
k_ra8_prcr_unlock_lpm	RA8 prcr unlock lpm.
k_ra8_prcr_unlock_pvd	RA8 prcr unlock pvd.
k_ra8_prcr_unlock_sar	RA8 prcr unlock sar.
k_ra8_prcr_unlock_rst	RA8 prcr unlock rst.
k_ra8_prcr_lock_all	RA8 prcr lock all.

Definition at line 227 of file ra8_system_regs.h.

◆ ra8_rstsr0_bit_t

enum ra8_rstsr0_bit_t : uint8_t

Reset Status Register 0 bit positions.

Set by hardware when a reset of the corresponding cause occurred. Cleared by software (write 0 after unlocking PRCR group 0).

Enumerator
k_ra8_rstsr0_bit_porf	Power-on reset.
k_ra8_rstsr0_bit_lvd0	Voltage-monitor 0 reset.
k_ra8_rstsr0_bit_lvd1	Voltage-monitor 1 reset.
k_ra8_rstsr0_bit_lvd2	Voltage-monitor 2 reset.

Definition at line 260 of file ra8_system_regs.h.

◆ ra8_rstsr2_bit_t

enum ra8_rstsr2_bit_t : uint8_t

Reset Status Register 2 bit positions.

Enumerator
k_ra8_rstsr2_bit_cwsf	Cold / warm start flag.
k_ra8_rstsr2_bit_iwdtrf	IWDT reset.
k_ra8_rstsr2_bit_wdtrf	WDT reset.
k_ra8_rstsr2_bit_swrf	Software reset.

Definition at line 271 of file ra8_system_regs.h.

◆ ra8_somcr_drv_t

enum ra8_somcr_drv_t : uint8_t

SOMCR.SODRV[1:0] sub-clock drive-capability codes.

Selects the drive strength feeding the 32.768 kHz crystal. Standard (12.5 pF) is the cold-reset default and matches the EK-RA8D2 watch crystal. SOMCR must be written while SOSCCR.SOSTP is 1 (SOSC stopped) (HUM Ch 9.2.29 "SOMCR : Sub-Clock Oscillator Mode Control Register" p 351).

Enumerator
k_ra8_somcr_drv_standard	Standard drive (12.5 pF).
k_ra8_somcr_drv_lp1	Low-power mode 1 (9 pF).
k_ra8_somcr_drv_lp2	Low-power mode 2 (7 pF).
k_ra8_somcr_drv_lp3	Low-power mode 3 (4 pF).

Definition at line 164 of file ra8_system_regs.h.

◆ ra8_sosccr_bit_t

enum ra8_sosccr_bit_t : uint8_t

Bit mask in SOSCCR (Sub-Clock Oscillator Control Register).

SOSTP at bit 0: write 0 to operate the 32.768 kHz sub-clock crystal oscillator, 1 to stop it. Reset value is 1 (stopped). Set SOMCR before clearing SOSTP, then wait the sub-clock stabilization time (t_SUBOSCWT) before using the clock (HUM Ch 9.2.14 "SOSCCR : Sub-Clock Oscillator Control Register" p 339).

Enumerator
k_ra8_sosccr_sostp_mask	SOSTP – 0 operates SOSC, 1 stops it.

Definition at line 149 of file ra8_system_regs.h.

◆ ra8_system_addr_t

enum ra8_system_addr_t : uintptr_t

Enumerator
k_ra8_system_base_addr	R_SYSTEM.

Definition at line 58 of file ra8_system_regs.h.

◆ ra8_system_offset_t

enum ra8_system_offset_t : uint16_t

Enumerator
k_ra8_sys_off_vscr	VSCR voltage scaling control (32-bit).
k_ra8_sys_off_sckdivcr	SCKDIVCR (32-bit).
k_ra8_sys_off_sckdivcr2	SCKDIVCR2 (16-bit).
k_ra8_sys_off_sckscr	SCKSCR (8-bit).
k_ra8_sys_off_pllcr	PLLCR (8-bit).
k_ra8_sys_off_moscr	MOSCCR (8-bit).
k_ra8_sys_off_hococr	HOCOCR (8-bit).
k_ra8_sys_off_oscsf	OSCSF (8-bit).
k_ra8_sys_off_pll2cr	PLL2CR – PLL2 stop control (8-bit).
k_ra8_sys_off_pllccr2	PLLCCR2 – PLL1 output dividers (16-bit).
k_ra8_sys_off_pll2ccr2	PLL2CCR2 – PLL2 output dividers (16-bit).
k_ra8_sys_off_scickdivcr	SCICKDIVCR (8-bit).
k_ra8_sys_off_scickcr	SCICKCR (8-bit).
k_ra8_sys_off_eswckdivcr	ESWCKDIVCR (8-bit) – ESWM module clock div.
k_ra8_sys_off_eswpckdivcr	ESWPCKDIVCR (8-bit) – ESWM-PHY clock div.
k_ra8_sys_off_eswckcr	ESWCKCR (8-bit) – ESWM clock source.
k_ra8_sys_off_eswpckcr	ESWPCKCR (8-bit) – ESWM-PHY clock source.
k_ra8_sys_off_usbckdivcr	USBCKDIVCR (8-bit) – USB-FS clock divider.
k_ra8_sys_off_octackdivcr	OCTACKDIVCR (8-bit) – HUM Ch 9.2.40 p 357.
k_ra8_sys_off_canfdckdivcr	CANFDCKDIVCR (8-bit) – HUM Ch 9.2.41 p 363.
k_ra8_sys_off_usb60ckdivcr	USB60CKDIVCR (8-bit) – USBHS 60MHz divider.
k_ra8_sys_off_usbckcr	USBCKCR (8-bit) – USB-FS clock src.
k_ra8_sys_off_octackcr	OCTACKCR (8-bit) – HUM Ch 9.2.45 p 360.
k_ra8_sys_off_canfdckcr	CANFDCKCR (8-bit) – HUM Ch 9.2.46 p 366.
k_ra8_sys_off_usb60ckcr	USB60CKCR (8-bit) – USBHS 60MHz src.
k_ra8_sys_off_moscwtcr	MOSCWTCR (8-bit).
k_ra8_sys_off_pdctreswm	PDCTRESWM (8-bit) – ESWM power-domain control.
k_ra8_sys_off_pllccr	PLLCCR (32-bit).
k_ra8_sys_off_rstsr1	RSTSR1 (32-bit).
k_ra8_sys_off_pll2ccr	PLL2CCR – input/mul/source (32-bit, HUM Ch 9.2.9).
k_ra8_sys_off_prcr	PRCR (16-bit).
k_ra8_sys_off_rstsr0	RSTSR0 (8-bit).
k_ra8_sys_off_rstsr2	RSTSR2 (8-bit).
k_ra8_sys_off_lococr	LOCOCR (8-bit) – HUM Ch 9.2.15 p 339.
k_ra8_sys_off_sosccr	SOSCCR (8-bit) – HUM Ch 9.2.14 p 339.
k_ra8_sys_off_somcr	SOMCR (8-bit) – HUM Ch 9.2.29 p 351.

Definition at line 67 of file ra8_system_regs.h.

◆ ra8_usbckcr_bit_t

enum ra8_usbckcr_bit_t : uint8_t

USBCKCR / USB60CKCR bit positions (HUM Ch 9).

Cited from FSP CMSIS device header R7KA8D2KF_core0.h. USBCKSEL[3:0] selects the source clock; USBCKSREQ requests a switch; USBCKSRDY is the read-only handshake-done flag.

Enumerator
k_ra8_usbckcr_shift_sel	USBCKSEL field starts at bit 0.
k_ra8_usbckcr_mask_sel	USBCKSEL field is 4 bits wide.
k_ra8_usbckcr_bit_sreq	USBCKSREQ – request switch.
k_ra8_usbckcr_bit_srdy	USBCKSRDY – handshake ready.

Definition at line 494 of file ra8_system_regs.h.

◆ ra8_usbcksel_t

enum ra8_usbcksel_t : uint8_t

USBCKCR.USBCKSEL source codes (RA8D2 mapping).

Enumerator
k_ra8_usbcksel_hoco	HOCO.
k_ra8_usbcksel_main	Main XTAL.
k_ra8_usbcksel_pll1p	PLL1P.
k_ra8_usbcksel_pll2p	PLL2P.
k_ra8_usbcksel_pll1q	PLL1Q.
k_ra8_usbcksel_pll1r	PLL1R.
k_ra8_usbcksel_pll2q	PLL2Q.
k_ra8_usbcksel_pll2r	PLL2R.

Definition at line 505 of file ra8_system_regs.h.

◆ ra8_vscr_bit_t

enum ra8_vscr_bit_t : uint32_t

Bit masks in VSCR (Voltage Scaling Control Register).

On RA8 Gen2 silicon, software must drop the core to the "not high voltage" range (VSCM = 1) before lifting PLL1 above its default rate, then poll VSCMTSF until the transition completes (FSP bsp_clocks.c, FSP CMSIS device header R7KA8D2KF_core0.h).

Bit positions inside the 32-bit register:

VSCM = bit 0 (write 1 to enter not-high-voltage mode)
VSCMTSF = bit 4 (read-only, set while transition is in flight)

Enumerator
k_ra8_vscr_bit_vscm	VSCM bit mask (write 1 = not-high-V).
k_ra8_vscr_bit_vscmtsf	VSCMTSF transition-in-flight mask.

Definition at line 121 of file ra8_system_regs.h.

Function Documentation

◆ ra8_sys_canfdckcr()

volatile uint8_t * ra8_sys_canfdckcr ( void )

inlinestatic

Get pointer to the 8-bit CANFDCKCR (CANFD core clock source select).

HUM Ch 9.2.46 "CANFDCKCR : CANFD Core Clock Control Register" p 366. Layout matches USBCKCR: CANFDCKSEL[3:0] at [3:0], CANFDCKSREQ at bit 6, CANFDCKSRDY at bit 7. Reset value 0x01 selects MOCO.

Definition at line 549 of file ra8_system_regs.h.

References k_ra8_sys_off_canfdckcr, and k_ra8_system_base_addr.

Referenced by internal_canfd_clock_block_init(), and internal_wait_canfdcksrdy().

◆ ra8_sys_canfdckdivcr()

volatile uint8_t * ra8_sys_canfdckdivcr ( void )

inlinestatic

Get pointer to the 8-bit CANFDCKDIVCR (CANFD core clock divider).

HUM Ch 9.2.41 "CANFDCKDIVCR : CANFD Core Clock Division Control Register" p 363. CANFDCKDIV[3:0] in bits [3:0].

Definition at line 560 of file ra8_system_regs.h.

References k_ra8_sys_off_canfdckdivcr, and k_ra8_system_base_addr.

Referenced by internal_canfd_clock_block_init().

◆ ra8_sys_eswckcr()

volatile uint8_t * ra8_sys_eswckcr ( void )

inlinestatic

Get pointer to the 8-bit ESWCKCR (Ethernet Switch / RMAC clock source).

HUM Ch 9.2 "ESWCKCR" – 8-bit register, layout identical to USB60CKCR:

CKSEL[3:0] : clock source code (same enum as ra8_usbcksel_t).
CKSREQ bit 6 : write 1 to request a switch.
CKSRDY bit 7 : read-only handshake-done flag.

The ESWCLK feeds the Ethernet Switch Module (ESWM) and the per-port RMAC PHY-management clock divider MPIC.PSMCS. Without a valid ESWCLK the MDC line never toggles at the rate the PHY expects (max 2.5 MHz for Clause-22).

Definition at line 640 of file ra8_system_regs.h.

References k_ra8_sys_off_eswckcr, and k_ra8_system_base_addr.

Referenced by internal_eswclk_program_cks().

◆ ra8_sys_eswckdivcr()

volatile uint8_t * ra8_sys_eswckdivcr ( void )

inlinestatic

Get pointer to the 8-bit ESWCKDIVCR (ESWCLK divider; 4-bit CKDIV field).

Definition at line 646 of file ra8_system_regs.h.

References k_ra8_sys_off_eswckdivcr, and k_ra8_system_base_addr.

Referenced by internal_eswclk_program_cks().

◆ ra8_sys_eswpckcr()

volatile uint8_t * ra8_sys_eswpckcr ( void )

inlinestatic

Get pointer to the 8-bit ESWPCKCR (Ethernet-PHY clock source).

ESWPHYCLK is the high-speed clock fed into the per-port RMAC pin pad timing (in addition to ESWCLK feeding the MDC divider). Without this clock running, the entire RMAC / ETHA register block reads back as 0 and writes are silently dropped – exactly the failure mode seen when only ESWCKCR is programmed but ESWPCKCR is left at its reset default of MOCO/1 ~= 8 MHz. Layout identical to ESWCKCR (same ra8_eswckcr_bit_t shifts and ra8_eswcksel_t source enum).

Definition at line 664 of file ra8_system_regs.h.

References k_ra8_sys_off_eswpckcr, and k_ra8_system_base_addr.

Referenced by internal_eswclk_program_cks().

◆ ra8_sys_eswpckdivcr()

volatile uint8_t * ra8_sys_eswpckdivcr ( void )

inlinestatic

Get pointer to the 8-bit ESWPCKDIVCR (ESWPHYCLK divider; 4-bit CKDIV field).

Definition at line 670 of file ra8_system_regs.h.

References k_ra8_sys_off_eswpckdivcr, and k_ra8_system_base_addr.

Referenced by internal_eswclk_program_cks().

◆ ra8_sys_hococr()

volatile uint8_t * ra8_sys_hococr ( void )

inlinestatic

Get pointer to the 8-bit HOCOCR register.

Definition at line 323 of file ra8_system_regs.h.

References k_ra8_sys_off_hococr, and k_ra8_system_base_addr.

Referenced by priv_ra8_cgc_ensure_hoco_running_for_usb_ck(), ra8_cgc_usbfs_clock_enable(), and ra8_cgc_use_hoco().

◆ ra8_sys_lococr()

volatile uint8_t * ra8_sys_lococr ( void )

inlinestatic

Get pointer to the 8-bit LOCOCR register (LOCO stop control).

Definition at line 341 of file ra8_system_regs.h.

References k_ra8_sys_off_lococr, and k_ra8_system_base_addr.

Referenced by internal_start_count_source().

◆ ra8_sys_moscwtcr()

volatile uint8_t * ra8_sys_moscwtcr ( void )

inlinestatic

Get pointer to the 8-bit MOSCWTCR register.

Definition at line 347 of file ra8_system_regs.h.

References k_ra8_sys_off_moscwtcr, and k_ra8_system_base_addr.

Referenced by internal_start_main_osc().

◆ ra8_sys_octackcr()

volatile uint8_t * ra8_sys_octackcr ( void )

inlinestatic

Get pointer to the 8-bit OCTACKCR (Octal-SPI clock source select).

HUM Ch 9.2.45 "OCTACKCR : Octal-SPI Clock Control Register" p 360. Layout matches USBCKCR / CANFDCKCR: OCTACKSEL[3:0] at [3:0], OCTACKSREQ at bit 6, OCTACKSRDY at bit 7. Reset value 0x01 selects MOCO. Per HUM Ch 11.2.7 MSTPCRB Note 3 (p 444) the OSPI MSTPB16 / MSTPB17 bits must be written AFTER OCTACLK is stable; the SREQ -> SRDY -> SREQ-clear handshake is the documented way to confirm stability.

Definition at line 576 of file ra8_system_regs.h.

References k_ra8_sys_off_octackcr, and k_ra8_system_base_addr.

Referenced by internal_wait_octacksrdy(), and internal_xspi_clock_block_init().

◆ ra8_sys_octackdivcr()

volatile uint8_t * ra8_sys_octackdivcr ( void )

inlinestatic

Get pointer to the 8-bit OCTACKDIVCR (Octal-SPI clock divider).

HUM Ch 9.2.40 "OCTACKDIVCR : Octal-SPI Clock Division Control Register" p 357. OCTACKDIV[3:0] in bits [3:0]; reset value 0 (/1).

Definition at line 586 of file ra8_system_regs.h.

References k_ra8_sys_off_octackdivcr, and k_ra8_system_base_addr.

Referenced by internal_xspi_clock_block_init().

◆ ra8_sys_oscsf()

volatile uint8_t * ra8_sys_oscsf ( void )

inlinestatic

Get pointer to the 8-bit OSCSF (oscillation stabilisation) register.

Definition at line 443 of file ra8_system_regs.h.

References k_ra8_sys_off_oscsf, and k_ra8_system_base_addr.

Referenced by internal_usb60ckcr_switch_to_pll2p_div4(), priv_ra8_cgc_wait_oscsf_clear(), priv_ra8_cgc_wait_oscsf_set(), and ra8_cgc_pll2_enable().

◆ ra8_sys_pdctreswm()

volatile uint8_t * ra8_sys_pdctreswm ( void )

inlinestatic

Get pointer to the 8-bit PDCTRESWM (ESWM power-domain control).

Definition at line 698 of file ra8_system_regs.h.

References k_ra8_sys_off_pdctreswm, and k_ra8_system_base_addr.

Referenced by internal_eswclk_power_on_domain(), and internal_wait_pdctreswm_clear().

◆ ra8_sys_pll2ccr()

volatile uint32_t * ra8_sys_pll2ccr ( void )

inlinestatic

Get pointer to the 32-bit PLL2CCR register (PLL2 input/mul/source).

PLL2CCR layout per RA8D2 HUM Ch 9.2.9 "PLL2CCR : PLL2 Clock Control Register" (offset 0x0C8, 32-bit access):

PL2IDIV [1:0] – input divider (0=/1, 1=/2, 2=/3)
PL2SRCSEL [4] – 0 = Main XTAL, 1 = HOCO
PLL2MULNF [7:6] – fractional multiplier in 0.25 steps
PLL2MUL [16:8] – integer multiplier (9 bits, 0x27..0x12B = x40..x300)
bits 31:17, 5, 3:2 reserved (read 0, write 0)

Note: this register on RA8D2 is 9-bit-MUL wide and located at offset 0x0C8 (NOT 0x048 as in older RA8M1 family parts). The previous accessor used the RA8M1 layout and silently dropped writes on real RA8D2 silicon.

Returns: Pointer to the live PLL2CCR register.

Precondition: Single-threaded init context with PRCR group 0 unlocked.; PLL2 has been stopped (PLL2CR.PLL2STP = 1) before any write.

Postcondition: No mutation; pointer-only accessor.; Pointer aliases live MMIO – caller must use volatile semantics.

Note: Not thread-safe.

Since: 0.1.0

Definition at line 389 of file ra8_system_regs.h.

References k_ra8_sys_off_pll2ccr, and k_ra8_system_base_addr.

Referenced by internal_pll2_program_protected().

◆ ra8_sys_pll2ccr2()

volatile uint16_t * ra8_sys_pll2ccr2 ( void )

inlinestatic

Get pointer to the 16-bit PLL2CCR2 register (PLL2 output dividers).

PLL2CCR2 layout (HUM Ch 9.2.12 "PLL2CCR2 : PLL2 Clock Control Register 2", FSP R_SYSTEM_PLL2CCR2_PL2ODIVx_Pos):

PL2ODIVP [3:0] – PLL2P output divider code
PL2ODIVQ [7:4] – PLL2Q output divider code
PL2ODIVR [11:8] – PLL2R output divider code

Code-to-ratio map matches PLL1's ra8_plodiv_t (ratio - 1 for /1../6, /8 = 7, /9 = 8, /16 = 15).

Returns: Pointer to the live PLL2CCR2 register.

Precondition: Single-threaded init context with PRCR group 0 unlocked.; PLL2 has been stopped before any write.

Postcondition: No mutation; pointer-only accessor.; Pointer aliases live MMIO.

Note: Not thread-safe.

Since: 0.1.0

Definition at line 436 of file ra8_system_regs.h.

References k_ra8_sys_off_pll2ccr2, and k_ra8_system_base_addr.

Referenced by internal_pll2_program_protected().

◆ ra8_sys_pll2cr()

volatile uint8_t * ra8_sys_pll2cr ( void )

inlinestatic

Get pointer to the 8-bit PLL2CR register (PLL2 stop control).

PLL2CR.PLL2STP at bit 0: write 1 to stop PLL2, 0 to run it (HUM Ch 9.2.11 "PLL2CR : PLL2 Control Register"; FSP R_SYSTEM_PLL2CR_PLL2STP_Pos).

Returns: Pointer to the live PLL2CR register.

Precondition: Single-threaded init context with PRCR group 0 unlocked.; CPU is not currently sourced from PLL2 (would self-stall).

Postcondition: No mutation; pointer-only accessor.; Pointer aliases live MMIO.

Note: Not thread-safe.

Since: 0.1.0

Definition at line 410 of file ra8_system_regs.h.

References k_ra8_sys_off_pll2cr, and k_ra8_system_base_addr.

Referenced by internal_pll2_program_protected().

◆ ra8_sys_pllccr()

volatile uint32_t * ra8_sys_pllccr ( void )

inlinestatic

Get pointer to the 32-bit PLLCCR register.

Definition at line 353 of file ra8_system_regs.h.

References k_ra8_sys_off_pllccr, and k_ra8_system_base_addr.

Referenced by internal_program_and_start_pll1().

◆ ra8_sys_pllccr2()

volatile uint16_t * ra8_sys_pllccr2 ( void )

inlinestatic

Get pointer to the 16-bit PLLCCR2 register (PLL1 output dividers).

Definition at line 359 of file ra8_system_regs.h.

References k_ra8_sys_off_pllccr2, and k_ra8_system_base_addr.

Referenced by internal_program_and_start_pll1().

◆ ra8_sys_pllcr()

volatile uint8_t * ra8_sys_pllcr ( void )

inlinestatic

Get pointer to the 8-bit PLLCR register (PLL enable/stop).

Definition at line 449 of file ra8_system_regs.h.

References k_ra8_sys_off_pllcr, and k_ra8_system_base_addr.

Referenced by internal_program_and_start_pll1(), and internal_stop_pll1().

◆ ra8_sys_prcr()

volatile uint16_t * ra8_sys_prcr ( void )

inlinestatic

Get pointer to the 16-bit PRCR register.

Definition at line 468 of file ra8_system_regs.h.

References k_ra8_sys_off_prcr, and k_ra8_system_base_addr.

Referenced by internal_lvd_demo_configure(), ra8_prot_scope_begin(), ra8_sys_prcr_lock_all(), and ra8_sys_prcr_unlock_cgc().

◆ ra8_sys_prcr_lock_all()

void ra8_sys_prcr_lock_all ( void )

inlinestatic

Re-lock every protection group (write password with all group bits clear).

See implementation.

Precondition: Module state is consistent.; Module state is consistent.

Postcondition: Caller-visible state matches the documented contract.; Caller-visible state matches the documented contract.

Note: Not thread-safe unless documented otherwise.

Since: 0.1.0

Definition at line 741 of file ra8_system_regs.h.

References k_ra8_prcr_lock_all, and ra8_sys_prcr().

Referenced by internal_lvd_demo_configure(), and ra8_prot_scope_end().

◆ ra8_sys_prcr_unlock_cgc()

void ra8_sys_prcr_unlock_cgc ( void )

inlinestatic

Unlock the CGC + LVD protection group so CGC registers can be written.

Writes 0xA501 to PRCR. Paired with ra8_sys_prcr_lock_all() once the CGC programming sequence is complete.

Note: Not thread-safe. Call only from single-threaded init or with interrupts masked.

Precondition: Module state is consistent.; Module state is consistent.

Postcondition: Caller-visible state matches the documented contract.; Caller-visible state matches the documented contract.

Since: 0.1.0

Definition at line 725 of file ra8_system_regs.h.

References k_ra8_prcr_unlock_cgc, and ra8_sys_prcr().

◆ ra8_sys_rstsr0()

volatile uint8_t * ra8_sys_rstsr0 ( void )

inlinestatic

Get pointer to the 8-bit RSTSR0 register.

Definition at line 474 of file ra8_system_regs.h.

References k_ra8_sys_off_rstsr0, and k_ra8_system_base_addr.

◆ ra8_sys_rstsr1()

volatile uint32_t * ra8_sys_rstsr1 ( void )

inlinestatic

Get pointer to the 32-bit RSTSR1 register.

Definition at line 462 of file ra8_system_regs.h.

References k_ra8_sys_off_rstsr1, and k_ra8_system_base_addr.

◆ ra8_sys_rstsr2()

volatile uint8_t * ra8_sys_rstsr2 ( void )

inlinestatic

Get pointer to the 8-bit RSTSR2 register.

Definition at line 480 of file ra8_system_regs.h.

References k_ra8_sys_off_rstsr2, and k_ra8_system_base_addr.

◆ ra8_sys_scickcr()

volatile uint8_t * ra8_sys_scickcr ( void )

inlinestatic

Get pointer to the 8-bit SCICKCR register (SCICLK source select).

Definition at line 311 of file ra8_system_regs.h.

References k_ra8_sys_off_scickcr, and k_ra8_system_base_addr.

Referenced by internal_route_sciclk().

◆ ra8_sys_scickdivcr()

volatile uint8_t * ra8_sys_scickdivcr ( void )

inlinestatic

Get pointer to the 8-bit SCICKDIVCR register (SCICLK divider).

Definition at line 304 of file ra8_system_regs.h.

References k_ra8_sys_off_scickdivcr, and k_ra8_system_base_addr.

Referenced by internal_route_sciclk().

◆ ra8_sys_sckdivcr()

volatile uint32_t * ra8_sys_sckdivcr ( void )

inlinestatic

Get pointer to the 32-bit SCKDIVCR register.

Definition at line 297 of file ra8_system_regs.h.

References k_ra8_sys_off_sckdivcr, and k_ra8_system_base_addr.

Referenced by cache_mpu_test_device_mmio(), internal_program_dividers(), and mpu_boot_test_device_mmio().

◆ ra8_sys_sckdivcr2()

volatile uint16_t * ra8_sys_sckdivcr2 ( void )

inlinestatic

Get pointer to the 16-bit SCKDIVCR2 register.

Definition at line 455 of file ra8_system_regs.h.

References k_ra8_sys_off_sckdivcr2, and k_ra8_system_base_addr.

Referenced by internal_program_dividers().

◆ ra8_sys_sckscr()

volatile uint8_t * ra8_sys_sckscr ( void )

inlinestatic

Get pointer to the 8-bit SCKSCR register.

Definition at line 317 of file ra8_system_regs.h.

References k_ra8_sys_off_sckscr, and k_ra8_system_base_addr.

Referenced by internal_cgc_init_protected(), ra8_cgc_switch_pll1_target(), and ra8_cgc_use_hoco().

◆ ra8_sys_somcr()

volatile uint8_t * ra8_sys_somcr ( void )

inlinestatic

Get pointer to the 8-bit SOMCR register (sub-clock oscillator mode).

Definition at line 335 of file ra8_system_regs.h.

References k_ra8_sys_off_somcr, and k_ra8_system_base_addr.

Referenced by internal_start_count_source().

◆ ra8_sys_sosccr()

volatile uint8_t * ra8_sys_sosccr ( void )

inlinestatic

Get pointer to the 8-bit SOSCCR register (sub-clock oscillator stop).

Definition at line 329 of file ra8_system_regs.h.

References k_ra8_sys_off_sosccr, and k_ra8_system_base_addr.

Referenced by internal_start_count_source().

◆ ra8_sys_usb60ckcr()

volatile uint8_t * ra8_sys_usb60ckcr ( void )

inlinestatic

Get pointer to the 8-bit USB60CKCR (USBHS 60MHz source select).

Definition at line 530 of file ra8_system_regs.h.

References k_ra8_sys_off_usb60ckcr, and k_ra8_system_base_addr.

Referenced by internal_usb60ckcr_switch_to_pll2p_div4(), and internal_wait_usb60cksrdy().

◆ ra8_sys_usb60ckdivcr()

volatile uint8_t * ra8_sys_usb60ckdivcr ( void )

inlinestatic

Get pointer to the 8-bit USB60CKDIVCR (USBHS 60MHz divider).

Definition at line 537 of file ra8_system_regs.h.

References k_ra8_sys_off_usb60ckdivcr, and k_ra8_system_base_addr.

Referenced by internal_usb60ckcr_switch_to_pll2p_div4().

◆ ra8_sys_usbckcr()

volatile uint8_t * ra8_sys_usbckcr ( void )

inlinestatic

Get pointer to the 8-bit USBCKCR (USB-FS source select).

Definition at line 524 of file ra8_system_regs.h.

References k_ra8_sys_off_usbckcr, and k_ra8_system_base_addr.

Referenced by internal_usbckcr_switch_to_pll2p_div5(), and internal_wait_usbcksrdy().

◆ ra8_sys_usbckdivcr()

volatile uint8_t * ra8_sys_usbckdivcr ( void )

inlinestatic

Get pointer to the 8-bit USBCKDIVCR (USB clock divider).

Definition at line 517 of file ra8_system_regs.h.

References k_ra8_sys_off_usbckdivcr, and k_ra8_system_base_addr.

Referenced by internal_usbckcr_switch_to_pll2p_div5().

◆ ra8_sys_vscr()

volatile uint32_t * ra8_sys_vscr ( void )

inlinestatic

Get pointer to the 32-bit VSCR register (voltage scaling control).

Definition at line 291 of file ra8_system_regs.h.

References k_ra8_sys_off_vscr, and k_ra8_system_base_addr.

Referenced by internal_set_vscr_not_high_v().

Enumerations

Functions

Detailed Description

Map (partial – only the registers this firmware touches)

PRCR unlock sequence

Enumeration Type Documentation

◆ ra8_eswckcr_bit_t

◆ ra8_eswcksel_t

◆ ra8_lococr_bit_t

◆ ra8_moscr_bit_t

◆ ra8_oscsf_bit_t

◆ ra8_pdctreswm_bit_t

◆ ra8_prcr_t

◆ ra8_rstsr0_bit_t

◆ ra8_rstsr2_bit_t

◆ ra8_somcr_drv_t

◆ ra8_sosccr_bit_t

◆ ra8_system_addr_t

◆ ra8_system_offset_t

◆ ra8_usbckcr_bit_t

◆ ra8_usbcksel_t

◆ ra8_vscr_bit_t

Function Documentation

◆ ra8_sys_canfdckcr()

◆ ra8_sys_canfdckdivcr()

◆ ra8_sys_eswckcr()

◆ ra8_sys_eswckdivcr()

◆ ra8_sys_eswpckcr()

◆ ra8_sys_eswpckdivcr()

◆ ra8_sys_hococr()

◆ ra8_sys_lococr()

◆ ra8_sys_moscwtcr()

◆ ra8_sys_octackcr()

◆ ra8_sys_octackdivcr()

◆ ra8_sys_oscsf()

◆ ra8_sys_pdctreswm()

◆ ra8_sys_pll2ccr()

◆ ra8_sys_pll2ccr2()

◆ ra8_sys_pll2cr()

◆ ra8_sys_pllccr()

◆ ra8_sys_pllccr2()

◆ ra8_sys_pllcr()

◆ ra8_sys_prcr()

◆ ra8_sys_prcr_lock_all()

◆ ra8_sys_prcr_unlock_cgc()

◆ ra8_sys_rstsr0()

◆ ra8_sys_rstsr1()

◆ ra8_sys_rstsr2()

◆ ra8_sys_scickcr()

◆ ra8_sys_scickdivcr()

◆ ra8_sys_sckdivcr()

◆ ra8_sys_sckdivcr2()

◆ ra8_sys_sckscr()

◆ ra8_sys_somcr()

◆ ra8_sys_sosccr()

◆ ra8_sys_usb60ckcr()

◆ ra8_sys_usb60ckdivcr()

◆ ra8_sys_usbckcr()

◆ ra8_sys_usbckdivcr()

◆ ra8_sys_vscr()