main.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cache.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_log.h"
#include "ra8_system_regs.h"

typedef enum : uint32_t {
  k_cache_mpu_baud         = 115200U,     
  k_cache_mpu_buf_bytes    = 4096U,       
  k_cache_mpu_buf_min      = 4096U,       
  k_cache_mpu_sckdivcr_exp = 0x32233432U, 
  k_cache_mpu_mram_sum_exp = 0xAAAAAAAAU, 
} cache_mpu_config_t;

typedef enum : uint8_t {
  k_cache_mpu_pat_mul = 31U, 
  k_cache_mpu_pat_add = 7U,  
} cache_mpu_pattern_t;

typedef enum : uint8_t {
  k_cache_mpu_mram_words = 4U, 
} cache_mpu_mram_t;

typedef enum : uint8_t {
  k_cache_mpu_result_pass      = 0U, 
  k_cache_mpu_result_fail_sram = 1U, 
  k_cache_mpu_result_fail_mram = 2U, 
  k_cache_mpu_result_fail_mmio = 3U, 
} cache_mpu_result_t;
 
static_assert((uint32_t)k_cache_mpu_buf_bytes >= (uint32_t)k_cache_mpu_buf_min,
              "cacheable self-test buffer must be at least 4 KiB");

alignas(32) static uint8_t s_cache_mpu_buf[k_cache_mpu_buf_bytes];

static const uint32_t k_cache_mpu_mram_table[k_cache_mpu_mram_words] = {
  0x11111111U,
  0x22222222U,
  0x33333333U,
  0x44444444U,
};

static const uint8_t k_cache_mpu_pass_banner[] = "cache_mpu_hil: cache+mpu PASS\r\n";

static const uint8_t k_cache_mpu_fail_setup[] = "cache_mpu_hil: setup FAIL\r\n";

static const uint8_t k_cache_mpu_fail_sram[] = "cache_mpu_hil: cacheable-SRAM FAIL\r\n";

static const uint8_t k_cache_mpu_fail_mram[] = "cache_mpu_hil: MRAM-const FAIL\r\n";

static const uint8_t k_cache_mpu_fail_mmio[] = "cache_mpu_hil: device-MMIO FAIL\r\n";

[[noreturn]] static void cache_mpu_wfi_forever(void)
{
  while (1) {
    __asm volatile("wfi");
  }
}

[[gnu::noinline]] static uint32_t cache_mpu_mram_const_sum(void)
{
  const volatile uint32_t* p   = k_cache_mpu_mram_table;
  uint32_t                 sum = 0U;
  for (uint8_t i = 0U; i < (uint8_t)k_cache_mpu_mram_words; i++) {
    sum += p[i];
  }
  return sum;
}

static bool cache_mpu_test_cacheable_rw(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_cache_mpu_buf_bytes; i++) {
    s_cache_mpu_buf[i] =
      (uint8_t)((i * (uint32_t)k_cache_mpu_pat_mul) + (uint32_t)k_cache_mpu_pat_add);
  }
 
  /* Force the freshly written (dirty) lines back to SRAM and drop them, so the
   * verify pass below must refill from memory -- the full write-back + refill
   * round-trip with the D-cache on. */
  if (ra8_cache_dcache_clean_invalidate_by_addr(s_cache_mpu_buf,
                                                (uint32_t)sizeof(s_cache_mpu_buf)) != k_ra8_ok) {
    return false;
  }
 
  for (uint32_t i = 0U; i < (uint32_t)k_cache_mpu_buf_bytes; i++) {
    const uint8_t expected =
      (uint8_t)((i * (uint32_t)k_cache_mpu_pat_mul) + (uint32_t)k_cache_mpu_pat_add);
    if (s_cache_mpu_buf[i] != expected) {
      return false;
    }
  }
  return true;
}

static bool cache_mpu_test_mram_const(void)
{
  const uint32_t sum1 = cache_mpu_mram_const_sum();
  const uint32_t sum2 = cache_mpu_mram_const_sum();
  if (sum1 != (uint32_t)k_cache_mpu_mram_sum_exp) {
    return false;
  }
  if (sum1 != sum2) {
    return false;
  }
  return true;
}

static bool cache_mpu_test_device_mmio(void)
{
  /* HUM Ch 9.2.2 "SCKDIVCR : System Clock Division Control Register" p 326 */
  const uint32_t sckdivcr = *ra8_sys_sckdivcr();
  if (sckdivcr == 0U) {
    return false;
  }
  if (sckdivcr != (uint32_t)k_cache_mpu_sckdivcr_exp) {
    return false;
  }
  return true;
}

static cache_mpu_result_t cache_mpu_run_selftest(void)
{
  if (!cache_mpu_test_cacheable_rw()) {
    return k_cache_mpu_result_fail_sram;
  }
  if (!cache_mpu_test_mram_const()) {
    return k_cache_mpu_result_fail_mram;
  }
  if (!cache_mpu_test_device_mmio()) {
    return k_cache_mpu_result_fail_mmio;
  }
  return k_cache_mpu_result_pass;
}

static bool cache_mpu_setup(void)
{
  if (ra8_cgc_init() != k_ra8_ok) {
    return false;
  }
  if (ra8_board_uart_console_init((uint32_t)k_cache_mpu_baud) != k_ra8_ok) {
    return false;
  }
  return true;
}

static void cache_mpu_emit(const uint8_t* line, size_t len)
{
  if (line == nullptr) {
    return;
  }
  if (len == 0U) {
    return;
  }
  (void)ra8_board_uart_console_write(line, len);
  (void)ra8_board_uart_console_flush();
}

void main(void)
{
  ra8_log_init();
  ra8_log_info("CACHE_MPU", "==== cache_mpu_hil: M85 L1 cache + MPU self-test ====");
 
  if (!cache_mpu_setup()) {
    ra8_log_info("CACHE_MPU", "setup FAILED (CGC / console) -- halting");
    cache_mpu_emit(k_cache_mpu_fail_setup, sizeof(k_cache_mpu_fail_setup) - 1U);
    cache_mpu_wfi_forever();
  }
 
  const cache_mpu_result_t result = cache_mpu_run_selftest();
 
  switch (result) {
    case k_cache_mpu_result_pass:
      ra8_log_info("CACHE_MPU", "cache+mpu PASS (cacheable RW + MRAM const + Device MMIO)");
      cache_mpu_emit(k_cache_mpu_pass_banner, sizeof(k_cache_mpu_pass_banner) - 1U);
      break;
    case k_cache_mpu_result_fail_sram:
      ra8_log_info("CACHE_MPU", "cacheable-SRAM step FAILED");
      cache_mpu_emit(k_cache_mpu_fail_sram, sizeof(k_cache_mpu_fail_sram) - 1U);
      break;
    case k_cache_mpu_result_fail_mram:
      ra8_log_info("CACHE_MPU", "MRAM-const step FAILED");
      cache_mpu_emit(k_cache_mpu_fail_mram, sizeof(k_cache_mpu_fail_mram) - 1U);
      break;
    case k_cache_mpu_result_fail_mmio:
    default:
      ra8_log_info("CACHE_MPU", "device-MMIO step FAILED");
      cache_mpu_emit(k_cache_mpu_fail_mmio, sizeof(k_cache_mpu_fail_mmio) - 1U);
      break;
  }
 
  cache_mpu_wfi_forever();
}