ra8_cache.c

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#include "ra8_cache.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_intrinsics.h"

static const char* const s_tag = "ra8_cache";

typedef enum : uintptr_t {
  k_ra8_cache_ccr      = 0xE000ED14UL, 
  k_ra8_cache_ctr      = 0xE000ED7CUL, 
  k_ra8_cache_ccsidr   = 0xE000ED80UL, 
  k_ra8_cache_csselr   = 0xE000ED84UL, 
  k_ra8_cache_iciallu  = 0xE000EF50UL, 
  k_ra8_cache_dcimvac  = 0xE000EF5CUL, 
  k_ra8_cache_dcisw    = 0xE000EF60UL, 
  k_ra8_cache_dccmvac  = 0xE000EF68UL, 
  k_ra8_cache_dccimvac = 0xE000EF70UL, 
  k_ra8_cache_dccisw   = 0xE000EF74UL, 
} ra8_cache_reg_addr_t;

typedef enum : uint32_t {
  k_ra8_cache_word_bytes      = 4U,        
  k_ra8_cache_ctr_dmin_shift  = 16U,       
  k_ra8_cache_ctr_dmin_mask   = 0xFU,      
  k_ra8_cache_ccsidr_sets_sh  = 13U,       
  k_ra8_cache_ccsidr_sets_msk = 0x7FFFU,   
  k_ra8_cache_ccsidr_assoc_sh = 3U,        
  k_ra8_cache_ccsidr_assoc_mk = 0x3FFU,    
  k_ra8_cache_dcisw_set_shift = 5U,        
  k_ra8_cache_dcisw_way_shift = 30U,       
  k_ra8_cache_ccr_ic_bit      = 1UL << 17, 
  k_ra8_cache_ccr_dc_bit      = 1UL << 16, 
} ra8_cache_field_t;

RA8_INTERNAL static inline volatile uint32_t* internal_ra8_cache_reg(ra8_cache_reg_addr_t addr)
{
  return (volatile uint32_t*)addr;
}
 
uint32_t ra8_cache_dcache_line_bytes(void)
{
  /* Arm v8-M ARM: CTR.DminLine = log2 of the smallest D-cache line in words. */
  const uint32_t ctr = *internal_ra8_cache_reg(k_ra8_cache_ctr);
  const uint32_t dmin =
    (ctr >> (uint32_t)k_ra8_cache_ctr_dmin_shift) & (uint32_t)k_ra8_cache_ctr_dmin_mask;
  return (uint32_t)k_ra8_cache_word_bytes << dmin;
}

RA8_INTERNAL static uint32_t
internal_ra8_cache_span_lines(uintptr_t addr, uint32_t size, uint32_t line, uintptr_t* out_start)
{
  const uintptr_t mask  = (uintptr_t)line - 1U;
  const uintptr_t start = addr & ~mask;
  const uintptr_t last  = (addr + (uintptr_t)size - 1U) & ~mask;
  *out_start            = start;
  return (uint32_t)((last - start) / (uintptr_t)line) + 1U;
}

RA8_INTERNAL static ra8_err_t
internal_ra8_cache_maintain_range(const void* addr, uint32_t size, ra8_cache_reg_addr_t reg)
{
  RA8_CHECK_NULL_PTR(addr, s_tag, "maintain: addr");
  if (size == 0U) {
    return k_ra8_ok;
  }
  const uint32_t line  = ra8_cache_dcache_line_bytes();
  uintptr_t      start = 0U;
  const uint32_t lines = internal_ra8_cache_span_lines((uintptr_t)addr, size, line, &start);
  ra8_hw_dsb();
  for (uint32_t i = 0U; i < lines; ++i) {
    *internal_ra8_cache_reg(reg) = (uint32_t)(start + ((uintptr_t)i * (uintptr_t)line));
  }
  ra8_hw_dsb();
  ra8_hw_isb();
  return k_ra8_ok;
}
 
ra8_err_t ra8_cache_dcache_clean_by_addr(const void* addr, uint32_t size)
{
  return internal_ra8_cache_maintain_range(addr, size, k_ra8_cache_dccmvac);
}
 
ra8_err_t ra8_cache_dcache_invalidate_by_addr(const void* addr, uint32_t size)
{
  return internal_ra8_cache_maintain_range(addr, size, k_ra8_cache_dcimvac);
}
 
ra8_err_t ra8_cache_dcache_clean_invalidate_by_addr(const void* addr, uint32_t size)
{
  return internal_ra8_cache_maintain_range(addr, size, k_ra8_cache_dccimvac);
}

RA8_INTERNAL static void internal_ra8_cache_setway_all(ra8_cache_reg_addr_t op_reg)
{
  /* Arm v8-M ARM: select L1 data cache, read its geometry, then apply the
   * set/way op to every set/way. CSSELR=0 selects level 0, data. */
  *internal_ra8_cache_reg(k_ra8_cache_csselr) = 0U;
  ra8_hw_dsb();
  const uint32_t ccsidr = *internal_ra8_cache_reg(k_ra8_cache_ccsidr);
  if ((ccsidr == 0U) || (ccsidr == UINT32_MAX)) {
    return; /* geometry unavailable -- nothing safe to touch */
  }
  uint32_t sets =
    (ccsidr >> (uint32_t)k_ra8_cache_ccsidr_sets_sh) & (uint32_t)k_ra8_cache_ccsidr_sets_msk;
  do {
    uint32_t ways =
      (ccsidr >> (uint32_t)k_ra8_cache_ccsidr_assoc_sh) & (uint32_t)k_ra8_cache_ccsidr_assoc_mk;
    do {
      *internal_ra8_cache_reg(op_reg) = (sets << (uint32_t)k_ra8_cache_dcisw_set_shift) |
                                        (ways << (uint32_t)k_ra8_cache_dcisw_way_shift);
    } while (ways-- != 0U);
  } while (sets-- != 0U);
  ra8_hw_dsb();
  ra8_hw_isb();
}
 
void ra8_cache_dcache_invalidate_all(void)
{
  internal_ra8_cache_setway_all(k_ra8_cache_dcisw);
}
 
void ra8_cache_icache_invalidate_all(void)
{
  /* Arm v8-M ARM: ICIALLU invalidates the whole L1 instruction cache to the
   * point of unification. Barriers bracket it so prior accesses retire and the
   * pipeline refetches before execution continues. */
  ra8_hw_dsb();
  ra8_hw_isb();
  *internal_ra8_cache_reg(k_ra8_cache_iciallu) = 0U;
  ra8_hw_dsb();
  ra8_hw_isb();
}
 
void ra8_cache_icache_enable(void)
{
  ra8_cache_icache_invalidate_all();
  /* Arm v8-M ARM: set SCB.CCR.IC (bit 17) to enable the L1 instruction cache.
   * Read-modify-write preserves the other CCR controls (DIV_0_TRP, BP, ...). */
  uint32_t ccr = *internal_ra8_cache_reg(k_ra8_cache_ccr);
  ccr |= (uint32_t)k_ra8_cache_ccr_ic_bit;
  *internal_ra8_cache_reg(k_ra8_cache_ccr) = ccr;
  ra8_hw_dsb();
  ra8_hw_isb();
}
 
void ra8_cache_icache_disable(void)
{
  /* Arm v8-M ARM: clear SCB.CCR.IC (bit 17), then invalidate so no stale line
   * survives a later re-enable. The I-cache holds no dirty state. */
  ra8_hw_dsb();
  ra8_hw_isb();
  uint32_t ccr = *internal_ra8_cache_reg(k_ra8_cache_ccr);
  ccr &= ~(uint32_t)k_ra8_cache_ccr_ic_bit;
  *internal_ra8_cache_reg(k_ra8_cache_ccr)     = ccr;
  *internal_ra8_cache_reg(k_ra8_cache_iciallu) = 0U;
  ra8_hw_dsb();
  ra8_hw_isb();
}
 
void ra8_cache_dcache_enable(void)
{
  /* Invalidate every set/way first (existing primitive) so no random power-on
   * line is treated as valid once the cache is on, THEN set CCR.DC. */
  ra8_cache_dcache_invalidate_all();
  /* Arm v8-M ARM: set SCB.CCR.DC (bit 16) to enable the L1 data cache. */
  uint32_t ccr = *internal_ra8_cache_reg(k_ra8_cache_ccr);
  ccr |= (uint32_t)k_ra8_cache_ccr_dc_bit;
  *internal_ra8_cache_reg(k_ra8_cache_ccr) = ccr;
  ra8_hw_dsb();
  ra8_hw_isb();
}
 
void ra8_cache_dcache_disable(void)
{
  /* Arm v8-M ARM: clear SCB.CCR.DC (bit 16) to stop new allocations, then clean
   * AND invalidate every set/way via DCCISW so any dirty line is written back to
   * memory as the cache goes cold -- disable must not discard dirty data. */
  uint32_t ccr = *internal_ra8_cache_reg(k_ra8_cache_ccr);
  ccr &= ~(uint32_t)k_ra8_cache_ccr_dc_bit;
  *internal_ra8_cache_reg(k_ra8_cache_ccr) = ccr;
  internal_ra8_cache_setway_all(k_ra8_cache_dccisw);
}
 
void ra8_cache_enable(void)
{
  /* Unified L1 bring-up: I-cache then D-cache, matching the order every
   * system_init.c boot copy uses. Each half runs its own architectural
   * invalidate before setting its CCR enable bit, so this is safe to call once
   * from a cold cache at boot. */
  ra8_cache_icache_enable();
  ra8_cache_dcache_enable();
}