ra8_canfd.c

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#include "ra8_canfd.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_canfd_regs.h"
#include "ra8_cgc.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hal_internal.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_register_protection.h"
#include "ra8_system_regs.h"
 
static const char* s_tag = "CANFD";

typedef enum : uint32_t {
  k_ra8_canfd_spin      = 20000U,  
  k_ra8_canfd_ckcr_spin = 262144U, 
} ra8_canfd_internal_t;

RA8_INTERNAL
static ra8_err_t internal_wait_status_bit(volatile r_canfd_t* reg, uint8_t status_bit)
{
  /* HUM Ch 41 p 2766 "CFDCnSTS" -- wait for the requested mode-ack bit
   * (CRSTSTS / CHLTSTS / ...) to latch. The host unit-test build runs this
   * same loop through the ra8_fake_mmio seam (ra8_hw_err.h), so a stuck
   * channel surfaces here as an hw_timeout instead of short-circuiting. */
  return ra8_hw_wait_flag_set32(&reg->CFDC[0].STS,
                                (uint32_t)(1UL << status_bit),
                                (uint32_t)k_ra8_canfd_spin);
}

static const ra8_mstp_t s_canfd_mstp_table[] = {
  k_ra8_mstp_canfd0,
  k_ra8_mstp_canfd1,
};

ra8_err_t priv_ra8_canfd_internal_set_channel_mode(volatile r_canfd_t* reg, ra8_chmdc_mode_t mode)
{
  /* Read-modify-write the CTR register, mask CHMDC to bits [1:0],
   * stamp the requested mode. Also clear CSLPR (bit 2): the channel
   * comes out of reset with CSLPR=1 (sleep request), and CHMDC
   * writes are silently ignored while the channel is asleep -- the
   * state machine stays in CH_RESET, status bits never flip, and
   * the next mode write times out. JTAG dump after the original
   * init showed CTR=0x05 / STS=0x05 (CHMDC=01 RESET + CSLPR=1 +
   * CRSTSTS=1 + CSLPSTS=1) confirming the channel never woke.
   * Mirrors the GSLPR clear in internal_set_global_mode.
   * HUM Ch 41 p 2762 "CFDCnCTR.CHMDC" + "CFDCnCTR.CSLPR" */
  uint32_t ctr = reg->CFDC[0].CTR;
  ctr &= ~(k_ra8_cnctr_mask_chmdc | k_ra8_cnctr_mask_cslpr);
  ctr |= ((uint32_t)mode & k_ra8_cnctr_mask_chmdc);
  reg->CFDC[0].CTR = ctr;
 
  /* HUM Ch 41 p 2766 "CFDCnSTS" -- the channel state machine reflects
   * the requested mode by latching CHLTSTS (halt), CRSTSTS (reset), or
   * by clearing BOTH (operation). Returning before the chip latches the
   * new state lets a subsequent CHMDC write race against the in-flight
   * transition and the chip silently ignores it (FSP r_canfd
   * mode_transition does the matching three-mode poll). Symptom seen on
   * HIL prior to this wait: ra8_canfd_set_test_mode -> set CHMDC=halt
   * times out on CHLTSTS because the channel state machine was still
   * completing the GL/CH operation handshake from ra8_canfd_init. */
  if (mode == k_ra8_chmdc_halt) {
    return internal_wait_status_bit(reg, k_ra8_cnsts_bit_chltst);
  }
  if (mode == k_ra8_chmdc_reset) {
    return internal_wait_status_bit(reg, k_ra8_cnsts_bit_crstst);
  }
  /* Operation: poll for (CRSTSTS|CHLTSTS) == 0 so a subsequent CHMDC
   * write does not race the in-flight transition. Real silicon
   * converges within a handful of CANFDCLK ticks; the host unit-test
   * build drives this same loop through the ra8_fake_mmio seam
   * (ra8_hw_err.h) so a stuck channel surfaces here as an hw_timeout
   * rather than at the next mode write, which is what made
   * canfd_loopback report a phantom test_mode failure with the real
   * problem being "channel never reached operation". */
  const uint32_t reset_or_halt =
    (uint32_t)((1UL << k_ra8_cnsts_bit_crstst) | (1UL << k_ra8_cnsts_bit_chltst));
  return ra8_hw_wait_flag_clear32(&reg->CFDC[0].STS, reset_or_halt, (uint32_t)k_ra8_canfd_spin);
}

RA8_INTERNAL
static ra8_err_t internal_set_global_mode(volatile r_canfd_t* reg, uint32_t gmdc_value)
{
  /* HUM Ch 41 "CFDGCTR.GMDC" p 2742 */ /* "CFDGCTR.GMDC" + GSLPR clear. */
  uint32_t gctr = reg->CFDGCTR;
  gctr &= ~(k_ra8_gctr_mask_gmdc | k_ra8_gctr_mask_gslpr);
  gctr |= (gmdc_value & k_ra8_gctr_mask_gmdc);
  reg->CFDGCTR = gctr;
 
  if (gmdc_value == k_ra8_gctr_value_halt) {
    return ra8_hw_wait_flag_set32(&reg->CFDGSTS,
                                  (uint32_t)(1UL << k_ra8_gsts_bit_ghltsts),
                                  (uint32_t)k_ra8_canfd_spin);
  }
  if (gmdc_value == k_ra8_gctr_value_reset) {
    return ra8_hw_wait_flag_set32(&reg->CFDGSTS,
                                  (uint32_t)(1UL << k_ra8_gsts_bit_grststs),
                                  (uint32_t)k_ra8_canfd_spin);
  }
  /* Global OPERATION is the state where BOTH GRSTSTS and GHLTSTS
   * read 0. The host unit-test build drives this same loop through the
   * ra8_fake_mmio seam (ra8_hw_err.h) so a stuck global block surfaces
   * here as an hw_timeout rather than at the next channel-mode write.
   * HUM Ch 41 p 2746 "CFDGSTS" */
  const uint32_t reset_or_halt =
    (uint32_t)((1UL << k_ra8_gsts_bit_grststs) | (1UL << k_ra8_gsts_bit_ghltsts));
  return ra8_hw_wait_flag_clear32(&reg->CFDGSTS, reset_or_halt, (uint32_t)k_ra8_canfd_spin);
}

RA8_INTERNAL
static void internal_install_default_afl(volatile r_canfd_t* reg)
{
  /* HUM Ch 41 "CFDGAFLCFG0" p 2730 */ /* RNC0 = 1 -> one rule on page 0. */
  reg->CFDGAFLCFG0 = 1UL << 16U;
 
  /* HUM Ch 41 "CFDGAFLECTR" p 2734 */ /* page 0, AFLDAE = 1 unlocks edit. */
  reg->CFDGAFLECTR = k_ra8_gaflectr_bit_afldae;
 
  /* HUM Ch 41 "CFDGAFLID" p 2735 */ /* accept-id ignored: mask = 0. */
  reg->CFDGAFL[0].ID = 0U;
  /* HUM Ch 41 "CFDGAFLM" p 2736 */ /* mask = 0 -> accept every ID. */
  reg->CFDGAFL[0].M = 0U;
  /* HUM Ch 41 "CFDGAFLP0" p 2738 */ /* no RX-MB routing requested. */
  reg->CFDGAFL[0].P0 = 0U;
  /* HUM Ch 41 "CFDGAFLP1" p 2740 */ /* GAFLFDP0 = bit 0 -> RX FIFO 0. */
  reg->CFDGAFL[0].P1 = 1UL << 0U;
 
  /* Re-lock the AFL data window. */
  reg->CFDGAFLECTR = 0U;
}

RA8_INTERNAL
static void internal_configure_rx_fifo0(volatile r_canfd_t* reg)
{
  /* Programme depth + payload in GL_RESET (RFE bit left zero -- it
   * is only writable in GL_HALT or GL_OPERATION per HUM Ch 41
   * "CFDRFCCa" p 2741. Setting RFE here would silently no-op, the
   * FIFO would stay disabled, and every loopback frame would land
   * in /dev/null instead of the RX FIFO.) */
  enum : uint32_t {
    k_rfcc_rfdc_4msgs = 1UL << 8U, 
    k_rfcc_rfpls_64   = 7UL << 4U, 
  };
  reg->CFDRFCC[0] = k_rfcc_rfdc_4msgs | k_rfcc_rfpls_64;
}

RA8_INTERNAL
static void internal_enable_rx_fifo0(volatile r_canfd_t* reg)
{
  /* HUM Ch 41 "CFDRFCCa.RFE" p 2742 -- separate write after the rest of
   * the CFDRFCCa register has been set, while in GL_OPERATION. */
  reg->CFDRFCC[0] |= k_ra8_rfcc_bit_rfe;
}

RA8_INTERNAL
static ra8_err_t internal_wait_canfdcksrdy(uint8_t expected)
{
  /* SRDY (clock-source ready) is bit 7 of CANFDCKCR. @p expected is
   * always 0 or 1, so this reduces to a single-bit set/clear wait; the
   * host unit-test build runs the same loop through the ra8_fake_mmio
   * seam (ra8_hw_err.h) instead of faking the ack write. */
  /* HUM Ch 9.2.46 "CANFDCKCR.CANFDCKSRDY" p 366 */
  volatile const uint8_t* const ckcr = ra8_sys_canfdckcr();
  const uint8_t                 mask = (uint8_t)(1U << k_ra8_usbckcr_bit_srdy);
  if (expected != 0U) {
    return ra8_hw_wait_flag_set8(ckcr, mask, (uint32_t)k_ra8_canfd_ckcr_spin);
  }
  return ra8_hw_wait_flag_clear8(ckcr, mask, (uint32_t)k_ra8_canfd_ckcr_spin);
}

RA8_INTERNAL
static ra8_err_t internal_canfd_clock_block_init(void)
{
  static bool s_canfd_clock_inited = false;
  if (s_canfd_clock_inited) {
    return k_ra8_ok;
  }
  ra8_err_t err = k_ra8_ok;
  RA8_PROTECTED_WRITE(k_ra8_prcr_unlock_cgc)
  {
    /* HUM Ch 9.2.41 "CANFDCKDIVCR" p 357 -- /1 divider keeps MOCO at
     * its native rate (~8 MHz nominal; PCLKA on this project is
     * 100 MHz so MOCO < PCLKA satisfies HUM Ch 41.1.2 clock
     * restriction CANFDCLK <= PCLKA). */
    *ra8_sys_canfdckdivcr() = 0U;
 
    /* HUM Ch 9.2.46 "CANFDCKCR.CANFDCKSREQ" p 366 -- assert SREQ with
     * the reset-default source (MOCO, CANFDCKSEL = 0001b). */
    const uint8_t sreq_mask = (uint8_t)(1U << k_ra8_usbckcr_bit_sreq);
    const uint8_t src_moco  = 0x01U;
    *ra8_sys_canfdckcr()    = (uint8_t)(src_moco | sreq_mask);
 
    /* Step 3: wait for SRDY = 1 (chip acknowledges the request). */
    err = internal_wait_canfdcksrdy(1U);
    if (err != k_ra8_ok) {
      ra8_log_error(s_tag, "canfd: CANFDCKSRDY=1 timeout");
      break;
    }
    /* Step 4: drop SREQ -- commits the (same) source selection. */
    *ra8_sys_canfdckcr() = src_moco;
    /* Step 5: wait for SRDY = 0 -- handshake done. */
    err = internal_wait_canfdcksrdy(0U);
    if (err != k_ra8_ok) {
      ra8_log_error(s_tag, "canfd: CANFDCKSRDY=0 timeout");
      break;
    }
  }
  if (err == k_ra8_ok) {
    s_canfd_clock_inited = true;
    ra8_log_info(s_tag, "canfd block clock stable");
  }
  return err;
}

RA8_INTERNAL
static ra8_err_t internal_canfd_open_channel(volatile r_canfd_t* reg)
{
  (void)internal_set_global_mode(reg, k_ra8_gctr_value_reset);
  (void)priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_reset);
 
  internal_install_default_afl(reg);
  internal_configure_rx_fifo0(reg);
 
  const ra8_err_t gop_err = internal_set_global_mode(reg, k_ra8_gctr_value_operation);
  if (gop_err != k_ra8_ok) {
    return gop_err;
  }
  /* RFE is only writable in GL_HALT / GL_OPERATION, so enable RX FIFO
   * 0 only after the global block has actually transitioned. */
  internal_enable_rx_fifo0(reg);
  return priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_operation);
}
 
ra8_err_t ra8_canfd_init(uint8_t channel)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  if (channel >= (uint8_t)(sizeof(s_canfd_mstp_table) / sizeof(s_canfd_mstp_table[0]))) {
    return k_ra8_err_invalid_arg;
  }
  /* MSTPC26/27 must be written AFTER CANFDCLK is stable.
   * HUM Ch 11.2.8 "MSTPCRC" Note 4 p 446 */
  const ra8_err_t clk_err = internal_canfd_clock_block_init();
  if (clk_err != k_ra8_ok) {
    return clk_err;
  }
 
  /* HUM Ch 11.2.8 "MSTPCRC : Module Stop Control Register C", p 447 */
  const ra8_err_t mst_err = ra8_mstp_enable(s_canfd_mstp_table[channel]);
  /* GCOVR_EXCL_BR_START -- MSTP HW readback */
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "canfd_init: mstp enable");
  /* GCOVR_EXCL_BR_STOP */
 
  /* Wait for RAM init done (CFDGSTS.GRAMINIT clears). */
  /* HUM Ch 41.2 "CFDGSTS : Global Status Register" p 2730 */
  for (uint32_t i = 0U; i < k_ra8_canfd_spin; i++) {
    if ((reg->CFDGSTS & (uint32_t)(1UL << k_ra8_gsts_bit_graminit)) == 0U) {
      break;
    }
  }
 
  const ra8_err_t open_err = internal_canfd_open_channel(reg);
  if (open_err != k_ra8_ok) {
    return open_err;
  }
  ra8_log_info_val(s_tag, "canfd_init ch", (uint32_t)channel);
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_deinit(uint8_t channel)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
 
  /* HUM Ch 41 "CFDCnCTR.CHMDC" p 2762 */ /* "CFDCnCTR.CHMDC" -- park channel in reset. */
  (void)priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_reset);
  return k_ra8_ok;
}
 
/* =============================================================================
 * status + IRQ + power transition
 * =============================================================================
 */
 
static ra8_canfd_event_fn_t s_canfd_fn;
static void*                s_canfd_ctx;
 
ra8_err_t ra8_canfd_get_status(uint8_t channel, uint32_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "out_mask must not be nullptr");
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  /* HUM Ch 41 "CFDCnSTS" p 2766 */ /* "CFDCnSTS". */
  *out_mask = reg->CFDC[0].STS;
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_clear_status(uint8_t channel, uint32_t mask)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  /* HUM Ch 41 p 2772 "CFDCnERFL" -- error flags are W0C: writing 0
   * clears, writing 1 leaves untouched. We compute the inverse mask
   * to match the previous behaviour ("clear bits in mask"). */
  reg->CFDC[0].ERFL = reg->CFDC[0].ERFL & ~mask;
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_attach_handler(ra8_canfd_event_fn_t fn, void* ctx)
{
  s_canfd_fn  = fn;
  s_canfd_ctx = ctx;
  return k_ra8_ok;
}
 
RA8_ISR_SAFE
void ra8_canfd_dispatch(uint8_t channel)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  if (reg == nullptr) {
    return;
  }
  /* HUM Ch 41 "CFDCnERFL" p 2772 */ /* "CFDCnERFL" snapshot then ack. */
  const uint32_t             mask = reg->CFDC[0].ERFL;
  const ra8_canfd_event_fn_t fn   = s_canfd_fn;
  void* const                ctx  = s_canfd_ctx;
  reg->CFDC[0].ERFL               = 0U;
  if (fn != nullptr) {
    fn(ctx, channel, mask);
  }
}

enum : uint16_t {
  k_ra8_canfd_afl_per_page = 16U, 
};

RA8_INTERNAL
static void internal_bump_rnc0_locked(volatile r_canfd_t* reg, uint16_t filter_id)
{
  if (filter_id >= (uint16_t)k_ra8_canfd_afl_per_page) {
    return;
  }
  const uint32_t cur_rnc =
    (reg->CFDGAFLCFG0 >> k_ra8_gaflcfg0_shift_rnc0) & k_ra8_gaflcfg0_mask_rnc0;
  const uint32_t new_rnc = ((uint32_t)filter_id + 1U) & k_ra8_gaflcfg0_mask_rnc0;
  if (cur_rnc < new_rnc) {
    const uint32_t cfg0 = reg->CFDGAFLCFG0;
    reg->CFDGAFLCFG0    = (cfg0 & ~(k_ra8_gaflcfg0_mask_rnc0 << k_ra8_gaflcfg0_shift_rnc0)) |
                          ((new_rnc & k_ra8_gaflcfg0_mask_rnc0) << k_ra8_gaflcfg0_shift_rnc0);
  }
}

RA8_INTERNAL
static void internal_write_afl_slot(volatile r_canfd_t* reg,
                                    uint16_t            slot,
                                    uint32_t            accept_id,
                                    uint32_t            mask,
                                    uint8_t             dlc)
{
  reg->CFDGAFL[slot].ID = accept_id;
  reg->CFDGAFL[slot].M  = mask | (uint32_t)k_ra8_gaflm_bit_gafllb;
  reg->CFDGAFL[slot].P0 = 0U;
  reg->CFDGAFL[slot].P1 =
    (((uint32_t)dlc & k_ra8_canfd_ptr_mask_dlc) << k_ra8_canfd_ptr_shift_dlc) |
    (uint32_t)k_ra8_gaflp1_bit_gaflfdp0;
}
 
/* ra8_canfd_filter_set -- see header for full description.
 *
 * HUM Ch 41.2.18 / 41.2.20 / 41.2.22 p 2735-2742: CFDGAFLCFG0.RNC0
 * and the per-slot CFDGAFL.{ID,M,P0,P1} registers are only writable
 * while the global block is in GL_RESET. Writing them in
 * GL_OPERATION lands the bits in the register file but the AFL
 * lookup engine never resamples them, so live filtering keeps using
 * the snapshot taken at the most recent GL_RESET -> GL_OPERATION
 * transition. install_default_afl in internal_canfd_open_channel
 * runs in GL_RESET for that reason; we mirror the same RESET ->
 * write -> OPERATION transaction here so updates take effect. */
ra8_err_t ra8_canfd_filter_set(uint16_t filter_id, uint32_t accept_id, uint32_t mask, uint8_t dlc)
{
  if (filter_id >= k_ra8_canfd_afl_total) {
    return k_ra8_err_invalid_arg;
  }
  if (dlc > k_ra8_canfd_dlc_max) {
    return k_ra8_err_invalid_arg;
  }
  if ((accept_id & ~k_ra8_canfd_id_ext_mask) != 0U) {
    return k_ra8_err_invalid_arg;
  }
 
  const uint16_t page = (uint16_t)(filter_id / k_ra8_canfd_afl_per_page);
  const uint16_t slot = (uint16_t)(filter_id % k_ra8_canfd_afl_per_page);
 
  /* AFL is global across instances; access via channel 0. */
  volatile r_canfd_t* reg = ra8_canfd(0U);
  RA8_CHECK_NULL_PTR(reg, s_tag, "filter_set: channel0 unavailable");
 
  const ra8_err_t reset_err = internal_set_global_mode(reg, k_ra8_gctr_value_reset);
  if (reset_err != k_ra8_ok) {
    return reset_err;
  }
 
  internal_bump_rnc0_locked(reg, filter_id);
 
  /* Unlock AFL data window via AFLDAE bit. */
  /* HUM Ch 41.2 "CFDGAFLECTR : AFL Entry Control Register" p 2734 */
  reg->CFDGAFLECTR = ((uint32_t)page & k_ra8_gaflectr_mask_aflpn) | k_ra8_gaflectr_bit_afldae;
  internal_write_afl_slot(reg, slot, accept_id, mask, dlc);
  reg->CFDGAFLECTR = 0U;
 
  const ra8_err_t op_err = internal_set_global_mode(reg, k_ra8_gctr_value_operation);
  if (op_err != k_ra8_ok) {
    return op_err;
  }
  /* GL_RESET cleared CFDRFCCa.RFE (HUM Ch 41 p 2742); re-enable so
   * matched frames have a landing FIFO once we resume operation. */
  internal_enable_rx_fifo0(reg);
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_set_test_mode(uint8_t channel, ra8_ctms_mode_t mode)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  if ((uint8_t)mode > (uint8_t)k_ra8_ctms_self_test_1) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 41 "CFDCnCTR" p 2710 -- CTME (bit 24) and CTMS (bits
   * [26:25]) are only writable in CH_HALT mode.  ra8_canfd_init parks
   * the channel in CH_OPERATION so we transition through CH_HALT to
   * land the test-mode select, then return to CH_OPERATION. */
  const ra8_err_t halt_err = priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_halt);
  if (halt_err != k_ra8_ok) {
    /* Best-effort recover the channel before reporting the error. */
    (void)priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_operation);
    return halt_err;
  }
 
  /* Read-modify-write CTR: clear any prior CTME/CTMS, then OR in the
   * requested selector with CTME = 1. */
  uint32_t ctr = reg->CFDC[0].CTR;
  ctr &= ~(k_ra8_cnctr_mask_ctme | k_ra8_cnctr_mask_ctms);
  ctr |= k_ra8_cnctr_mask_ctme;
  ctr |= ((uint32_t)mode << (uint32_t)k_ra8_cnctr_bit_ctms) & k_ra8_cnctr_mask_ctms;
  reg->CFDC[0].CTR = ctr;
 
  return priv_ra8_canfd_internal_set_channel_mode(reg, k_ra8_chmdc_operation);
}
 
ra8_err_t ra8_canfd_set_iso_mode(bool enable)
{
  volatile r_canfd_t* reg = ra8_canfd(0U);
  RA8_CHECK_NULL_PTR(reg, s_tag, "set_iso_mode: channel0 unavailable");
  /* HUM Ch 41 "CFDGFDCFG" pp 2702-2867 -- bit 0 (NISO) is set for ISO
   * mode (default) and cleared for non-ISO Bosch framing. */
  uint32_t v = reg->CFDGFDCFG;
  if (enable) {
    v |= k_ra8_gfdcfg_bit_niso;
  } else {
    v &= ~k_ra8_gfdcfg_bit_niso;
  }
  reg->CFDGFDCFG = v;
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_enter_stop(uint8_t channel)
{
  if (channel >= k_ra8_canfd_instance_count) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 11.2.8 "MSTPCRC" p 447 */ /* gate channel clock back off. */
  return ra8_mstp_disable(s_canfd_mstp_table[channel]);
}
 
ra8_err_t ra8_canfd_exit_stop(uint8_t channel)
{
  if (channel >= k_ra8_canfd_instance_count) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 11.2.8 "MSTPCRC" p 447 */ /* ungate channel clock. */
  return ra8_mstp_enable(s_canfd_mstp_table[channel]);
}