ra8_canfd_regs.h File Reference

CANFD controller register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_canfd_regs.h:

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Go to the source code of this file.

Data Structures
struct	r_canfd_cfdc_t
struct	r_canfd_cfdc2_t
struct	r_canfd_cfdgafl_t
struct	r_canfd_cfdrf_t
struct	r_canfd_cfdcf_t
struct	r_canfd_cfdtm_t
struct	r_canfd_cfdthl_t
struct	r_canfd_cfdrm_entry_t
struct	r_canfd_cfdrm_t
struct	r_canfd_t

Enumerations
enum	ra8_canfd_addr_t : uintptr_t {   k_ra8_canfd0_base_addr = 0x40380000UL ,   k_ra8_canfd1_base_addr = 0x40382000UL }
enum	ra8_canfd_limits_t : uint8_t {   k_ra8_canfd_instance_count = 2U ,   k_ra8_canfd_rx_fifo_count = 2U ,   k_ra8_canfd_cf_count = 1U ,   k_ra8_canfd_tx_mb_count = 4U ,   k_ra8_canfd_afl_page_size = 16U ,   k_ra8_canfd_rm_per_cluster = 8U ,   k_ra8_canfd_rm_clusters = 4U }
enum	ra8_canfd_frame_limits_t : uint8_t {   k_ra8_canfd_data_bytes_max = 64U ,   k_ra8_canfd_dlc_max = 15U }
	Message-frame limits common to the public API and register layer. More...
enum	ra8_canfd_pad_t : uint16_t {   k_ra8_canfd_pad_cfdc2_tail_bytes = 12U ,   k_ra8_canfd_pad_rm_cluster_words = 104U ,   k_ra8_canfd_pad_before_grstc = 2U ,   k_ra8_canfd_pad_after_grstc_words = 9U ,   k_ra8_canfd_pad_before_rpgacc = 24U ,   k_ra8_canfd_rpgacc_word_count = 64U ,   k_ra8_canfd_pad_before_rf_words = 104U ,   k_ra8_canfd_pad_before_thl_words = 3U ,   k_ra8_canfd_pad_before_rm_words = 118U }
	Reserved-region sizes between FSP-named registers. More...
enum	ra8_cnctr_bit_t : uint8_t {   k_ra8_cnctr_bit_chmdc = 0U ,   k_ra8_cnctr_bit_cslpr = 2U ,   k_ra8_cnctr_bit_bom = 21U ,   k_ra8_cnctr_bit_ctme = 24U ,   k_ra8_cnctr_bit_ctms = 25U }
enum	ra8_cnctr_mask_t : uint32_t {   k_ra8_cnctr_mask_chmdc = 0x3UL ,   k_ra8_cnctr_mask_cslpr = 0x4UL ,   k_ra8_cnctr_mask_ctme = 1UL << 24U ,   k_ra8_cnctr_mask_ctms = 0x3UL << 25U }
enum	ra8_ctms_mode_t : uint8_t {   k_ra8_ctms_basic = 0U ,   k_ra8_ctms_listen_only = 1U ,   k_ra8_ctms_self_test_0 = 2U ,   k_ra8_ctms_self_test_1 = 3U }
	Channel Test Mode Select values (CFDC[0].CTR.CTMS[1:0]). More...
enum	ra8_chmdc_mode_t : uint8_t {   k_ra8_chmdc_operation = 0U ,   k_ra8_chmdc_reset = 1U ,   k_ra8_chmdc_halt = 2U ,   k_ra8_chmdc_keep = 3U }
	Channel Mode Control (CFDC[0].CTR.CHMDC[1:0]) values. More...
enum	ra8_cnsts_bit_t : uint8_t {   k_ra8_cnsts_bit_crstst = 0U ,   k_ra8_cnsts_bit_chltst = 1U ,   k_ra8_cnsts_bit_cslpst = 2U ,   k_ra8_cnsts_bit_epst = 3U ,   k_ra8_cnsts_bit_bosts = 4U ,   k_ra8_cnsts_bit_rec = 16U ,   k_ra8_cnsts_bit_tec = 24U }
enum	ra8_cnsts_mask_t : uint32_t {   k_ra8_cnsts_mask_rec = 0xFFUL ,   k_ra8_cnsts_mask_tec = 0xFFUL }
enum	ra8_cncfg_shift_t : uint8_t {   k_ra8_cncfg_shift_nbrp = 0U ,   k_ra8_cncfg_shift_nsjw = 10U ,   k_ra8_cncfg_shift_ntseg1 = 17U ,   k_ra8_cncfg_shift_ntseg2 = 25U }
enum	ra8_cncfg_mask_t : uint32_t {   k_ra8_cncfg_mask_nbrp = 0x3FFUL ,   k_ra8_cncfg_mask_nsjw = 0x7FUL ,   k_ra8_cncfg_mask_ntseg1 = 0xFFUL ,   k_ra8_cncfg_mask_ntseg2 = 0x7FUL }
enum	ra8_dcfg_shift_t : uint8_t {   k_ra8_dcfg_shift_dbrp = 0U ,   k_ra8_dcfg_shift_dtseg1 = 8U ,   k_ra8_dcfg_shift_dtseg2 = 16U ,   k_ra8_dcfg_shift_dsjw = 24U }
enum	ra8_dcfg_mask_t : uint32_t {   k_ra8_dcfg_mask_dbrp = 0xFFUL ,   k_ra8_dcfg_mask_dtseg1 = 0x1FUL ,   k_ra8_dcfg_mask_dtseg2 = 0xFUL ,   k_ra8_dcfg_mask_dsjw = 0xFUL }
enum	ra8_canfd_bit_timing_limits_t : uint32_t {   k_ra8_canfd_tq_per_bit = 20U ,   k_ra8_canfd_prescaler_min = 1U ,   k_ra8_canfd_prescaler_max = 1024U ,   k_ra8_canfd_data_prescaler_max = 256U ,   k_ra8_canfd_sjw_max = 16U ,   k_ra8_canfd_dsjw_max = 16U ,   k_ra8_canfd_dtseg1_max = 32U ,   k_ra8_canfd_dtseg2_max = 16U }
	Prescaler / TSEG / SJW resolution bounds shared by both phases. More...
enum	ra8_cnerfl_mask_t : uint32_t {   k_ra8_cnerfl_mask_bef = 1UL << 0U ,   k_ra8_cnerfl_mask_ewf = 1UL << 1U ,   k_ra8_cnerfl_mask_epf = 1UL << 2U ,   k_ra8_cnerfl_mask_boef = 1UL << 3U ,   k_ra8_cnerfl_mask_borf = 1UL << 4U ,   k_ra8_cnerfl_mask_ovlf = 1UL << 5U ,   k_ra8_cnerfl_mask_blf = 1UL << 6U ,   k_ra8_cnerfl_mask_alf = 1UL << 7U ,   k_ra8_cnerfl_mask_serr = 1UL << 8U ,   k_ra8_cnerfl_mask_ferr = 1UL << 9U ,   k_ra8_cnerfl_mask_aerr = 1UL << 10U ,   k_ra8_cnerfl_mask_cerr = 1UL << 11U ,   k_ra8_cnerfl_mask_b1err = 1UL << 12U ,   k_ra8_cnerfl_mask_b0err = 1UL << 13U ,   k_ra8_cnerfl_mask_aderr = 1UL << 14U ,   k_ra8_cnerfl_mask_all_w1c = 0x7FFFUL }
enum	ra8_gctr_bit_t : uint8_t {   k_ra8_gctr_bit_gmdc = 0U ,   k_ra8_gctr_bit_gslpr = 2U }
enum	ra8_gctr_value_t : uint32_t {   k_ra8_gctr_mask_gmdc = 0x3UL ,   k_ra8_gctr_mask_gslpr = 1UL << 2U ,   k_ra8_gctr_value_operation = 0UL ,   k_ra8_gctr_value_reset = 1UL ,   k_ra8_gctr_value_halt = 2UL }
enum	ra8_gsts_bit_t : uint8_t {   k_ra8_gsts_bit_grststs = 0U ,   k_ra8_gsts_bit_ghltsts = 1U ,   k_ra8_gsts_bit_gslpsts = 2U ,   k_ra8_gsts_bit_graminit = 3U }
	Global Status (CFDGSTS) bit positions. More...
enum	ra8_rfcc_bits_t : uint32_t {   k_ra8_rfcc_bit_rfe = 1UL << 0U ,   k_ra8_rfcc_bit_rfie = 1UL << 1U }
enum	ra8_rfsts_bits_t : uint32_t {   k_ra8_rfsts_bit_empty = 1UL << 0U ,   k_ra8_rfsts_bit_full = 1UL << 1U ,   k_ra8_rfsts_bit_mlt = 1UL << 2U ,   k_ra8_rfsts_bit_if = 1UL << 3U }
enum	ra8_rfpctr_bits_t : uint32_t { k_ra8_rfpctr_value_ack = 0xFFUL }
enum	ra8_gaflectr_bits_t : uint32_t {   k_ra8_gaflectr_mask_aflpn = 0xFUL ,   k_ra8_gaflectr_bit_afldae = 1UL << 8U }
enum	ra8_gaflcfg0_bits_t : uint32_t {   k_ra8_gaflcfg0_shift_rnc0 = 16U ,   k_ra8_gaflcfg0_mask_rnc0 = 0x1FU }
	CFDGAFLCFG0 layout (HUM Ch 41.2.18 p 2735). More...
enum	ra8_gaflp1_bits_t : uint32_t { k_ra8_gaflp1_bit_gaflfdp0 = 1UL << 0U }
	CFDGAFLP1r layout (HUM Ch 41.2.22 p 2740). More...
enum	ra8_gaflm_bits_t : uint32_t {   k_ra8_gaflm_bit_gafllb = 1UL << 29U ,   k_ra8_gaflm_bit_gaflrtrm = 1UL << 30U ,   k_ra8_gaflm_bit_gaflidem = 1UL << 31U }
	CFDGAFLM (Acceptance Filter Mask) layout (HUM Ch 41.2.20 p 2736). More...
enum	ra8_canfd_afl_total_t : uint16_t { k_ra8_canfd_afl_total = (uint16_t)(16U * 16U) }
	Maximum number of GAFL filter rules across all paged windows. More...
enum	ra8_canfd_gfdcfg_bits_t : uint32_t { k_ra8_gfdcfg_bit_niso = 1UL << 0U }
	CFDGFDCFG (Global FD Config) field positions. More...
enum	ra8_canfd_id_bits_t : uint32_t {   k_ra8_canfd_id_std_mask = 0x000007FFUL ,   k_ra8_canfd_id_ext_mask = 0x1FFFFFFFUL ,   k_ra8_canfd_id_thlen = 1UL << 29U ,   k_ra8_canfd_id_rtr = 1UL << 30U ,   k_ra8_canfd_id_ide = 1UL << 31U }
enum	ra8_canfd_fd_bits_t : uint32_t {   k_ra8_canfd_fd_esi = 1UL << 0U ,   k_ra8_canfd_fd_brs = 1UL << 1U ,   k_ra8_canfd_fd_fdf = 1UL << 2U }
enum	ra8_canfd_ptr_shift_t : uint8_t { k_ra8_canfd_ptr_shift_dlc = 28U }
enum	ra8_canfd_ptr_mask_t : uint32_t { k_ra8_canfd_ptr_mask_dlc = 0xFUL }
enum	ra8_canfd_tmc_bits_t : uint8_t {   k_ra8_canfd_tmc_txreq = 1U << 0U ,   k_ra8_canfd_tmc_abort = 1U << 1U ,   k_ra8_canfd_tmc_oneshot = 1U << 2U }
enum	ra8_fdcfg_shift_t : uint8_t {   k_ra8_fdcfg_shift_tdco = 8U ,   k_ra8_fdcfg_shift_tdcoc = 15U ,   k_ra8_fdcfg_shift_tde = 16U }
	Bit-shift positions for the TDC fields in CFDCnFDCFG. More...
enum	ra8_fdcfg_mask_t : uint32_t {   k_ra8_fdcfg_mask_tdco = 0x7FUL ,   k_ra8_fdcfg_mask_tdcoc = 1UL << 15U ,   k_ra8_fdcfg_mask_tde = 1UL << 16U }
	Bit masks for the TDC fields in CFDCnFDCFG. More...
enum	ra8_canfd_tdc_limits_t : uint8_t { k_ra8_canfd_tdc_offset_max = 127U }
	Bounds on the Transmitter Delay Compensation Offset field. More...
enum	ra8_fdsts_mask_t : uint32_t { k_ra8_fdsts_mask_tdcr = 0xFFUL }
	Bit mask for the TDCR read-only measurement in CFDCnFDSTS. More...

Functions
static volatile r_canfd_t *	ra8_canfd (uint8_t channel)
	Get pointer to CANFD instance N (0..1).

Detailed Description

CANFD controller register layout for the Renesas RA8D2.

Two CANFD instances live at 0x40380000 (CANFD0) and 0x40382000 (CANFD1). Each instance is a full RA8 CANFD block (NOT the smaller "CANFD Lite" / "CANFD_B" found on RA4/RA6 parts). The actual register layout is the one captured by the FSP CMSIS device file R7KA8D2KF_core0.h R_CANFD_Type (size 0x1920) and matches the field semantics in r_canfd.c (FSP).

Layout summary (offsets relative to the channel base):

• 0x000 .. 0x00F : per-channel CFDC[1] = { NCFG, CTR, STS, ERFL }
• 0x010 : reserved
• 0x014 .. 0x0DC : global block (CFDGCFG, CFDGCTR, CFDGSTS, CFDGERFL, CFDGTSC, CFDGAFLECTR, CFDGAFLCFG0, CFDRMNB, CFDRMND0, CFDRMIEC, CFDRFCC[2], CFDRFSTS[2], CFDRFPCTR[2], CFDCFCC[1], CFDCFSTS[1], CFDCFPCTR[1], CFDFESTS, CFDFFSTS, CFDFMSTS, CFDRFISTS, CFDTMC[4], CFDTMSTS[4], CFDTMTRSTS[1], CFDTMTARSTS[1], CFDTMTCSTS[1], CFDTMTASTS[1], CFDTMIEC[1], CFDTXQCC0[1], CFDTXQSTS0[1], CFDTXQPCTR0[1], CFDTHLCC[1], CFDTHLSTS[1], CFDTHLPCTR[1], CFDGTINTSTS0, CFDGTSTCFG, CFDGTSTCTR, CFDGFDCFG, CFDGLOCKK, CFDGAFLIGNENT, CFDGAFLIGNCTR, CFDCDTCT, CFDCDTSTS, CFDGRSTC)
• 0x100 .. 0x11F : per-channel CFDC2[1] = { DCFG, FDCFG, FDCTR, FDSTS, FDCRC }
• 0x120 .. 0x21F : CFDGAFL[16] acceptance-filter list page window
• 0x280 .. 0x37F : CFDRPGACC[64] RAM-test page-access window
• 0x520 .. 0x5B7 : CFDRF[2] RX FIFO access (ID/PTR/FDSTS/DF[64])
• 0x5B8 .. 0x603 : CFDCF[1] common FIFO access
• 0x604 .. 0x73F : CFDTM[4] TX message buffer access
• 0x740 .. 0x747 : CFDTHL[1] TX history list
• 0x920 .. 0x191F: CFDRM[4] RX message-buffer cluster

Field shifts / masks below come from the FSP R7KA8D2KF_core0.h bit-field unions and from HUM Ch 41 "CAN with Flexible Data-rate (CANFD)" pages 2702..2867 (chapter map row 41).

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_canfd_regs.h.

Enumeration Type Documentation

ra8_canfd_addr_t

enum ra8_canfd_addr_t : uintptr_t

Enumerator
k_ra8_canfd0_base_addr	HUM Ch 41 p 2702 channel 0 base.
k_ra8_canfd1_base_addr	HUM Ch 41 p 2702 channel 1 base.

Definition at line 64 of file ra8_canfd_regs.h.

ra8_canfd_afl_total_t

enum ra8_canfd_afl_total_t : uint16_t

Maximum number of GAFL filter rules across all paged windows.

The CFDGAFLECTR.AFLPN field is 4 bits wide so the controller can page through at most 16 windows. Each window exposes 16 entries (k_ra8_canfd_afl_page_size), giving 256 total filters. HUM Ch 41 "Acceptance Filter List" pp 2702-2867.

Enumerator
k_ra8_canfd_afl_total	16 pages x 16 entries.

Definition at line 640 of file ra8_canfd_regs.h.

ra8_canfd_bit_timing_limits_t

enum ra8_canfd_bit_timing_limits_t : uint32_t

Prescaler / TSEG / SJW resolution bounds shared by both phases.

Enumerator
k_ra8_canfd_tq_per_bit	Default time quanta per bit.
k_ra8_canfd_prescaler_min	Smallest valid prescaler.
k_ra8_canfd_prescaler_max	Largest valid nominal prescaler.
k_ra8_canfd_data_prescaler_max	Largest valid data prescaler (8-bit).
k_ra8_canfd_sjw_max	Nominal SJW cap.
k_ra8_canfd_dsjw_max	Data-phase SJW cap.
k_ra8_canfd_dtseg1_max	Data-phase TSEG1 cap.
k_ra8_canfd_dtseg2_max	Data-phase TSEG2 cap.

Definition at line 473 of file ra8_canfd_regs.h.

ra8_canfd_fd_bits_t

enum ra8_canfd_fd_bits_t : uint32_t

Enumerator
k_ra8_canfd_fd_esi	ESI: error state indicator.
k_ra8_canfd_fd_brs	BRS: bit-rate switch.
k_ra8_canfd_fd_fdf	FDF: frame is CAN-FD.

Definition at line 683 of file ra8_canfd_regs.h.

ra8_canfd_frame_limits_t

enum ra8_canfd_frame_limits_t : uint8_t

Message-frame limits common to the public API and register layer.

Enumerator
k_ra8_canfd_data_bytes_max	CAN-FD payload cap in bytes.
k_ra8_canfd_dlc_max	4-bit DLC max value (64 bytes).

Definition at line 83 of file ra8_canfd_regs.h.

ra8_canfd_gfdcfg_bits_t

enum ra8_canfd_gfdcfg_bits_t : uint32_t

CFDGFDCFG (Global FD Config) field positions.

From FSP R_CANFD_CFDGFDCFG_b – bit 0 is NISO (1 = ISO 11898-1 stuff-count / CRC, 0 = original Bosch non-ISO framing).

Enumerator
k_ra8_gfdcfg_bit_niso	NISO: ISO mode select.

Definition at line 652 of file ra8_canfd_regs.h.

ra8_canfd_id_bits_t

enum ra8_canfd_id_bits_t : uint32_t

Enumerator
k_ra8_canfd_id_std_mask	11-bit standard ID.
k_ra8_canfd_id_ext_mask	29-bit extended ID.
k_ra8_canfd_id_thlen	TX history-list enable.
k_ra8_canfd_id_rtr	RTR: remote frame.
k_ra8_canfd_id_ide	IDE: extended flag.

Definition at line 666 of file ra8_canfd_regs.h.

ra8_canfd_limits_t

enum ra8_canfd_limits_t : uint8_t

Enumerator
k_ra8_canfd_instance_count	Number of CANFD channels.
k_ra8_canfd_rx_fifo_count	CFDRFCC / CFDRFSTS array length.
k_ra8_canfd_cf_count	Common-FIFO array length.
k_ra8_canfd_tx_mb_count	CFDTM / CFDTMC / CFDTMSTS length.
k_ra8_canfd_afl_page_size	CFDGAFL[] page-window size.
k_ra8_canfd_rm_per_cluster	RX MB entries per cluster.
k_ra8_canfd_rm_clusters	CFDRM cluster array length.

Definition at line 69 of file ra8_canfd_regs.h.

ra8_canfd_pad_t

enum ra8_canfd_pad_t : uint16_t

Reserved-region sizes between FSP-named registers.

Each value covers a documented gap in the RA8D2 R_CANFD_Type memory map (see HUM Ch 41 register-list table and FSP R7KA8D2KF_core0.h::R_CANFD_Type). Naming them keeps the layout literal-free and lets clang-tidy readability-magic-numbers stay happy.

Enumerator
k_ra8_canfd_pad_cfdc2_tail_bytes	CFDC2 reserved tail (3 words).
k_ra8_canfd_pad_rm_cluster_words	CFDRM cluster pad (0x1A0/4).
k_ra8_canfd_pad_before_grstc	0x0D0..0x0D7 -> 2 words.
k_ra8_canfd_pad_after_grstc_words	0x0DC..0x0FF -> 9 words.
k_ra8_canfd_pad_before_rpgacc	0x220..0x27F -> 24 words.
k_ra8_canfd_rpgacc_word_count	CFDRPGACC[64] RAM-test page.
k_ra8_canfd_pad_before_rf_words	0x380..0x51F -> 104 words.
k_ra8_canfd_pad_before_thl_words	0x734..0x73F -> 3 words.
k_ra8_canfd_pad_before_rm_words	0x748..0x91F -> 118 words.

Definition at line 99 of file ra8_canfd_regs.h.

ra8_canfd_ptr_mask_t

enum ra8_canfd_ptr_mask_t : uint32_t

Enumerator
k_ra8_canfd_ptr_mask_dlc	4-bit DLC mask.

Definition at line 699 of file ra8_canfd_regs.h.

ra8_canfd_ptr_shift_t

enum ra8_canfd_ptr_shift_t : uint8_t

Enumerator
k_ra8_canfd_ptr_shift_dlc	DLC field shift.

Definition at line 695 of file ra8_canfd_regs.h.

ra8_canfd_tdc_limits_t

enum ra8_canfd_tdc_limits_t : uint8_t

Bounds on the Transmitter Delay Compensation Offset field.

TDCO is a 7-bit field at FDCFG[14:8], so the offset must not exceed k_ra8_canfd_tdc_offset_max (0x7F = 127). A value of zero is legal and represents a zero-TQ offset when TDE is set. HUM Ch 41 "CFDCnFDCFG" p 2788.

See also

ra8_canfd_set_tdc()

Since

0.1.0

Enumerator
k_ra8_canfd_tdc_offset_max	Maximum TDCO value: 7-bit field cap.

Definition at line 791 of file ra8_canfd_regs.h.

ra8_canfd_tmc_bits_t

enum ra8_canfd_tmc_bits_t : uint8_t

Enumerator
k_ra8_canfd_tmc_txreq	TMTR: transmit request.
k_ra8_canfd_tmc_abort	TMTAR: abort request.
k_ra8_canfd_tmc_oneshot	TMOM: one-shot mode.

Definition at line 709 of file ra8_canfd_regs.h.

ra8_chmdc_mode_t

enum ra8_chmdc_mode_t : uint8_t

Channel Mode Control (CFDC[0].CTR.CHMDC[1:0]) values.

Enumerator
k_ra8_chmdc_operation	Bus operation mode.
k_ra8_chmdc_reset	Reset mode.
k_ra8_chmdc_halt	Halt mode.
k_ra8_chmdc_keep	Keep current mode.

Definition at line 394 of file ra8_canfd_regs.h.

ra8_cncfg_mask_t

enum ra8_cncfg_mask_t : uint32_t

Enumerator
k_ra8_cncfg_mask_nbrp	[9:0] 10-bit prescaler field.
k_ra8_cncfg_mask_nsjw	[16:10] 7-bit SJW field.
k_ra8_cncfg_mask_ntseg1	[24:17] 8-bit TSEG1 field.
k_ra8_cncfg_mask_ntseg2	[31:25] 7-bit TSEG2 field.

Definition at line 440 of file ra8_canfd_regs.h.

ra8_cncfg_shift_t

enum ra8_cncfg_shift_t : uint8_t

Enumerator
k_ra8_cncfg_shift_nbrp	RA8 cncfg shift nbrp.
k_ra8_cncfg_shift_nsjw	RA8 cncfg shift nsjw.
k_ra8_cncfg_shift_ntseg1	RA8 cncfg shift ntseg1.
k_ra8_cncfg_shift_ntseg2	RA8 cncfg shift ntseg2.

Definition at line 433 of file ra8_canfd_regs.h.

ra8_cnctr_bit_t

enum ra8_cnctr_bit_t : uint8_t

Enumerator
k_ra8_cnctr_bit_chmdc	Channel Mode Control [1:0].
k_ra8_cnctr_bit_cslpr	Channel Sleep Request bit 2.
k_ra8_cnctr_bit_bom	Bus-Off Mode [22:21].
k_ra8_cnctr_bit_ctme	Channel Test Mode Enable bit 24.
k_ra8_cnctr_bit_ctms	Channel Test Mode Select [26:25].

Definition at line 359 of file ra8_canfd_regs.h.

ra8_cnctr_mask_t

enum ra8_cnctr_mask_t : uint32_t

Enumerator
k_ra8_cnctr_mask_chmdc	2-bit CHMDC mask.
k_ra8_cnctr_mask_cslpr	CSLPR (bit 2).
k_ra8_cnctr_mask_ctme	CTME bit 24.
k_ra8_cnctr_mask_ctms	CTMS[1:0] at bits [26:25].

Definition at line 367 of file ra8_canfd_regs.h.

ra8_cnerfl_mask_t

enum ra8_cnerfl_mask_t : uint32_t

Enumerator
k_ra8_cnerfl_mask_bef	RA8 cnerfl mask bef.
k_ra8_cnerfl_mask_ewf	RA8 cnerfl mask ewf.
k_ra8_cnerfl_mask_epf	RA8 cnerfl mask epf.
k_ra8_cnerfl_mask_boef	RA8 cnerfl mask boef.
k_ra8_cnerfl_mask_borf	RA8 cnerfl mask borf.
k_ra8_cnerfl_mask_ovlf	RA8 cnerfl mask ovlf.
k_ra8_cnerfl_mask_blf	RA8 cnerfl mask blf.
k_ra8_cnerfl_mask_alf	RA8 cnerfl mask alf.
k_ra8_cnerfl_mask_serr	RA8 cnerfl mask serr.
k_ra8_cnerfl_mask_ferr	RA8 cnerfl mask ferr.
k_ra8_cnerfl_mask_aerr	RA8 cnerfl mask aerr.
k_ra8_cnerfl_mask_cerr	RA8 cnerfl mask cerr.
k_ra8_cnerfl_mask_b1err	RA8 cnerfl mask b1err.
k_ra8_cnerfl_mask_b0err	RA8 cnerfl mask b0err.
k_ra8_cnerfl_mask_aderr	RA8 cnerfl mask aderr.
k_ra8_cnerfl_mask_all_w1c	[14:0] all writable error bits.

Definition at line 495 of file ra8_canfd_regs.h.

ra8_cnsts_bit_t

enum ra8_cnsts_bit_t : uint8_t

Enumerator
k_ra8_cnsts_bit_crstst	Channel Reset Status.
k_ra8_cnsts_bit_chltst	Channel Halt Status.
k_ra8_cnsts_bit_cslpst	Channel Sleep Status.
k_ra8_cnsts_bit_epst	Error Passive Status.
k_ra8_cnsts_bit_bosts	Bus-Off Status.
k_ra8_cnsts_bit_rec	REC[23:16] in STS.
k_ra8_cnsts_bit_tec	TEC[31:24] in STS.

Definition at line 409 of file ra8_canfd_regs.h.

ra8_cnsts_mask_t

enum ra8_cnsts_mask_t : uint32_t

Enumerator
k_ra8_cnsts_mask_rec	REC field mask (post-shift).
k_ra8_cnsts_mask_tec	TEC field mask (post-shift).

Definition at line 419 of file ra8_canfd_regs.h.

ra8_ctms_mode_t

enum ra8_ctms_mode_t : uint8_t

Channel Test Mode Select values (CFDC[0].CTR.CTMS[1:0]).

HUM Ch 41 "CFDCnCTR" p 2710 – CTMS is bits [26:25] of CTR and is only writable while the channel is in CH_HALT mode. Selecting any test mode requires CTME (bit 24) to be set in the same write.

Enumerator
k_ra8_ctms_basic	00b: Basic test mode (CRC observation).
k_ra8_ctms_listen_only	01b: Listen-only mode.
k_ra8_ctms_self_test_0	10b: Self-test 0 (external loopback).
k_ra8_ctms_self_test_1	11b: Self-test 1 (internal loopback).

Definition at line 383 of file ra8_canfd_regs.h.

ra8_dcfg_mask_t

enum ra8_dcfg_mask_t : uint32_t

Enumerator
k_ra8_dcfg_mask_dbrp	[7:0] 8-bit DBRP.
k_ra8_dcfg_mask_dtseg1	[12:8] 5-bit DTSEG1.
k_ra8_dcfg_mask_dtseg2	[19:16] 4-bit DTSEG2.
k_ra8_dcfg_mask_dsjw	[27:24] 4-bit DSJW.

Definition at line 462 of file ra8_canfd_regs.h.

ra8_dcfg_shift_t

enum ra8_dcfg_shift_t : uint8_t

Enumerator
k_ra8_dcfg_shift_dbrp	RA8 dcfg shift dbrp.
k_ra8_dcfg_shift_dtseg1	RA8 dcfg shift dtseg1.
k_ra8_dcfg_shift_dtseg2	RA8 dcfg shift dtseg2.
k_ra8_dcfg_shift_dsjw	RA8 dcfg shift dsjw.

Definition at line 455 of file ra8_canfd_regs.h.

ra8_fdcfg_mask_t

enum ra8_fdcfg_mask_t : uint32_t

Bit masks for the TDC fields in CFDCnFDCFG.

k_ra8_fdcfg_mask_tdco is the pre-shift 7-bit mask for the TDCO offset field; apply it as (offset & k_ra8_fdcfg_mask_tdco) << k_ra8_fdcfg_shift_tdco. k_ra8_fdcfg_mask_tdcoc and k_ra8_fdcfg_mask_tde are positioned masks (already at their register bit positions). HUM Ch 41 "CFDCnFDCFG" p 2788.

See also

ra8_fdcfg_shift_t

ra8_canfd_set_tdc()

Since

0.1.0

Enumerator
k_ra8_fdcfg_mask_tdco	TDCO pre-shift 7-bit mask.
k_ra8_fdcfg_mask_tdcoc	TDCOC positioned mask (bit 15).
k_ra8_fdcfg_mask_tde	TDE positioned mask (bit 16).

Definition at line 772 of file ra8_canfd_regs.h.

ra8_fdcfg_shift_t

enum ra8_fdcfg_shift_t : uint8_t

Bit-shift positions for the TDC fields in CFDCnFDCFG.

TDCO is a 7-bit offset at [14:8]; TDCOC is the offset-control select bit at [15]; TDE is the enable gate at [16]. Together these three fields govern Transmitter Delay Compensation. HUM Ch 41 "CFDCnFDCFG" p 2788.

See also

ra8_fdcfg_mask_t

ra8_canfd_set_tdc()

Since

0.1.0

Enumerator
k_ra8_fdcfg_shift_tdco	TDCO[14:8]: 7-bit TDC offset bit-shift.
k_ra8_fdcfg_shift_tdcoc	TDCOC[15]: TDC offset-control bit-shift.
k_ra8_fdcfg_shift_tde	TDE[16]: TDC enable bit-shift.

Definition at line 750 of file ra8_canfd_regs.h.

ra8_fdsts_mask_t

enum ra8_fdsts_mask_t : uint32_t

Bit mask for the TDCR read-only measurement in CFDCnFDSTS.

Reading and masking with k_ra8_fdsts_mask_tdcr extracts the 8-bit measured transmitter loop delay from FDSTS[7:0]. Compare it against FDCFG.TDCO to tune the manual offset. HUM Ch 41 "CFDCnFDSTS" p 2792.

See also

ra8_canfd_set_tdc()

Since

0.1.0

Enumerator
k_ra8_fdsts_mask_tdcr	TDCR[7:0]: 8-bit measured TDC result.

Definition at line 821 of file ra8_canfd_regs.h.

ra8_gaflcfg0_bits_t

enum ra8_gaflcfg0_bits_t : uint32_t

CFDGAFLCFG0 layout (HUM Ch 41.2.18 p 2735).

RNC0[20:16] selects how many rules on page 0 the AFL consults. Only writable in GL_RESET.

Enumerator
k_ra8_gaflcfg0_shift_rnc0	Position of RNC0[4:0].
k_ra8_gaflcfg0_mask_rnc0	RNC0 field is 5 bits.

Definition at line 588 of file ra8_canfd_regs.h.

ra8_gaflectr_bits_t

enum ra8_gaflectr_bits_t : uint32_t

Enumerator
k_ra8_gaflectr_mask_aflpn	RA8 gaflectr mask aflpn.
k_ra8_gaflectr_bit_afldae	RA8 gaflectr bit afldae.

Definition at line 576 of file ra8_canfd_regs.h.

ra8_gaflm_bits_t

enum ra8_gaflm_bits_t : uint32_t

CFDGAFLM (Acceptance Filter Mask) layout (HUM Ch 41.2.20 p 2736).

Bit 29 GAFLLB is "Loopback Configuration": when 0 the AFL entry is only valid for standard non-loopback RX; when 1 the AFL entry is also valid in Self-test mode 0/1 (HUM Ch 41.5.5 Table 41.22). For internal-loopback demos (canfd_loopback, canfd_filter_demo) GAFLLB must be set, otherwise every loopback frame passes the filter and a no-match round wrongly receives data.

Bits 30/31 are the per-field compare-enable mask bits that sit at the same positions as GAFLRTR / GAFLIDE in the CFDGAFLID word: GAFLRTRM (bit 30) makes the RTR flag part of the acceptance match, and GAFLIDEM (bit 31) makes the IDE flag part of the match so a standard rule does not accidentally accept an extended frame whose low ID bits coincide. Both are 1 = compare, 0 = don't-care (HUM Ch 41.2.20 "CFDGAFLM : Acceptance Filter List ID Mask Register" p 2736).

Enumerator
k_ra8_gaflm_bit_gafllb	Loopback Configuration bit.
k_ra8_gaflm_bit_gaflrtrm	RTR-compare mask bit.
k_ra8_gaflm_bit_gaflidem	IDE-compare mask bit.

Definition at line 624 of file ra8_canfd_regs.h.

ra8_gaflp1_bits_t

enum ra8_gaflp1_bits_t : uint32_t

CFDGAFLP1r layout (HUM Ch 41.2.22 p 2740).

Bit 0 GAFLFDP0 = route matched frame into RX FIFO 0. At least one of the GAFLFDPn bits MUST be set or the matched frame is dropped instead of being routed.

Enumerator
k_ra8_gaflp1_bit_gaflfdp0	Route to RX FIFO 0.

Definition at line 601 of file ra8_canfd_regs.h.

ra8_gctr_bit_t

enum ra8_gctr_bit_t : uint8_t

Enumerator
k_ra8_gctr_bit_gmdc	GMDC field [1:0].
k_ra8_gctr_bit_gslpr	Global Sleep Request bit.

Definition at line 521 of file ra8_canfd_regs.h.

ra8_gctr_value_t

enum ra8_gctr_value_t : uint32_t

Enumerator
k_ra8_gctr_mask_gmdc	2-bit GMDC mask.
k_ra8_gctr_mask_gslpr	RA8 gctr mask gslpr.
k_ra8_gctr_value_operation	GMDC = 0: operation.
k_ra8_gctr_value_reset	GMDC = 1: reset.
k_ra8_gctr_value_halt	GMDC = 2: halt.

Definition at line 526 of file ra8_canfd_regs.h.

ra8_gsts_bit_t

enum ra8_gsts_bit_t : uint8_t

Global Status (CFDGSTS) bit positions.

Enumerator
k_ra8_gsts_bit_grststs	Global Reset Status.
k_ra8_gsts_bit_ghltsts	Global Halt Status.
k_ra8_gsts_bit_gslpsts	Global Sleep Status.
k_ra8_gsts_bit_graminit	Global RAM Initialisation.

Definition at line 538 of file ra8_canfd_regs.h.

ra8_rfcc_bits_t

enum ra8_rfcc_bits_t : uint32_t

Enumerator
k_ra8_rfcc_bit_rfe	RFE: enable FIFO.
k_ra8_rfcc_bit_rfie	RFIE: interrupt enable.

Definition at line 552 of file ra8_canfd_regs.h.

ra8_rfpctr_bits_t

enum ra8_rfpctr_bits_t : uint32_t

Enumerator
k_ra8_rfpctr_value_ack	Dummy write to pop entry.

Definition at line 564 of file ra8_canfd_regs.h.

ra8_rfsts_bits_t

enum ra8_rfsts_bits_t : uint32_t

Enumerator
k_ra8_rfsts_bit_empty	RFEMP: FIFO empty flag.
k_ra8_rfsts_bit_full	RFFLL: FIFO full flag.
k_ra8_rfsts_bit_mlt	RFMLT: message lost.
k_ra8_rfsts_bit_if	RFIF: interrupt flag.

Definition at line 557 of file ra8_canfd_regs.h.

Function Documentation

ra8_canfd()

volatile r_canfd_t * ra8_canfd ( uint8_t channel )

inlinestatic

Get pointer to CANFD instance N (0..1).

Definition at line 341 of file ra8_canfd_regs.h.

References k_ra8_canfd0_base_addr, k_ra8_canfd1_base_addr, and k_ra8_canfd_instance_count.

Referenced by internal_canfd_demo_setup_or_halt(), ra8_canfd_clear_status(), ra8_canfd_deinit(), ra8_canfd_dispatch(), ra8_canfd_filter_set(), ra8_canfd_get_error_state(), ra8_canfd_get_status(), ra8_canfd_init(), ra8_canfd_receive(), ra8_canfd_set_accept_filter(), ra8_canfd_set_bitrate(), ra8_canfd_set_brs(), ra8_canfd_set_iso_mode(), ra8_canfd_set_tdc(), ra8_canfd_set_test_mode(), and ra8_canfd_transmit().