ra8_canfd_frame.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_canfd.h"
#include "ra8_canfd_regs.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
 
static const char* s_tag = "CANFD";

typedef enum : uint32_t {
  k_ra8_canfd_tx_spin = 100000U, 
} ra8_canfd_frame_spin_t;

typedef enum : uint8_t {
  k_ra8_canfd_tx_mb_default   = 0U, 
  k_ra8_canfd_rx_fifo_default = 0U, 
} ra8_canfd_buffer_idx_t;

RA8_INTERNAL
static ra8_err_t internal_validate_frame(const ra8_canfd_frame_t* frame)
{
  if (frame->dlc > k_ra8_canfd_dlc_max) {
    return k_ra8_err_invalid_arg;
  }
  if (frame->is_extended == 0U) {
    if ((frame->id & ~k_ra8_canfd_id_std_mask) != 0U) {
      return k_ra8_err_invalid_arg;
    }
  } else {
    if ((frame->id & ~k_ra8_canfd_id_ext_mask) != 0U) {
      return k_ra8_err_invalid_arg;
    }
  }
  if ((frame->is_brs != 0U) && (frame->is_fd == 0U)) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static void internal_write_tx_data(volatile r_canfd_t* reg, const ra8_canfd_frame_t* frame)
{
  for (uint8_t b = 0U; b < k_ra8_canfd_data_bytes_max; b++) {
    reg->CFDTM[k_ra8_canfd_tx_mb_default].DF[b] = frame->data[b];
  }
}

RA8_INTERNAL
static uint32_t internal_tx_id(const ra8_canfd_frame_t* frame)
{
  const uint32_t masked = (frame->is_extended != 0U) ? (frame->id & k_ra8_canfd_id_ext_mask)
                                                     : (frame->id & k_ra8_canfd_id_std_mask);
  return (frame->is_extended != 0U) ? (masked | k_ra8_canfd_id_ide) : masked;
}

RA8_INTERNAL
static uint32_t internal_tx_fdctr(const ra8_canfd_frame_t* frame)
{
  uint32_t w = 0U;
  if (frame->is_fd != 0U) {
    w |= k_ra8_canfd_fd_fdf;
  }
  if (frame->is_brs != 0U) {
    w |= k_ra8_canfd_fd_brs;
  }
  return w;
}

RA8_INTERNAL
static void internal_wait_tx_complete(volatile r_canfd_t* reg)
{
  enum : uint8_t { k_ra8_tmsts_tmtrf_done = 0x04U  };
  for (uint32_t i = 0U; i < k_ra8_canfd_tx_spin; i++) {
#if defined(RA8_OFF_TARGET) && defined(UNIT_TEST)
    if (ra8_fake_mmio_wait_eval(
          &reg->CFDTMSTS[k_ra8_canfd_tx_mb_default],
          i,
          ((reg->CFDTMSTS[k_ra8_canfd_tx_mb_default] & k_ra8_tmsts_tmtrf_done) != 0U))) {
      break;
    }
#else
    if ((reg->CFDTMSTS[k_ra8_canfd_tx_mb_default] & k_ra8_tmsts_tmtrf_done) != 0U) {
      break;
    }
#endif
  }
}
 
ra8_err_t ra8_canfd_transmit(uint8_t channel, const ra8_canfd_frame_t* frame)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  RA8_CHECK_NULL_PTR(frame, s_tag, "frame must not be nullptr");
 
  const ra8_err_t v = internal_validate_frame(frame);
  if (v != k_ra8_ok) {
    return v;
  }
 
  /* Clear the previous transmission's TMTRF before asserting TXREQ:
   * HUM Ch 41 "CFDTMSTSj.TMTRF" p ~2756 says TMTR is only honored when
   * TMTRF is 00b. After the first successful TX the chip leaves
   * TMTRF=10b ("transmission successful") and silently drops every
   * subsequent TXREQ -- the symptom is the first round-trip working
   * and every later one returning no_data. */
  reg->CFDTMSTS[k_ra8_canfd_tx_mb_default] = 0U;
 
  /* HUM Ch 41 p 2806 "CFDTMID/CFDTMPTR/CFDTMFDCTR/CFDTMDF" +
   * FSP r_canfd.c line ~668..684. */
  reg->CFDTM[k_ra8_canfd_tx_mb_default].ID    = internal_tx_id(frame);
  reg->CFDTM[k_ra8_canfd_tx_mb_default].PTR   = ((uint32_t)frame->dlc & k_ra8_canfd_ptr_mask_dlc)
                                                << (uint32_t)k_ra8_canfd_ptr_shift_dlc;
  reg->CFDTM[k_ra8_canfd_tx_mb_default].FDCTR = internal_tx_fdctr(frame);
  internal_write_tx_data(reg, frame);
 
  /* HUM Ch 41 p 2810 "CFDTMC" -- single-byte transmit-request register.
   * FSP r_canfd.c line ~724: `p_reg->CFDTMC[idx] = 1`. */
  reg->CFDTMC[k_ra8_canfd_tx_mb_default] = k_ra8_canfd_tmc_txreq;
 
  internal_wait_tx_complete(reg);
  return k_ra8_ok;
}

RA8_INTERNAL
static void internal_read_rx_data(volatile r_canfd_t* reg, ra8_canfd_frame_t* out)
{
  for (uint8_t b = 0U; b < k_ra8_canfd_data_bytes_max; b++) {
    out->data[b] = reg->CFDRF[k_ra8_canfd_rx_fifo_default].DF[b];
  }
}

RA8_INTERNAL
static void internal_decode_rx_header(uint32_t           id_word,
                                      uint32_t           ptr_word,
                                      uint32_t           fdsts_word,
                                      ra8_canfd_frame_t* out)
{
  const uint8_t is_ext = (uint8_t)(((id_word & k_ra8_canfd_id_ide) != 0U) ? 1U : 0U);
  out->is_extended     = is_ext;
  out->id =
    (is_ext != 0U) ? (id_word & k_ra8_canfd_id_ext_mask) : (id_word & k_ra8_canfd_id_std_mask);
  out->dlc =
    (uint8_t)((ptr_word >> (uint32_t)k_ra8_canfd_ptr_shift_dlc) & k_ra8_canfd_ptr_mask_dlc);
  out->is_fd  = ((fdsts_word & k_ra8_canfd_fd_fdf) != 0U) ? 1U : 0U;
  out->is_brs = ((fdsts_word & k_ra8_canfd_fd_brs) != 0U) ? 1U : 0U;
}
 
ra8_err_t ra8_canfd_receive(uint8_t channel, ra8_canfd_frame_t* out_frame)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  RA8_CHECK_NULL_PTR(out_frame, s_tag, "out_frame must not be nullptr");
 
  /* HUM Ch 41 "CFDRFSTSn.RFEMP" p 2754 */ /* "CFDRFSTSn.RFEMP" -- empty flag is bit 0. */
  if ((reg->CFDRFSTS[k_ra8_canfd_rx_fifo_default] & k_ra8_rfsts_bit_empty) != 0U) {
    return k_ra8_err_no_data;
  }
 
  /* HUM Ch 41 "CFDRFn ID/PTR/FDSTS/DF" p 2796 */ /* "CFDRFn ID/PTR/FDSTS/DF". */
  internal_decode_rx_header(reg->CFDRF[k_ra8_canfd_rx_fifo_default].ID,
                            reg->CFDRF[k_ra8_canfd_rx_fifo_default].PTR,
                            reg->CFDRF[k_ra8_canfd_rx_fifo_default].FDSTS,
                            out_frame);
  internal_read_rx_data(reg, out_frame);
 
  /* HUM Ch 41 p 2756 "CFDRFPCTRn.RFPC" -- write 0xFF to advance pointer.
   * FSP r_canfd.c uses the same dummy 0xFF write to pop. */
  reg->CFDRFPCTR[k_ra8_canfd_rx_fifo_default] = k_ra8_rfpctr_value_ack;
  return k_ra8_ok;
}
 
ra8_err_t ra8_canfd_get_error_state(uint8_t channel, uint8_t* tx_err, uint8_t* rx_err)
{
  volatile r_canfd_t* reg = ra8_canfd(channel);
  RA8_CHECK_NULL_PTR(reg, s_tag, "channel out of range");
  RA8_CHECK_NULL_PTR(tx_err, s_tag, "tx_err must not be nullptr");
  RA8_CHECK_NULL_PTR(rx_err, s_tag, "rx_err must not be nullptr");
 
  /* HUM Ch 41 p 2766 "CFDCnSTS" -- TEC[31:24] / REC[23:16] live in
   * CFDC[0].STS, NOT in CFDC[0].ERFL like the previous header model. */
  const uint32_t sts = reg->CFDC[0].STS;
  *tx_err            = (uint8_t)((sts >> (uint32_t)k_ra8_cnsts_bit_tec) & k_ra8_cnsts_mask_tec);
  *rx_err            = (uint8_t)((sts >> (uint32_t)k_ra8_cnsts_bit_rec) & k_ra8_cnsts_mask_rec);
  return k_ra8_ok;
}