ra8_canfd_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
 
/* =============================================================================
 * Base addresses
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_canfd0_base_addr = 0x40380000UL, 
  k_ra8_canfd1_base_addr = 0x40382000UL, 
} ra8_canfd_addr_t;
 
typedef enum : uint8_t {
  k_ra8_canfd_instance_count = 2U,  
  k_ra8_canfd_rx_fifo_count  = 2U,  
  k_ra8_canfd_cf_count       = 1U,  
  k_ra8_canfd_tx_mb_count    = 4U,  
  k_ra8_canfd_afl_page_size  = 16U, 
  k_ra8_canfd_rm_per_cluster = 8U,  
  k_ra8_canfd_rm_clusters    = 4U,  
} ra8_canfd_limits_t;

typedef enum : uint8_t {
  k_ra8_canfd_data_bytes_max = 64U, 
  k_ra8_canfd_dlc_max        = 15U, 
} ra8_canfd_frame_limits_t;

typedef enum : uint16_t {
  k_ra8_canfd_pad_cfdc2_tail_bytes  = 12U,  
  k_ra8_canfd_pad_rm_cluster_words  = 104U, 
  k_ra8_canfd_pad_before_grstc      = 2U,   
  k_ra8_canfd_pad_after_grstc_words = 9U,   
  k_ra8_canfd_pad_before_rpgacc     = 24U,  
  k_ra8_canfd_rpgacc_word_count     = 64U,  
  k_ra8_canfd_pad_before_rf_words   = 104U, 
  k_ra8_canfd_pad_before_thl_words  = 3U,   
  k_ra8_canfd_pad_before_rm_words   = 118U, 
} ra8_canfd_pad_t;
 
/* =============================================================================
 * Per-channel control block (CFDC[0])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDC_Type` (size 0x10):
 *   +0x00 NCFG  Nominal-bitrate config
 *   +0x04 CTR   Channel control
 *   +0x08 STS   Channel status (TEC[31:24], REC[23:16] live here)
 *   +0x0C ERFL  Channel error flags / CRC value
 */
typedef struct {
  volatile uint32_t NCFG; 
  volatile uint32_t CTR;  
  volatile uint32_t STS;  
  volatile uint32_t ERFL; 
} r_canfd_cfdc_t;
 
/* =============================================================================
 * Per-channel CAN-FD config block (CFDC2[0])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDC2_Type` (size 0x20):
 *   +0x00 DCFG    Data-bitrate config
 *   +0x04 FDCFG   CAN-FD config (TDC, FDOE, REFE, CLOE, ESIC)
 *   +0x08 FDCTR   CAN-FD control (EOCCLR, SOCCLR)
 *   +0x0C FDSTS   CAN-FD status (TDC result, EOC/SOC counters)
 *   +0x10 FDCRC   CAN-FD CRC + stuff-bit count
 *   +0x14 .. 0x1F reserved (3 words)
 */
typedef struct {
  volatile uint32_t DCFG;                                        
  volatile uint32_t FDCFG;                                       
  volatile uint32_t FDCTR;                                       
  volatile uint32_t FDSTS;                                       
  volatile uint32_t FDCRC;                                       
  volatile uint8_t  _reserved[k_ra8_canfd_pad_cfdc2_tail_bytes]; 
} r_canfd_cfdc2_t;
 
/* =============================================================================
 * Acceptance-filter-list entry (CFDGAFL[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDGAFL_Type` (size 0x10) -- the AFL is paged through a
 * 16-entry page window. Set CFDGAFLECTR.AFLPN to select the page.
 */
typedef struct {
  volatile uint32_t ID; 
  volatile uint32_t M;  
  volatile uint32_t P0; 
  volatile uint32_t P1; 
} r_canfd_cfdgafl_t;
 
/* =============================================================================
 * RX FIFO access registers (CFDRF[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDRF_Type` (size 0x4C).
 */
typedef struct {
  volatile uint32_t ID;                             
  volatile uint32_t PTR;                            
  volatile uint32_t FDSTS;                          
  volatile uint8_t  DF[k_ra8_canfd_data_bytes_max]; 
} r_canfd_cfdrf_t;
 
/* =============================================================================
 * Common FIFO access registers (CFDCF[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDCF_Type` (size 0x4C).
 */
typedef struct {
  volatile uint32_t ID;                             
  volatile uint32_t PTR;                            
  volatile uint32_t FDSTS;                          
  volatile uint8_t  DF[k_ra8_canfd_data_bytes_max]; 
} r_canfd_cfdcf_t;
 
/* =============================================================================
 * TX message-buffer access registers (CFDTM[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDTM_Type` (size 0x4C).
 */
typedef struct {
  volatile uint32_t ID;                             
  volatile uint32_t PTR;                            
  volatile uint32_t FDCTR;                          
  volatile uint8_t  DF[k_ra8_canfd_data_bytes_max]; 
} r_canfd_cfdtm_t;
 
/* =============================================================================
 * TX history list (CFDTHL[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDTHL_Type` (size 0x8).
 */
typedef struct {
  volatile uint32_t ACC0; 
  volatile uint32_t ACC1; 
} r_canfd_cfdthl_t;
 
/* =============================================================================
 * RX message-buffer cluster (CFDRM[i])
 * =============================================================================
 *
 * FSP `R_CANFD_CFDRM_Type` (size 0x400) -- 8 RM entries (each 0x4C)
 * followed by 0x1A0 of reserved padding.
 */
typedef struct {
  volatile uint32_t ID;                             
  volatile uint32_t PTR;                            
  volatile uint32_t FDSTS;                          
  volatile uint8_t  DF[k_ra8_canfd_data_bytes_max]; 
} r_canfd_cfdrm_entry_t;
 
typedef struct {
  r_canfd_cfdrm_entry_t RM[k_ra8_canfd_rm_per_cluster]; 
  volatile uint32_t     _reserved[k_ra8_canfd_pad_rm_cluster_words];
} r_canfd_cfdrm_t;
 
/* =============================================================================
 * Aggregate channel block (R_CANFD0 / R_CANFD1)
 * =============================================================================
 */
typedef struct {
  /* 0x000 -- per-channel control */
  r_canfd_cfdc_t    CFDC[1];       
  volatile uint32_t _r_after_cfdc; 
 
  /* 0x014 -- global control (per-instance copy) */
  volatile uint32_t CFDGCFG;     
  volatile uint32_t CFDGCTR;     
  volatile uint32_t CFDGSTS;     
  volatile uint32_t CFDGERFL;    
  volatile uint32_t CFDGTSC;     
  volatile uint32_t CFDGAFLECTR; 
  volatile uint32_t CFDGAFLCFG0; 
  volatile uint32_t CFDRMNB;     
  volatile uint32_t CFDRMND0;    
  volatile uint32_t CFDRMIEC;    
  volatile uint32_t
    CFDRFCC[k_ra8_canfd_rx_fifo_count]; 
  volatile uint32_t
    CFDRFSTS[k_ra8_canfd_rx_fifo_count]; 
  volatile uint32_t
    CFDRFPCTR[k_ra8_canfd_rx_fifo_count];              
  volatile uint32_t CFDCFCC[k_ra8_canfd_cf_count];     
  volatile uint32_t CFDCFSTS[k_ra8_canfd_cf_count];    
  volatile uint32_t CFDCFPCTR[k_ra8_canfd_cf_count];   
  volatile uint32_t CFDFESTS;                          
  volatile uint32_t CFDFFSTS;                          
  volatile uint32_t CFDFMSTS;                          
  volatile uint32_t CFDRFISTS;                         
  volatile uint8_t  CFDTMC[k_ra8_canfd_tx_mb_count];   
  volatile uint8_t  CFDTMSTS[k_ra8_canfd_tx_mb_count]; 
  volatile uint32_t CFDTMTRSTS[1];                     
  volatile uint32_t CFDTMTARSTS[1];                    
  volatile uint32_t CFDTMTCSTS[1];                     
  volatile uint32_t CFDTMTASTS[1];                     
  volatile uint32_t CFDTMIEC[1];                       
  volatile uint32_t CFDTXQCC0[1];                      
  volatile uint32_t CFDTXQSTS0[1];                     
  volatile uint32_t CFDTXQPCTR0[1];                    
  volatile uint32_t CFDTHLCC[1];                       
  volatile uint32_t CFDTHLSTS[1];                      
  volatile uint32_t CFDTHLPCTR[1];                     
  volatile uint32_t CFDGTINTSTS0;                      
  volatile uint32_t CFDGTSTCFG;                        
  volatile uint32_t CFDGTSTCTR;                        
  volatile uint32_t CFDGFDCFG;                         
  volatile uint32_t _r_after_gfdcfg;                   
  volatile uint32_t CFDGLOCKK;                         
  volatile uint32_t _r_after_glockk;                   
  volatile uint32_t CFDGAFLIGNENT;                     
  volatile uint32_t CFDGAFLIGNCTR;                     
  volatile uint32_t CFDCDTCT;                          
  volatile uint32_t CFDCDTSTS;                         
  volatile uint32_t
    _r_before_grstc[k_ra8_canfd_pad_before_grstc]; 
  volatile uint32_t CFDGRSTC;                      
  volatile uint32_t
    _r_after_grstc[k_ra8_canfd_pad_after_grstc_words]; 
 
  /* 0x100 -- per-channel CAN-FD config */
  r_canfd_cfdc2_t CFDC2[1]; 
 
  /* 0x120 -- AFL page window */
  r_canfd_cfdgafl_t
    CFDGAFL[k_ra8_canfd_afl_page_size]; 
 
  /* 0x220 -- reserved (0x60) */
  volatile uint32_t
    _r_before_rpgacc[k_ra8_canfd_pad_before_rpgacc]; 
 
  /* 0x280 -- RAM test page */
  volatile uint32_t
    CFDRPGACC[k_ra8_canfd_rpgacc_word_count]; 
 
  /* 0x380 -- reserved (0x1A0) */
  volatile uint32_t
    _r_before_rf[k_ra8_canfd_pad_before_rf_words]; 
 
  /* 0x520 -- RX FIFO access (2 fifos x 0x4C each = 0x98) */
  r_canfd_cfdrf_t CFDRF[k_ra8_canfd_rx_fifo_count]; 
 
  /* 0x5B8 -- common FIFO access (1 fifo x 0x4C) */
  r_canfd_cfdcf_t CFDCF[k_ra8_canfd_cf_count]; 
 
  /* 0x604 -- TX MB access (4 buffers x 0x4C = 0x130) */
  r_canfd_cfdtm_t CFDTM[k_ra8_canfd_tx_mb_count]; 
 
  /* 0x734 -- reserved before THL (3 words) */
  volatile uint32_t
    _r_before_thl[k_ra8_canfd_pad_before_thl_words]; 
 
  /* 0x740 -- TX history list */
  r_canfd_cfdthl_t CFDTHL[1]; 
 
  /* 0x748 -- reserved before RM cluster (118 words = 0x1D8) */
  volatile uint32_t
    _r_before_rm[k_ra8_canfd_pad_before_rm_words]; 
 
  /* 0x920 -- RX MB cluster (4 clusters x 0x400) */
  r_canfd_cfdrm_t CFDRM[k_ra8_canfd_rm_clusters]; 
} r_canfd_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_canfd_t* ra8_canfd(uint8_t channel)
{
  if (channel >= k_ra8_canfd_instance_count) {
    return nullptr;
  }
  const uintptr_t base = (channel == 0U) ? k_ra8_canfd0_base_addr : k_ra8_canfd1_base_addr;
  return (volatile r_canfd_t*)base;
}
 
/* =============================================================================
 * Channel Control (CFDC[0].CTR) bit positions
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC_Type::CTR_b`. CHMDC is 2 bits at [1:0],
 * CSLPR is bit 2, BOM at [22:21]. The previous "Lite" header had
 * CHMDC at 3 bits and CSLPR at bit 4 -- both wrong.
 */
 
typedef enum : uint8_t {
  k_ra8_cnctr_bit_chmdc = 0U,  
  k_ra8_cnctr_bit_cslpr = 2U,  
  k_ra8_cnctr_bit_bom   = 21U, 
  k_ra8_cnctr_bit_ctme  = 24U, 
  k_ra8_cnctr_bit_ctms  = 25U, 
} ra8_cnctr_bit_t;
 
typedef enum : uint32_t {
  k_ra8_cnctr_mask_chmdc = 0x3UL,        
  k_ra8_cnctr_mask_cslpr = 0x4UL,        
  k_ra8_cnctr_mask_ctme  = 1UL << 24U,   
  k_ra8_cnctr_mask_ctms  = 0x3UL << 25U, 
} ra8_cnctr_mask_t;

typedef enum : uint8_t {
  k_ra8_ctms_basic       = 0U, 
  k_ra8_ctms_listen_only = 1U, 
  k_ra8_ctms_self_test_0 = 2U, 
  k_ra8_ctms_self_test_1 = 3U, 
} ra8_ctms_mode_t;

typedef enum : uint8_t {
  k_ra8_chmdc_operation = 0U, 
  k_ra8_chmdc_reset     = 1U, 
  k_ra8_chmdc_halt      = 2U, 
  k_ra8_chmdc_keep      = 3U, 
} ra8_chmdc_mode_t;
 
/* =============================================================================
 * Channel Status (CFDC[0].STS) bit positions
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC_Type::STS_b`. TEC[31:24] and REC[23:16] live
 * here -- not in ERFL like the previous header had it.
 */
 
typedef enum : uint8_t {
  k_ra8_cnsts_bit_crstst = 0U,  
  k_ra8_cnsts_bit_chltst = 1U,  
  k_ra8_cnsts_bit_cslpst = 2U,  
  k_ra8_cnsts_bit_epst   = 3U,  
  k_ra8_cnsts_bit_bosts  = 4U,  
  k_ra8_cnsts_bit_rec    = 16U, 
  k_ra8_cnsts_bit_tec    = 24U, 
} ra8_cnsts_bit_t;
 
typedef enum : uint32_t {
  k_ra8_cnsts_mask_rec = 0xFFUL, 
  k_ra8_cnsts_mask_tec = 0xFFUL, 
} ra8_cnsts_mask_t;
 
/* =============================================================================
 * Nominal Bit-Rate Config (CFDC[0].NCFG)
 * =============================================================================
 *
 * Verified against FSP `R_CANFD_CFDC_NCFG_b` (R7KA8D2KF_core0.h
 * lines ~1018-1027): NBRP[9:0], NSJW[16:10], NTSEG1[24:17],
 * NTSEG2[31:25].
 */
 
typedef enum : uint8_t {
  k_ra8_cncfg_shift_nbrp   = 0U,  
  k_ra8_cncfg_shift_nsjw   = 10U, 
  k_ra8_cncfg_shift_ntseg1 = 17U, 
  k_ra8_cncfg_shift_ntseg2 = 25U, 
} ra8_cncfg_shift_t;
 
typedef enum : uint32_t {
  k_ra8_cncfg_mask_nbrp   = 0x3FFUL, 
  k_ra8_cncfg_mask_nsjw   = 0x7FUL,  
  k_ra8_cncfg_mask_ntseg1 = 0xFFUL,  
  k_ra8_cncfg_mask_ntseg2 = 0x7FUL,  
} ra8_cncfg_mask_t;
 
/* =============================================================================
 * Data Bit-Rate Config (CFDC2[0].DCFG) -- DIFFERENT field positions
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC2_DCFG_b`: DBRP[7:0], DTSEG1[12:8],
 * DTSEG2[19:16], DSJW[27:24]. Narrower fields than nominal.
 */
 
typedef enum : uint8_t {
  k_ra8_dcfg_shift_dbrp   = 0U,  
  k_ra8_dcfg_shift_dtseg1 = 8U,  
  k_ra8_dcfg_shift_dtseg2 = 16U, 
  k_ra8_dcfg_shift_dsjw   = 24U, 
} ra8_dcfg_shift_t;
 
typedef enum : uint32_t {
  k_ra8_dcfg_mask_dbrp   = 0xFFUL, 
  k_ra8_dcfg_mask_dtseg1 = 0x1FUL, 
  k_ra8_dcfg_mask_dtseg2 = 0xFUL,  
  k_ra8_dcfg_mask_dsjw   = 0xFUL,  
} ra8_dcfg_mask_t;

typedef enum : uint32_t {
  k_ra8_canfd_tq_per_bit         = 20U,   
  k_ra8_canfd_prescaler_min      = 1U,    
  k_ra8_canfd_prescaler_max      = 1024U, 
  k_ra8_canfd_data_prescaler_max = 256U,  
  k_ra8_canfd_sjw_max            = 16U,   
  k_ra8_canfd_dsjw_max           = 16U,   
  k_ra8_canfd_dtseg1_max         = 32U,   
  k_ra8_canfd_dtseg2_max         = 16U,   
} ra8_canfd_bit_timing_limits_t;
 
/* =============================================================================
 * Channel Error-Flag register (CFDC[0].ERFL) bit positions
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC_ERFL_b`:
 *   bit  0 BEF, 1 EWF, 2 EPF, 3 BOEF, 4 BORF, 5 OVLF, 6 BLF, 7 ALF,
 *   bit  8 SERR, 9 FERR, 10 AERR, 11 CERR, 12 B1ERR, 13 B0ERR,
 *   bit 14 ADERR,
 *   bits [30:16] CRCREG (RO).
 */
 
typedef enum : uint32_t {
  k_ra8_cnerfl_mask_bef     = 1UL << 0U,  
  k_ra8_cnerfl_mask_ewf     = 1UL << 1U,  
  k_ra8_cnerfl_mask_epf     = 1UL << 2U,  
  k_ra8_cnerfl_mask_boef    = 1UL << 3U,  
  k_ra8_cnerfl_mask_borf    = 1UL << 4U,  
  k_ra8_cnerfl_mask_ovlf    = 1UL << 5U,  
  k_ra8_cnerfl_mask_blf     = 1UL << 6U,  
  k_ra8_cnerfl_mask_alf     = 1UL << 7U,  
  k_ra8_cnerfl_mask_serr    = 1UL << 8U,  
  k_ra8_cnerfl_mask_ferr    = 1UL << 9U,  
  k_ra8_cnerfl_mask_aerr    = 1UL << 10U, 
  k_ra8_cnerfl_mask_cerr    = 1UL << 11U, 
  k_ra8_cnerfl_mask_b1err   = 1UL << 12U, 
  k_ra8_cnerfl_mask_b0err   = 1UL << 13U, 
  k_ra8_cnerfl_mask_aderr   = 1UL << 14U, 
  k_ra8_cnerfl_mask_all_w1c = 0x7FFFUL,   
} ra8_cnerfl_mask_t;
 
/* =============================================================================
 * Global Control (CFDGCTR)
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDGCTR_b`: GMDC[1:0], GSLPR bit 2.
 */
 
typedef enum : uint8_t {
  k_ra8_gctr_bit_gmdc  = 0U, 
  k_ra8_gctr_bit_gslpr = 2U, 
} ra8_gctr_bit_t;
 
typedef enum : uint32_t {
  k_ra8_gctr_mask_gmdc       = 0x3UL,     
  k_ra8_gctr_mask_gslpr      = 1UL << 2U, 
  k_ra8_gctr_value_operation = 0UL,       
  k_ra8_gctr_value_reset     = 1UL,       
  k_ra8_gctr_value_halt      = 2UL,       
} ra8_gctr_value_t;

typedef enum : uint8_t {
  k_ra8_gsts_bit_grststs  = 0U, 
  k_ra8_gsts_bit_ghltsts  = 1U, 
  k_ra8_gsts_bit_gslpsts  = 2U, 
  k_ra8_gsts_bit_graminit = 3U, 
} ra8_gsts_bit_t;
 
/* =============================================================================
 * RX FIFO config / status / control (CFDRFCC, CFDRFSTS, CFDRFPCTR)
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDRFCC_b` and `R_CANFD_CFDRFSTS_b`.
 */
 
typedef enum : uint32_t {
  k_ra8_rfcc_bit_rfe  = 1UL << 0U, 
  k_ra8_rfcc_bit_rfie = 1UL << 1U, 
} ra8_rfcc_bits_t;
 
typedef enum : uint32_t {
  k_ra8_rfsts_bit_empty = 1UL << 0U, 
  k_ra8_rfsts_bit_full  = 1UL << 1U, 
  k_ra8_rfsts_bit_mlt   = 1UL << 2U, 
  k_ra8_rfsts_bit_if    = 1UL << 3U, 
} ra8_rfsts_bits_t;
 
typedef enum : uint32_t {
  k_ra8_rfpctr_value_ack = 0xFFUL, 
} ra8_rfpctr_bits_t;
 
/* =============================================================================
 * Acceptance-filter control (CFDGAFLECTR)
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDGAFLECTR_b`: AFLPN[3:0] page index, bit 8 AFLDAE
 * unlocks data access.
 */
 
typedef enum : uint32_t {
  k_ra8_gaflectr_mask_aflpn = 0xFUL,     
  k_ra8_gaflectr_bit_afldae = 1UL << 8U, 
} ra8_gaflectr_bits_t;

typedef enum : uint32_t {
  k_ra8_gaflcfg0_shift_rnc0 = 16U,   
  k_ra8_gaflcfg0_mask_rnc0  = 0x1FU, 
} ra8_gaflcfg0_bits_t;

typedef enum : uint32_t {
  k_ra8_gaflp1_bit_gaflfdp0 = 1UL << 0U, 
} ra8_gaflp1_bits_t;

typedef enum : uint32_t {
  k_ra8_gaflm_bit_gafllb   = 1UL << 29U, 
  k_ra8_gaflm_bit_gaflrtrm = 1UL << 30U, 
  k_ra8_gaflm_bit_gaflidem = 1UL << 31U, 
} ra8_gaflm_bits_t;

typedef enum : uint16_t {
  k_ra8_canfd_afl_total = (uint16_t)(16U * 16U), 
} ra8_canfd_afl_total_t;

typedef enum : uint32_t {
  k_ra8_gfdcfg_bit_niso = 1UL << 0U, 
} ra8_canfd_gfdcfg_bits_t;
 
/* =============================================================================
 * Message-ID layout (CFDRF.ID / CFDTM.ID / CFDCF.ID / CFDRM.ID)
 * =============================================================================
 *
 * Common across RX FIFO, TX MB, common FIFO and RX MB:
 *   [28:0]  raw ID (29-bit extended or 11-bit standard right-aligned)
 *   [29]    THLEN (TX) / GAFLLB (AFL) / reserved (RX)
 *   [30]    RTR
 *   [31]    IDE (1 = extended)
 */
typedef enum : uint32_t {
  k_ra8_canfd_id_std_mask = 0x000007FFUL, 
  k_ra8_canfd_id_ext_mask = 0x1FFFFFFFUL, 
  k_ra8_canfd_id_thlen    = 1UL << 29U,   
  k_ra8_canfd_id_rtr      = 1UL << 30U,   
  k_ra8_canfd_id_ide      = 1UL << 31U,   
} ra8_canfd_id_bits_t;
 
/* =============================================================================
 * FD-status layout (CFDTM.FDCTR / CFDRF.FDSTS / CFDCF.FDSTS / CFDRM.FDSTS)
 * =============================================================================
 *
 * From FSP unions: bit 0 = ESI, bit 1 = BRS, bit 2 = FDF.
 * Note this is DIFFERENT from the previous Lite header which had FDF
 * at bit 0 -- that was wrong.
 */
 
typedef enum : uint32_t {
  k_ra8_canfd_fd_esi = 1UL << 0U, 
  k_ra8_canfd_fd_brs = 1UL << 1U, 
  k_ra8_canfd_fd_fdf = 1UL << 2U, 
} ra8_canfd_fd_bits_t;
 
/* =============================================================================
 * PTR layout (CFDTM.PTR / CFDRF.PTR / CFDCF.PTR / CFDRM.PTR)
 * =============================================================================
 *
 * [15:0]   timestamp,  [31:28] DLC.
 */
typedef enum : uint8_t {
  k_ra8_canfd_ptr_shift_dlc = 28U, 
} ra8_canfd_ptr_shift_t;
 
typedef enum : uint32_t {
  k_ra8_canfd_ptr_mask_dlc = 0xFUL, 
} ra8_canfd_ptr_mask_t;
 
/* =============================================================================
 * TX message-buffer control byte (CFDTMC[i])
 * =============================================================================
 *
 * Single byte per buffer: TMTR (bit 0), TMTAR (bit 1), TMOM (bit 2).
 */
typedef enum : uint8_t {
  k_ra8_canfd_tmc_txreq   = 1U << 0U, 
  k_ra8_canfd_tmc_abort   = 1U << 1U, 
  k_ra8_canfd_tmc_oneshot = 1U << 2U, 
} ra8_canfd_tmc_bits_t;
 
/* =============================================================================
 * CAN-FD Config register (CFDC2[0].FDCFG) -- TDC fields
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC2_FDCFG_b` (R7KA8D2KF_core0.h):
 *   bits [2:0]   EOCCFG  Error-Occurrence Counter Config
 *   bits [7:3]   reserved
 *   bits [14:8]  TDCO    Transmitter Delay Compensation Offset (7-bit)
 *   bit  [15]    TDCOC   TDC Offset Control (0=measured FDSTS.TDCR, 1=TDCO)
 *   bit  [16]    TDE     Transmitter Delay Compensation Enable
 *   bit  [17]    reserved
 *   bit  [18]    FDOE    FD-Only Enable
 *   bit  [19]    REFE    RX Edge Filter Enable
 *   bit  [20]    CLOE    CAN Classic-frame Loopback Enable
 *   bits [23:21] reserved
 *   bit  [24]    ESIC    Error State Indication Configuration
 *   bits [31:25] reserved
 *
 * HUM Ch 41 "CFDCnFDCFG" p 2788.
 */

typedef enum : uint8_t {
  k_ra8_fdcfg_shift_tdco  = 8U,  
  k_ra8_fdcfg_shift_tdcoc = 15U, 
  k_ra8_fdcfg_shift_tde   = 16U, 
} ra8_fdcfg_shift_t;

typedef enum : uint32_t {
  k_ra8_fdcfg_mask_tdco  = 0x7FUL,     
  k_ra8_fdcfg_mask_tdcoc = 1UL << 15U, 
  k_ra8_fdcfg_mask_tde   = 1UL << 16U, 
} ra8_fdcfg_mask_t;

typedef enum : uint8_t {
  k_ra8_canfd_tdc_offset_max = 127U, 
} ra8_canfd_tdc_limits_t;
 
/* =============================================================================
 * CAN-FD Status register (CFDC2[0].FDSTS) -- TDC result field
 * =============================================================================
 *
 * From FSP `R_CANFD_CFDC2_FDSTS_b`:
 *   bits [7:0]  TDCR    Measured TDC result in time quanta (read-only)
 *   bit  [8]    EOCO    Error-Occurrence Counter Overflow
 *   bit  [9]    SOCO    Stuff-bit Counter Overflow
 *
 * After TDE is set the controller writes the measured transmitter loop
 * delay (in TQ units) into FDSTS.TDCR[7:0] after the first successful
 * data-phase bit. HUM Ch 41 "CFDCnFDSTS" p 2792.
 */

typedef enum : uint32_t {
  k_ra8_fdsts_mask_tdcr = 0xFFUL, 
} ra8_fdsts_mask_t;
 
#ifdef __cplusplus
}
#endif