ra8_cgc_eswclk.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_cgc.h"
#include "ra8_cgc_internal.h"
#include "ra8_cgc_regs.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_hw_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_register_protection.h"
#include "ra8_system_regs.h"
#include "ra8_time_constants.h"
 
static const char* s_tag = "CGC";
 
typedef enum : uint8_t {
  k_ra8_eswckdivcr_div1  = 0U, 
  k_ra8_eswckdivcr_div2  = 1U, 
  k_ra8_eswckdivcr_div4  = 2U, 
  k_ra8_eswckdivcr_div8  = 3U, 
  k_ra8_eswckdivcr_div16 = 4U, 
  k_ra8_eswckdivcr_div32 = 5U, 
  k_ra8_eswckdivcr_div64 = 6U, 
} ra8_cgc_eswckdivcr_t;

typedef enum : uint32_t {
  k_ra8_cgc_eswclk_target_hz    = 250000000UL, 
  k_ra8_cgc_eswphyclk_target_hz = 500000000UL, 
  k_ra8_cgc_eswclk_poll_limit   = 200000U,     
} ra8_cgc_eswclk_const_t;

static uint32_t s_eswclk_hz = 0U;

RA8_INTERNAL static ra8_err_t internal_wait_cksrdy(volatile const uint8_t* ckcr_reg,
                                                   uint8_t                 expected)
{
  const uint8_t mask = (uint8_t)(1U << k_ra8_eswckcr_bit_srdy);
  /* Bounded wait through ra8_hw_err.h: on host tests the ra8_fake_mmio
   * seam decides the poll (first-poll success unless a test arms a
   * fault), so the real timeout leg is reachable everywhere. */
  if (expected != 0U) {
    return ra8_hw_wait_flag_set8(ckcr_reg, mask, (uint32_t)k_ra8_cgc_eswclk_poll_limit);
  }
  return ra8_hw_wait_flag_clear8(ckcr_reg, mask, (uint32_t)k_ra8_cgc_eswclk_poll_limit);
}

RA8_INTERNAL static ra8_err_t internal_switch_eswcr_to_pll1p(volatile uint8_t* ckcr_reg,
                                                             volatile uint8_t* divcr_reg,
                                                             uint8_t           div_code)
{
  const uint8_t sreq_mask = (uint8_t)(1U << k_ra8_eswckcr_bit_sreq);
  const uint8_t srdy_mask = (uint8_t)(1U << k_ra8_eswckcr_bit_srdy);
  /* FSP `bsp_clocks.c` ::bsp_peripheral_clock_set sequence:
   *   1. Set SREQ=1 (preserve current SEL via read-modify-write).
   *   2. Spin-wait SRDY=1.
   *   3. Programme CKDIVCR (peripheral clock now stopped).
   *   4. Write `source | SREQ | SRDY`. Writing SRDY in the same word
   *      is mandatory per FSP (bsp_clocks.c line 2896); without it
   *      the subsequent SREQ-clear hangs.
   *   5. Clear SREQ -> peripheral clock starts.
   *   6. Spin-wait SRDY=0 (start acknowledged).                       */
  *ckcr_reg     = (uint8_t)(*ckcr_reg | sreq_mask);
  ra8_err_t err = internal_wait_cksrdy(ckcr_reg, 1U);
  if (err != k_ra8_ok) {
    return err;
  }
  *divcr_reg        = div_code;
  const uint8_t src = (uint8_t)((uint8_t)k_ra8_eswcksel_pll1p & k_ra8_eswckcr_mask_sel);
  *ckcr_reg         = (uint8_t)(src | sreq_mask | srdy_mask);
  *ckcr_reg         = (uint8_t)(*ckcr_reg & (uint8_t)~sreq_mask);
  return internal_wait_cksrdy(ckcr_reg, 0U);
}

RA8_INTERNAL static ra8_err_t internal_wait_pdctreswm_clear(uint8_t bit)
{
  volatile const uint8_t* const pd   = ra8_sys_pdctreswm();
  const uint8_t                 mask = (uint8_t)(1U << bit);
  /* Bounded wait through ra8_hw_err.h: on host tests the ra8_fake_mmio
   * seam decides the poll, so the stuck-flag timeout leg is testable. */
  return ra8_hw_wait_flag_clear8(pd, mask, (uint32_t)k_ra8_cgc_eswclk_poll_limit);
}

RA8_INTERNAL static ra8_err_t internal_eswclk_power_on_domain(void)
{
  RA8_PROTECTED_WRITE(k_ra8_prcr_unlock_lpm)
  {
    volatile uint8_t* const pd = ra8_sys_pdctreswm();
    /* Only kick the power-on path if the domain is currently gated --
     * PDCSF=0 and PDPGSF=1 is the FSP-canonical "power off" signature. */
    const uint8_t state = *pd;
    if (((state & (1U << k_ra8_pdctr_bit_pdcsf)) == 0U) &&
        ((state & (1U << k_ra8_pdctr_bit_pdpgsf)) != 0U)) {
      *pd = (uint8_t)(state & (uint8_t)~(1U << k_ra8_pdctr_bit_pdde));
    }
  }
  /* Wait for power-on outside the PRCR window (the status flags are
   * read-only and not protected). */
  ra8_err_t err = internal_wait_pdctreswm_clear(k_ra8_pdctr_bit_pdcsf);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "eswclk: PDCSF stuck");
    return err;
  }
  err = internal_wait_pdctreswm_clear(k_ra8_pdctr_bit_pdpgsf);
  if (err != k_ra8_ok) {
    ra8_log_error(s_tag, "eswclk: PDPGSF stuck");
    return err;
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_eswclk_program_cks(void)
{
  ra8_err_t err = k_ra8_ok;
  RA8_PROTECTED_WRITE(k_ra8_prcr_unlock_cgc)
  {
    err = internal_switch_eswcr_to_pll1p(ra8_sys_eswckcr(),
                                         ra8_sys_eswckdivcr(),
                                         (uint8_t)k_ra8_eswckdivcr_div4);
    if (err != k_ra8_ok) {
      ra8_log_error(s_tag, "eswclk: ESWCKCR handshake timeout");
      break;
    }
    err = internal_switch_eswcr_to_pll1p(ra8_sys_eswpckcr(),
                                         ra8_sys_eswpckdivcr(),
                                         (uint8_t)k_ra8_eswckdivcr_div2);
    if (err != k_ra8_ok) {
      ra8_log_error(s_tag, "eswclk: ESWPCKCR handshake timeout");
      break;
    }
  }
  return err;
}
 
ra8_err_t ra8_cgc_eswclk_init(void)
{
  ra8_log_info(s_tag, "eswclk init (PLL1P/4 = 250 MHz, eswphyclk PLL1P/2 = 500 MHz)");
 
  /* Step 1: ESWCKCR / ESWPCKCR / USBCKCR / USB60CKCR all share the same
   * CKSEL reset-default (HOCO) and the same SREQ -> SRDY handshake
   * plumbing -- HOCO MUST be running before the SREQ is raised. */
  const ra8_err_t hoco_err = priv_ra8_cgc_ensure_hoco_running_for_usb_ck();
  if (hoco_err != k_ra8_ok) {
    ra8_log_error(s_tag, "eswclk: HOCO stabilization timeout");
    return hoco_err;
  }
  /* Step 2: turn on the ESWM peripheral power domain. */
  const ra8_err_t pd_err = internal_eswclk_power_on_domain();
  if (pd_err != k_ra8_ok) {
    return pd_err;
  }
  /* Step 3: release the MSTPC28 ETHPHYCLK module-stop gate. */
  const ra8_err_t ethphy_mst_err = ra8_mstp_enable(k_ra8_mstp_ethphyclk);
  if (ethphy_mst_err != k_ra8_ok) {
    ra8_log_error(s_tag, "eswclk: ethphyclk MSTP release failed");
    return ethphy_mst_err;
  }
  /* Step 4: switch ESWCKCR + ESWPCKCR to PLL1P. */
  const ra8_err_t cks_err = internal_eswclk_program_cks();
  if (cks_err != k_ra8_ok) {
    return cks_err;
  }
  s_eswclk_hz = (uint32_t)k_ra8_cgc_eswclk_target_hz;
  ra8_log_info(s_tag, "eswclk ready");
  return k_ra8_ok;
}
 
ra8_err_t ra8_cgc_eswclk_hz(uint32_t* out_hz)
{
  if (out_hz == nullptr) {
    return k_ra8_err_null_ptr;
  }
  *out_hz = s_eswclk_hz;
  return k_ra8_ok;
}