- Generated by
1.16.1
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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Cross-TU sharing for the split Clock Generation Circuit driver. More...
Go to the source code of this file.
Enumerations | |
| enum | ra8_cgc_byte_const_t : uint32_t { k_ra8_cgc_quarters_per_unit = 4UL , k_ra8_cgc_hz_per_mhz = 1000000UL , k_ra8_cgc_mr_min_hz = 1UL } |
| Bit-width / Hz-conversion constants used across the CGC driver. More... | |
Functions | |
| ra8_err_t | priv_ra8_cgc_wait_oscsf_set (uint8_t bit) |
| Bounded poll on a single OSCSF flag becoming set. | |
| ra8_err_t | priv_ra8_cgc_wait_oscsf_clear (uint8_t bit) |
| Bounded poll on a single OSCSF flag becoming clear. | |
| ra8_err_t | priv_ra8_cgc_ensure_hoco_running_for_usb_ck (void) |
| Ensure HOCO is running so a USBCKCR/USB60CKCR/ESWCKCR SREQ->SRDY handshake can drain. | |
Cross-TU sharing for the split Clock Generation Circuit driver.
The CGC driver is split across several translation units that all live in libs/ra8_hal/src/:
Any symbol referenced by more than one of those units is declared here so there is exactly one definition and no implicit cross-TU reference. The bounded OSCSF poll helpers and the HOCO-restart helper live in this seam because the USB and ESW paths reuse the same hardware handshakes the core bring-up established. The shared k_ra8_cgc_quarters_per_unit PLL-multiplier scale factor is the only member of ra8_cgc_byte_const_t referenced from more than one unit, so the whole enum block lives here.
This header is internal to the CGC driver – it is NOT a public API and must not be included outside libs/ra8_hal/src/ra8_cgc*.c.
Definition in file ra8_cgc_internal.h.
| enum ra8_cgc_byte_const_t : uint32_t |
Bit-width / Hz-conversion constants used across the CGC driver.
k_ra8_cgc_quarters_per_unit is referenced by both the core PLL1 path (ra8_cgc.c) and the PLL2 path (ra8_cgc_usb.c), so the whole block lives in this shared seam. The two Hz-conversion members are used only by the MRMS wait-state stage in ra8_cgc.c, but they ride along so the multiplier scale factor keeps its documented neighbours.
| Enumerator | |
|---|---|
| k_ra8_cgc_quarters_per_unit | PLL multiplier 0.25 step. |
| k_ra8_cgc_hz_per_mhz | Hz per MHz. |
| k_ra8_cgc_mr_min_hz | Below this, MR*FREQ field = 0. |
Definition at line 56 of file ra8_cgc_internal.h.
| ra8_err_t priv_ra8_cgc_ensure_hoco_running_for_usb_ck | ( | void | ) |
Ensure HOCO is running so a USBCKCR/USB60CKCR/ESWCKCR SREQ->SRDY handshake can drain.
USBCKCR / USB60CKCR / ESWCKCR all share HOCO as their reset-default source. The SREQ -> SRDY synchronizer chain crosses from ICLK into the CURRENT clock source's domain (HOCO at boot). If HOCO is stopped (HCSTP = 1) the handshake never completes. ra8_cgc_init leaves HOCO stopped because it switches SCKSCR to PLL1, so this helper restarts HOCO under a PRCR-CGC unlock window (HOCOCR IS PRCR-protected; writes outside the window are silently dropped) and then waits OSCSF.HOCOSF outside the PRCR window (read-only). Defined in ra8_cgc_usb.c and reused by ra8_cgc_eswclk.c.
| k_ra8_ok | HOCO running, OSCSF.HOCOSF asserted. |
| k_ra8_err_hw_timeout | HOCOSF never asserted. |
Definition at line 564 of file ra8_cgc_usb.c.
References k_ra8_hococr_hcstp, k_ra8_oscsf_bit_hocosf, k_ra8_prcr_unlock_cgc, priv_ra8_cgc_wait_oscsf_set(), RA8_PROTECTED_WRITE, and ra8_sys_hococr().
Referenced by ra8_cgc_eswclk_init(), and ra8_cgc_usbhs_pll_enable().
| ra8_err_t priv_ra8_cgc_wait_oscsf_clear | ( | uint8_t | bit | ) |
Bounded poll on a single OSCSF flag becoming clear.
Shared between the core PLL1 bring-up (ra8_cgc.c) and the PLL2 path (ra8_cgc_usb.c). Spins up to k_ra8_cgc_pll_spin_limit iterations.
| [in] | bit | OSCSF bit number to wait on. |
| k_ra8_ok | Flag observed clear. |
| k_ra8_err_hw_timeout | Spin limit exhausted. |
Definition at line 243 of file ra8_cgc.c.
References k_ra8_cgc_pll_spin_limit, ra8_hw_wait_flag_clear8(), and ra8_sys_oscsf().
Referenced by internal_pll2_program_protected(), and internal_stop_pll1().
| ra8_err_t priv_ra8_cgc_wait_oscsf_set | ( | uint8_t | bit | ) |
Bounded poll on a single OSCSF flag becoming set.
Shared between the core PLL1 bring-up (ra8_cgc.c) and the PLL2 / USB paths (ra8_cgc_usb.c). Spins up to k_ra8_cgc_osc_spin_limit iterations.
| [in] | bit | OSCSF bit number to wait on (e.g. k_ra8_oscsf_bit_pll1sf). |
| k_ra8_ok | Flag observed set. |
| k_ra8_err_hw_timeout | Spin limit exhausted. |
Definition at line 233 of file ra8_cgc.c.
References k_ra8_cgc_osc_spin_limit, ra8_hw_wait_flag_set8(), and ra8_sys_oscsf().
Referenced by internal_pll2_program_protected(), internal_program_and_start_pll1(), internal_start_main_osc(), priv_ra8_cgc_ensure_hoco_running_for_usb_ck(), ra8_cgc_usbfs_clock_enable(), ra8_cgc_usbhs_pll_enable(), and ra8_cgc_use_hoco().
1.16.1