ra8_lpm_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
 
/* =============================================================================
 * Base addresses
 * =============================================================================
 */

typedef enum : uintptr_t {
  k_ra8_lpm_sysc_base_addr = 0x4001E000UL, 
  k_ra8_lpm_icu_base_addr  = 0x4000C000UL, 
} ra8_lpm_addr_t;
 
/* =============================================================================
 * Register offsets
 * =============================================================================
 */

typedef enum : uint16_t {
  /* --- SYSC: lifecycle + LPSCR ---------------------------------------- */
  k_ra8_lpm_sbycr_off   = 0x00CU, 
  k_ra8_lpm_lpscr_off   = 0xA90U, 
  k_ra8_lpm_sscr1_off   = 0xA98U, 
  k_ra8_lpm_dpsbycr_off = 0xA00U, 
  k_ra8_lpm_opccr_off   = 0x0A0U, 
 
  /* --- SYSC: PRCR (16-bit, write-protect key) ------------------------- */
  k_ra8_lpm_prcr_off = 0x3FAU, 
 
  /* --- SYSC: RAM retention ------------------------------------------- */
  k_ra8_lpm_pdramscr0_off = 0x140U, 
  k_ra8_lpm_pdramscr1_off = 0x142U, 
 
  /* --- SYSC: LDO standby --------------------------------------------- */
  k_ra8_lpm_pll1ldocr_off = 0xB04U, 
  k_ra8_lpm_pll2ldocr_off = 0xB08U, 
  k_ra8_lpm_hocoldocr_off = 0xB0CU, 
 
  /* --- SYSC: deep-standby cancel (DPSIER0..3 / DPSIFR0..3 / DPSIEGR0..2) */
  k_ra8_lpm_dpsier0_off = 0xA08U, 
  k_ra8_lpm_dpsier1_off = 0xA0CU, 
  k_ra8_lpm_dpsier2_off = 0xA10U, 
  k_ra8_lpm_dpsier3_off = 0xA14U, 
 
  k_ra8_lpm_dpsifr0_off = 0xA18U, 
  k_ra8_lpm_dpsifr1_off = 0xA1CU, 
  k_ra8_lpm_dpsifr2_off = 0xA20U, 
  k_ra8_lpm_dpsifr3_off = 0xA24U, 
 
  k_ra8_lpm_dpsiegr0_off = 0xA28U, 
  k_ra8_lpm_dpsiegr1_off = 0xA2CU, 
  k_ra8_lpm_dpsiegr2_off = 0xA30U, 
 
  /* --- SYSC: power-domain gating control ------------------------------ */
  k_ra8_lpm_pdctrgd_off = 0x110U, 
 
  /* --- SYSC: per-oscillator stop bits (CGC sub-block, same SYSC base) -- */
  k_ra8_lpm_mosccr_off = 0x032U, 
  k_ra8_lpm_hococr_off = 0x036U, 
  k_ra8_lpm_mococr_off = 0x038U, 
  k_ra8_lpm_lococr_off = 0x400U, 
  k_ra8_lpm_sosccr_off = 0xC00U, 
 
  /* --- ICU: WUPEN0/WUPEN1 (32-bit) ----------------------------------- */
  k_ra8_lpm_wupen0_off = 0x1A0U, 
  k_ra8_lpm_wupen1_off = 0x1A4U, 
} ra8_lpm_off_t;
 
/* =============================================================================
 * Sleep mode (LPSCR.LPMD encoding)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_sleep_mode_sleep          = 0U,   
  k_ra8_sleep_mode_deep_sleep     = 2U,   
  k_ra8_sleep_mode_software_std   = 0x5U, 
  k_ra8_sleep_mode_deep_standby_1 = 0x8U, 
  k_ra8_sleep_mode_deep_standby_2 = 0x9U, 
  k_ra8_sleep_mode_deep_standby_3 = 0xAU, 
} ra8_sleep_mode_t;
 
/* =============================================================================
 * Bit fields and masks
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_lpm_sbycr_ope_mask  = 0x40U, 
  k_ra8_lpm_sbycr_reset_val = 0x40U, 
} ra8_lpm_sbycr_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_dpsbycr_dcssmode_shift = 2U,    
  k_ra8_lpm_dpsbycr_dcssmode_mask  = 0x0CU, 
  k_ra8_lpm_dpsbycr_iokeep_mask    = 0x40U, 
  k_ra8_lpm_dpsbycr_reset_val      = 0x14U, 
} ra8_lpm_dpsbycr_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_dcssmode_128us = 0x1U, 
  k_ra8_lpm_dcssmode_256us = 0x2U, 
  k_ra8_lpm_dcssmode_512us = 0x3U, 
} ra8_lpm_dcssmode_t;

typedef enum : uint8_t {
  k_ra8_lpm_sscr1_ss2fr_mask  = 0x01U, 
  k_ra8_lpm_sscr1_ss2lp_shift = 2U,    
  k_ra8_lpm_sscr1_ss2lp_mask  = 0x0CU, 
} ra8_lpm_sscr1_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_ss2lp_default = 0x0U, 
  k_ra8_lpm_ss2lp_low     = 0x1U, 
} ra8_lpm_sscr1_ss2lp_t;

typedef enum : uint8_t {
  k_ra8_lpm_lpscr_lpmd_mask = 0x0FU, 
} ra8_lpm_lpscr_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_opccr_opcm_mask   = 0x03U, 
  k_ra8_lpm_opccr_opcmtsf_msk = 0x10U, 
} ra8_lpm_opccr_bits_t;

typedef enum : uint16_t {
  k_ra8_lpm_prcr_key      = 0xA500U, 
  k_ra8_lpm_prcr_prc0_msk = 0x0001U, 
  k_ra8_lpm_prcr_prc1_msk = 0x0002U, 
  k_ra8_lpm_prcr_prc2_msk = 0x0008U, 
} ra8_lpm_prcr_bits_t;

typedef enum : uint16_t {
  k_ra8_lpm_pdramscr0_sram0_keep = 0x000FU, 
  k_ra8_lpm_pdramscr0_sram1_keep = 0x00F0U, 
  k_ra8_lpm_pdramscr0_sram2_keep = 0x0F00U, 
  k_ra8_lpm_pdramscr0_sram3_keep = 0x1000U, 
  k_ra8_lpm_pdramscr0_all_keep   = 0x1FFFU, 
  k_ra8_lpm_pdramscr0_writable   = 0x7FFFU, 
} ra8_lpm_pdramscr0_groups_t;

typedef enum : uint8_t {
  k_ra8_lpm_pdramscr1_rkeep0_mask = 0x01U, 
  k_ra8_lpm_pdramscr1_rkeep1_mask = 0x02U, 
} ra8_lpm_pdramscr1_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_ldocr_ldostp_mask = 0x01U, 
  k_ra8_lpm_ldocr_skeep_mask  = 0x02U, 
  k_ra8_lpm_ldocr_skeep_shift = 1U,    
} ra8_lpm_ldocr_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_ldo_disabled = 0U, 
  k_ra8_lpm_ldo_retained = 1U, 
} ra8_lpm_ldo_state_t;

typedef enum : uint8_t {
  k_ra8_lpm_clock_stop_mask = 0x01U, 
} ra8_lpm_clock_stop_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_pdctr_pdde_mask   = 0x01U, 
  k_ra8_lpm_pdctr_pdcsf_mask  = 0x40U, 
  k_ra8_lpm_pdctr_pdpgsf_mask = 0x80U, 
} ra8_lpm_pdctr_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_dpsier_idx_0 = 0U, 
  k_ra8_lpm_dpsier_idx_1 = 1U, 
  k_ra8_lpm_dpsier_idx_2 = 2U, 
  k_ra8_lpm_dpsier_idx_3 =
    3U, 
  k_ra8_lpm_dpsier_idx_count = 4U,
} ra8_lpm_dpsier_idx_t;

typedef enum : uint8_t {
  k_ra8_lpm_dpsier2_dpvd1ie_mask = 0x01U, 
  k_ra8_lpm_dpsier2_dpvd2ie_mask = 0x02U, 
  k_ra8_lpm_dpsier2_drtciie_mask = 0x04U, 
  k_ra8_lpm_dpsier2_drtcaie_mask = 0x08U, 
  k_ra8_lpm_dpsier2_dnmie_mask   = 0x10U, 
} ra8_lpm_dpsier2_bits_t;

typedef enum : uint8_t {
  k_ra8_lpm_dpsier3_dusbfsie_mask  = 0x01U, 
  k_ra8_lpm_dpsier3_dusbhsie_mask  = 0x02U, 
  k_ra8_lpm_dpsier3_dulpt0ie_mask  = 0x04U, 
  k_ra8_lpm_dpsier3_dulpt1ie_mask  = 0x08U, 
  k_ra8_lpm_dpsier3_diwdtie_mask   = 0x20U, 
  k_ra8_lpm_dpsier3_dsostdie_mask  = 0x40U, 
  k_ra8_lpm_dpsier3_dvbattadie_msk = 0x80U, 
} ra8_lpm_dpsier3_bits_t;

typedef enum : uint32_t {
  k_ra8_lpm_wupen0_irq0    = 1UL << 0,              
  k_ra8_lpm_wupen0_irq1    = 1UL << 1,              
  k_ra8_lpm_wupen0_irq2    = 1UL << 2,              
  k_ra8_lpm_wupen0_irq3    = 1UL << 3,              
  k_ra8_lpm_wupen0_irq4    = 1UL << 4,              
  k_ra8_lpm_wupen0_irq5    = 1UL << 5,              
  k_ra8_lpm_wupen0_irq6    = 1UL << 6,              
  k_ra8_lpm_wupen0_irq7    = 1UL << 7,              
  k_ra8_lpm_wupen0_iwdt    = 1UL << 16,             
  k_ra8_lpm_wupen0_pvd1    = 1UL << 18,             
  k_ra8_lpm_wupen0_pvd2    = 1UL << 19,             
  k_ra8_lpm_wupen0_vbatt   = 1UL << 20,             
  k_ra8_lpm_wupen0_rtcalm  = 1UL << 24,             
  k_ra8_lpm_wupen0_rtcprd  = 1UL << 25,             
  k_ra8_lpm_wupen0_usbhs   = 1UL << 26,             
  k_ra8_lpm_wupen0_usbfs   = 1UL << 27,             
  k_ra8_lpm_wupen0_agt1ud  = 1UL << 28,             
  k_ra8_lpm_wupen0_agt1ca  = 1UL << 29,             
  k_ra8_lpm_wupen0_agt1cb  = 1UL << 30,             
  k_ra8_lpm_wupen0_riic0   = 1UL << 31,             
  k_ra8_lpm_wupen0_acmphs0 = k_ra8_lpm_wupen0_pvd1, 
} ra8_lpm_wupen0_bits_t;

typedef enum : uint32_t {
  k_ra8_lpm_wupen1_comphs0 = 1UL << 3,  
  k_ra8_lpm_wupen1_sosc    = 1UL << 7,  
  k_ra8_lpm_wupen1_ulpt0u  = 1UL << 8,  
  k_ra8_lpm_wupen1_ulpt0a  = 1UL << 9,  
  k_ra8_lpm_wupen1_ulpt0b  = 1UL << 10, 
  k_ra8_lpm_wupen1_i3c0    = 1UL << 11, 
  k_ra8_lpm_wupen1_ulpt1u  = 1UL << 12, 
  k_ra8_lpm_wupen1_ulpt1a  = 1UL << 13, 
  k_ra8_lpm_wupen1_ulpt1b  = 1UL << 14, 
  k_ra8_lpm_wupen1_pdm     = 1UL << 15, 
} ra8_lpm_wupen1_bits_t;

typedef enum : uintptr_t {
  k_ra8_lpm_scb_scr_addr = 0xE000ED10UL, 
} ra8_lpm_scb_t;

typedef enum : uint32_t {
  k_ra8_lpm_scb_scr_sleepdeep = 0x4UL, 
} ra8_lpm_scb_field_t;
 
/* =============================================================================
 * Inline accessors
 * =============================================================================
 */

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_lpm_scb_scr(void)
{
  return (volatile uint32_t*)k_ra8_lpm_scb_scr_addr;
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint8_t* ra8_lpm_sysc_reg8(ra8_lpm_off_t off)
{
  return (volatile uint8_t*)(k_ra8_lpm_sysc_base_addr + (uintptr_t)off);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint16_t* ra8_lpm_sysc_reg16(ra8_lpm_off_t off)
{
  return (volatile uint16_t*)(k_ra8_lpm_sysc_base_addr + (uintptr_t)off);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_lpm_icu_reg32(ra8_lpm_off_t off)
{
  return (volatile uint32_t*)(k_ra8_lpm_icu_base_addr + (uintptr_t)off);
}
 
#ifdef __cplusplus
}
#endif